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sim: sim_halfword: new, handle HLL/HLLI/XHLLI/HLLM/HLLS, add unit tests
This commit is contained in:
Mikael Pettersson
@@ -317,6 +317,10 @@ dispatch(Core, Mem, IR, EA) ->
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8#475 -> sim_boolean:handle_SETO(Core, Mem, IR, EA); % SETOI = SETO
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8#476 -> sim_boolean:handle_SETOM(Core, Mem, IR, EA);
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8#477 -> sim_boolean:handle_SETOB(Core, Mem, IR, EA);
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8#500 -> sim_halfword:handle_HLL(Core, Mem, IR, EA);
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8#501 -> sim_halfword:handle_HLLI(Core, Mem, IR, EA); % XHLLI in non-zero sections
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8#502 -> sim_halfword:handle_HLLM(Core, Mem, IR, EA);
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8#503 -> sim_halfword:handle_HLLS(Core, Mem, IR, EA);
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_ ->
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PC = (Core#core.pc_section bsl 18) bor Core#core.pc_offset,
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{Core, Mem, {error, {?MODULE, {dispatch, PC, IR, EA}}}}
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115
erlang/apps/sim/src/sim_halfword.erl
Normal file
115
erlang/apps/sim/src/sim_halfword.erl
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@@ -0,0 +1,115 @@
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%%% -*- erlang-indent-level: 2 -*-
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%%%
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%%% simulator for pdp10-elf
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%%% Copyright (C) 2020 Mikael Pettersson
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%%%
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%%% This file is part of pdp10-tools.
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%%%
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%%% pdp10-tools is free software: you can redistribute it and/or modify
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%%% it under the terms of the GNU General Public License as published by
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%%% the Free Software Foundation, either version 3 of the License, or
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%%% (at your option) any later version.
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%%%
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%%% pdp10-tools is distributed in the hope that it will be useful,
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%%% but WITHOUT ANY WARRANTY; without even the implied warranty of
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%%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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%%% GNU General Public License for more details.
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%%%
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%%% You should have received a copy of the GNU General Public License
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%%% along with pdp10-tools. If not, see <http://www.gnu.org/licenses/>.
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%%%
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%%%=============================================================================
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%%%
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%%% 2.8 Half-Word Data Transmission
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-module(sim_halfword).
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-export([ handle_HLL/4
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, handle_HLLI/4
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, handle_HLLM/4
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, handle_HLLS/4
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]).
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-include("sim_core.hrl").
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%% 2.8 Half-Word Data Transmission =============================================
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%% HLL - Half Word Left to Left
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-spec handle_HLL(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HLL(Core, Mem, IR, EA) ->
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case sim_core:c(Core, Mem, EA) of
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{ok, CE} ->
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AC = IR band 8#17,
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CA = sim_core:get_ac(Core, AC),
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Word = set_left(CA, get_left(CE)),
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sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem);
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{error, Reason} ->
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sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
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end.
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-spec handle_HLLI(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HLLI(Core, Mem, IR, #ea{section = Section0, offset = Offset, islocal = IsLocal}) ->
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AC = IR band 8#17,
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CA = sim_core:get_ac(Core, AC),
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%% Behave as XHLLI (2.8.1) in non-zero sections.
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Section1 =
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if IsLocal, Offset =< 8#17, Section0 > 1 -> 1; % change local AC address to global one
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true -> Section0
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end,
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Word = set_left(CA, Section1),
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sim_core:next_pc(sim_core:set_ac(Core, AC, Word), Mem).
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-spec handle_HLLM(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HLLM(Core, Mem, IR, EA) ->
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case sim_core:c(Core, Mem, EA) of
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{ok, CE} ->
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AC = IR band 8#17,
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CA = sim_core:get_ac(Core, AC),
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Word = set_left(CE, get_left(CA)),
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handle_writeback(Core, Mem, EA, Word);
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{error, Reason} ->
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sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
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end.
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-spec handle_HLLS(#core{}, sim_mem:mem(), IR :: word(), #ea{})
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-> {#core{}, sim_mem:mem(), {ok, integer()} | {error, {module(), term()}}}.
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handle_HLLS(Core, Mem, IR, EA) ->
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%% "If A is zero, HLLS is a no-op; otherwise, it is equivalent to MOVE."
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%% This implies that redundant memory accesses should not be performed.
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AC = IR band 8#17,
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case AC of
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0 -> sim_core:next_pc(Core, Mem);
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_ ->
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case sim_core:c(Core, Mem, EA) of
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{ok, CE} ->
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sim_core:next_pc(sim_core:set_ac(Core, AC, CE), Mem);
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{error, Reason} ->
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sim_core:page_fault(Core, Mem, ea_address(EA), read, Reason,
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, IR, EA) end)
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end
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end.
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%% Miscellaneous ===============================================================
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handle_writeback(Core, Mem, EA, Word) ->
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case sim_core:cset(Core, Mem, EA, Word) of
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{ok, Core1} -> sim_core:next_pc(Core1, Mem);
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{error, Reason} ->
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sim_core:page_fault(Core, Mem, ea_address(EA), write, Reason,
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fun(Core1, Mem1) -> ?FUNCTION_NAME(Core1, Mem1, EA, Word) end)
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end.
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ea_address(#ea{section = Section, offset = Offset}) ->
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(Section bsl 18) bor Offset.
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get_left(Word) -> Word bsr 18.
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get_right(Word) -> Word band ((1 bsl 18) - 1).
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set_left(Word, Left) -> get_right(Word) bor (Left bsl 18).
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