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Code Issues Releases Wiki Activity

C64: move ROMs to SDRAM

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This commit is contained in:
Gyorgy Szombathelyi
2020-03-16 21:18:19 +01:00
parent 55e2c21f27
commit 09f7eb9d2d
3 changed files with 73 additions and 97 deletions
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49
cores/c64/rtl/fpga64_buslogic_roms_mmu.vhd
View File

@@ -26,7 +26,6 @@ entity fpga64_buslogic is
port (
clk : in std_logic;
reset : in std_logic;
c64gs : in std_logic;
cpuHasBus : in std_logic;
@@ -44,10 +43,6 @@ entity fpga64_buslogic is
ioF_rom : in std_logic;
max_ram : in std_logic;
c64rom_addr: in std_logic_vector(13 downto 0);
c64rom_data: in std_logic_vector(7 downto 0);
c64rom_wr: in std_logic;
cpuWe: in std_logic;
cpuAddr: in unsigned(15 downto 0);
cpuData: in unsigned(7 downto 0);
@@ -70,6 +65,7 @@ entity fpga64_buslogic is
cs_cia1: out std_logic;
cs_cia2: out std_logic;
cs_ram: out std_logic;
cs_rom: out std_logic;
-- To catridge port
cs_ioE: out std_logic;
@@ -98,9 +94,6 @@ architecture rtl of fpga64_buslogic is
signal charData: unsigned(7 downto 0);
signal basicData: unsigned(7 downto 0);
signal romData: std_logic_vector(7 downto 0);
signal romData_c64: std_logic_vector(7 downto 0);
signal romData_c64gs: std_logic_vector(7 downto 0);
signal c64gs_ena : std_logic := '0';
signal cs_CharReg : std_logic;
signal cs_romReg : std_logic;
@@ -129,44 +122,7 @@ begin
do => charData
);
kernelrom: entity work.rom_C64
port map
(
clock => clk,
wren => c64rom_wr,
data => c64rom_data,
wraddress => c64rom_addr,
rdaddress => std_logic_vector(cpuAddr(14) & cpuAddr(12 downto 0)),
q => romData_c64
);
-- not enough BRAM on MIST FPGA
-- kernelromGS: entity work.rom_GS64
-- port map
-- (
-- clock => clk,
-- wren => '0',
-- data => (others => '0'),
-- wraddress => (others => '0'),
-- rdaddress => std_logic_vector(cpuAddr(14) & cpuAddr(12 downto 0)),
-- q => romData_c64gs
-- );
romData <= romData_c64gs when c64gs_ena = '1' else romData_c64;
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
c64gs_ena <= c64gs;
end if;
end if;
end process;
romData <= std_logic_vector(ramData);
--
--begin
@@ -325,6 +281,7 @@ begin
end process;
cs_ram <= cs_ramReg or cs_romLReg or cs_romHReg or cs_UMAXromHReg; -- need to keep ram active for cartridges LCA
cs_rom <= cs_romReg;
cs_vic <= cs_vicReg;
cs_sid <= cs_sidReg;
cs_color <= cs_colorReg;

30
cores/c64/rtl/fpga64_sid_iec.vhd
View File

@@ -39,7 +39,6 @@ entity fpga64_sid_iec is
port(
clk32 : in std_logic;
reset_n : in std_logic;
c64gs : in std_logic;
-- keyboard interface (use any ordinairy PS2 keyboard)
kbd_clk : in std_logic;
kbd_dat : in std_logic;
@@ -50,9 +49,11 @@ entity fpga64_sid_iec is
ramAddr : out unsigned(15 downto 0);
ramDataIn : in unsigned(7 downto 0);
ramDataOut : out unsigned(7 downto 0);
romAddr : out unsigned(15 downto 0);
ramCE : out std_logic;
ramWe : out std_logic;
romCE : out std_logic;
idle : out std_logic;
@@ -136,11 +137,7 @@ entity fpga64_sid_iec is
cass_sense : in std_logic;
cass_read : in std_logic;
disk_num : out std_logic_vector(7 downto 0);
c64rom_addr : in std_logic_vector(13 downto 0);
c64rom_data : in std_logic_vector(7 downto 0);
c64rom_wr : in std_logic
disk_num : out std_logic_vector(7 downto 0)
);
end fpga64_sid_iec;
@@ -198,8 +195,9 @@ architecture rtl of fpga64_sid_iec is
signal cs_cia1: std_logic;
signal cs_cia2: std_logic;
signal cs_ram: std_logic;
signal cs_ioE: std_logic;
signal cs_ioF: std_logic;
signal cs_rom: std_logic;
signal cs_ioE: std_logic;
signal cs_ioF: std_logic;
signal cs_romL: std_logic;
signal cs_romH: std_logic;
signal cs_UMAXromH: std_logic; -- romH VIC II read flag
@@ -456,7 +454,6 @@ begin
port map (
clk => clk32,
reset => reset,
c64gs => c64gs,
cpuHasBus => cpuHasBus,
bankSwitch => cpuIO(2 downto 0),
@@ -494,15 +491,12 @@ begin
cs_cia1 => cs_cia1,
cs_cia2 => cs_cia2,
cs_ram => cs_ram,
cs_rom => cs_rom,
cs_ioE => cs_ioE,
cs_ioF => cs_ioF,
cs_romL => cs_romL,
cs_romH => cs_romH,
cs_UMAXromH => cs_UMAXromH,
c64rom_addr => c64rom_addr,
c64rom_data => c64rom_data,
c64rom_wr => c64rom_wr
cs_UMAXromH => cs_UMAXromH
);
process(clk32)
@@ -855,6 +849,14 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID)
sysCycle /= CYCLE_IEC3 and sysCycle /= CYCLE_CPU0 and sysCycle /= CYCLE_CPU1 and sysCycle /= CYCLE_CPUF and
cs_ram = '1' else '1';
romAddr <= "00" & cpuAddr(14) & cpuAddr(12 downto 0);
romCE <= '0' when sysCycle /= CYCLE_IDLE0 and sysCycle /= CYCLE_IDLE1 and sysCycle /= CYCLE_IDLE2 and
sysCycle /= CYCLE_IDLE3 and sysCycle /= CYCLE_IDLE4 and sysCycle /= CYCLE_IDLE5 and
sysCycle /= CYCLE_IDLE6 and sysCycle /= CYCLE_IDLE7 and sysCycle /= CYCLE_IDLE8 and
sysCycle /= CYCLE_IEC0 and sysCycle /= CYCLE_IEC1 and sysCycle /= CYCLE_IEC2 and
sysCycle /= CYCLE_IEC3 and sysCycle /= CYCLE_CPU0 and sysCycle /= CYCLE_CPU1 and sysCycle /= CYCLE_CPUF and
cs_rom = '1' else '1';
process(clk32)
begin
if rising_edge(clk32) then

91
cores/c64/rtl/mist/c64_mist.vhd
View File

@@ -356,8 +356,6 @@ end component cartridge;
signal CPU_hasbus : std_logic;
signal c1541rom_wr : std_logic;
signal c64rom_wr : std_logic;
signal c64rom_addr : std_logic_vector(13 downto 0);
signal joyA : std_logic_vector(31 downto 0);
signal joyB : std_logic_vector(31 downto 0);
@@ -459,6 +457,9 @@ end component cartridge;
signal c64_data_in16: std_logic_vector(15 downto 0);
alias c64_data_out_int : unsigned is unsigned(c64_data_out);
signal rom_ce : std_logic;
signal c64_rom_addr : unsigned(15 downto 0);
signal clk_c64 : std_logic; -- 31.527mhz (PAL), 32.727mhz(NTSC) clock source
signal clk_ram : std_logic; -- 2 x clk_c64
signal clk32 : std_logic; -- 32mhz
@@ -513,9 +514,8 @@ end component cartridge;
signal c64_addr_temp : std_logic_vector(24 downto 0);
signal cart_blk_len : std_logic_vector(31 downto 0);
signal cart_hdr_cnt : std_logic_vector(3 downto 0);
signal erase_cram : std_logic := '0';
signal erase_cartram : std_logic := '0';
signal force_erase : std_logic;
signal erase_to : std_logic_vector(4 downto 0) := (others => '0');
signal mem_ce : std_logic;
signal uart_rxD : std_logic;
@@ -523,7 +523,8 @@ end component cartridge;
-- sdram layout
constant C64_MEM_START : std_logic_vector(24 downto 0) := '0' & X"000000"; -- normal C64 RAM
constant CRT_MEM_START : std_logic_vector(24 downto 0) := '0' & X"100000"; -- cartdriges
constant C64_ROM_START : std_logic_vector(24 downto 0) := '0' & X"0F0000"; -- kernal/basic ROM
constant CRT_MEM_START : std_logic_vector(24 downto 0) := '0' & X"100000"; -- cartridges
constant TAP_MEM_START : std_logic_vector(24 downto 0) := '0' & X"200000"; -- .tap files
begin
@@ -651,7 +652,7 @@ begin
nmi => nmi,
nmi_ack => nmi_ack
);
-- rearrange joystick contacta for c64
joyA_int <= joyA(6 downto 5) & (joyA(4) or (mouse_en and mouse_btns(0))) & joyA(0) & joyA(1) & joyA(2) & (joyA(3) or (mouse_en and mouse_btns(1)));
joyB_int <= joyB(6 downto 5) & (joyB(4) or (mouse_en and mouse_btns(0))) & joyB(0) & joyB(1) & joyB(2) & (joyB(3) or (mouse_en and mouse_btns(1)));
@@ -662,11 +663,14 @@ begin
joyA_c64 <= joyB_int when st_swap_joystick='1' else joyA_int;
joyB_c64 <= joyA_int when st_swap_joystick='1' else joyB_int;
sdram_addr <= c64_addr_temp when iec_cycle='0' else ioctl_ram_addr when ioctl_download = '1' or erasing = '1' else tap_play_addr;
sdram_addr <= std_logic_vector(unsigned(C64_ROM_START) + c64_rom_addr) when iec_cycle = '0' and rom_ce = '0' else
c64_addr_temp when iec_cycle='0' else
ioctl_ram_addr when ioctl_download = '1' or erasing = '1' else
tap_play_addr;
sdram_data_out <= c64_data_out when iec_cycle='0' else ioctl_ram_data;
-- ram_we and ce are active low
sdram_ce <= mem_ce when iec_cycle='0' else ioctl_iec_cycle_used or tap_mem_ce;
-- ram_we and rom_ce are active low
sdram_ce <= (mem_ce or not rom_ce) when iec_cycle='0' else ioctl_iec_cycle_used or tap_mem_ce;
sdram_we <= not ram_we when iec_cycle='0' else ioctl_iec_cycle_used when ioctl_download = '1' or erasing = '1' else '0';
process(clk_c64)
@@ -697,11 +701,23 @@ begin
end if;
if ioctl_wr='1' then
if ioctl_index = FILE_BOOT or ioctl_index = FILE_ROM then
if ioctl_addr = 0 then
ioctl_load_addr <= C64_ROM_START;
if ioctl_index = FILE_ROM then
ioctl_load_addr <= C64_ROM_START + x"2000";
end if;
end if;
if ioctl_addr(24 downto 14) = 0 then
ioctl_ram_wr <= '1';
end if;
end if;
if ioctl_index = FILE_PRG then
if ioctl_addr = 0 then
ioctl_load_addr(7 downto 0) <= ioctl_data;
elsif(ioctl_addr = 1) then
ioctl_load_addr(15 downto 8) <= ioctl_data;
ioctl_load_addr(24 downto 8) <= '0'&x"00"&ioctl_data;
else
ioctl_ram_wr <= '1';
end if;
@@ -758,37 +774,43 @@ begin
end if;
end if;
-- cart added
if old_download /= ioctl_download and ioctl_index = FILE_CRT then
cart_attached <= old_download;
erase_cram <= '1';
end if;
-- cart removed
if st_detach_cartdrige='1' or buttons(1)='1' then
cart_attached <= '0';
erase_cartram <= '1';
end if;
-- start RAM erasing
if erasing='0' and force_erase = '1' then
erasing <='1';
ioctl_load_addr <= (others => '0');
end if;
if erasing = '1' and ioctl_ram_wr = '0' then
erase_to <= erase_to + "1";
if erase_to = "11111" then
if ioctl_load_addr < (erase_cram & X"FFFF") then
ioctl_ram_wr <= '1';
-- RAM erasing control
if erasing = '1' and iec_cycle = '1' and iec_cycleD = '1' then
-- erase up to 0xFFFF
if ioctl_load_addr(16 downto 0) = '1'&x"0000" then
if ioctl_load_addr < CRT_MEM_START and erase_cartram = '1' then
ioctl_load_addr <= CRT_MEM_START;
ioctl_ram_wr <= '1';
else
erasing <= '0';
erase_cartram <= '0';
end if;
else
erasing <= '0';
erase_cram <= '0';
ioctl_ram_wr <= '1';
end if;
end if;
end if;
end if;
end process;
c64rom_wr <= ioctl_wr when (((ioctl_index = FILE_BOOT) and (ioctl_addr(14) = '0')) or (ioctl_index = FILE_ROM)) and (ioctl_download = '1') else '0';
c64rom_addr <= ioctl_addr(13 downto 0) when ioctl_index = FILE_BOOT else '1' & ioctl_addr(12 downto 0);
c1541rom_wr <= ioctl_wr when (ioctl_index = FILE_BOOT) and (ioctl_addr(14) = '1') and (ioctl_download = '1') else '0';
process(clk_c64)
@@ -933,20 +955,17 @@ begin
reset_counter <= 1000000;
reset_n <= '0';
elsif buttons(1)='1' or st_detach_cartdrige='1' or reset_key = '1' or reset_crt='1' or
(ioctl_download='1' and (ioctl_index = FILE_ROM or ioctl_index = FILE_CRT)) then
(ioctl_download='1' and (ioctl_index = FILE_BOOT or ioctl_index = FILE_ROM or ioctl_index = FILE_CRT)) then
reset_counter <= 255;
reset_n <= '0';
elsif ioctl_download ='1' then
elsif erasing ='1' then
force_erase <= '0';
else
if reset_counter = 0 then
reset_n <= '1';
else
reset_counter <= reset_counter - 1;
if reset_counter = 100 then
elsif reset_counter = 0 then
reset_n <= '1';
elsif ioctl_download = '0' then
reset_counter <= reset_counter - 1;
if reset_counter = 100 then
force_erase <='1';
end if;
end if;
end if;
end if;
@@ -994,7 +1013,6 @@ begin
port map(
clk32 => clk_c64,
reset_n => reset_n,
c64gs => st_c64gs,-- not enough BRAM
kbd_clk => not ps2_clk,
kbd_dat => ps2_dat,
ramAddr => c64_addr_int,
@@ -1002,6 +1020,8 @@ begin
ramDataIn => c64_data_in_int,
ramCE => ram_ce,
ramWe => ram_we,
romAddr => c64_rom_addr,
romCE => rom_ce,
ntscInitMode => ntsc_init_mode,
hsync => hsync,
vsync => vsync,
@@ -1059,10 +1079,7 @@ begin
cass_write => cass_write,
cass_read => cass_read,
cass_sense => cass_sense,
c64rom_addr => c64rom_addr,
c64rom_data => ioctl_data,
c64rom_wr => c64rom_wr,
tap_playstop_key => tap_playstop_key,
reset_key => reset_key
);