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Code Issues Releases Wiki Activity

[C16] Move ROMs to SDRAM to free up some BRAM

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This commit is contained in:
Gyorgy Szombathelyi
2019-05-04 21:47:37 +02:00
parent 1ce2a26d96
commit 0a857fd788
2 changed files with 52 additions and 19 deletions
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34
cores/c16/c16.v
View File

@@ -30,7 +30,7 @@
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module C16 #(parameter MODE_PAL = 1)(
module C16 (
input wire CLK28,
input wire RESET,
input wire WAIT,
@@ -48,7 +48,11 @@ module C16 #(parameter MODE_PAL = 1)(
output wire [7:0] A,
input wire [7:0] DIN,
output wire [7:0] DOUT,
output wire CS0, // Select BASIC ROM (low active)
output wire CS1, // Select Kernal ROM (low active)
output wire [13:0] ROM_ADDR,
input [4:0] JOY0,
input [4:0] JOY1,
@@ -85,6 +89,9 @@ module C16 #(parameter MODE_PAL = 1)(
output RGBS
);
parameter MODE_PAL = 1;
parameter INTERNAL_ROM = 1;
wire [15:0] c16_addr;
wire [15:0] ted_addr;
wire [15:0] cpu_addr;
@@ -111,6 +118,7 @@ assign kbus[3:0] = kbus_kbd[3:0] & joy0_sel[3:0] & joy1_sel[3:0];
assign kbus[5:4] = kbus_kbd[5:4]; // no joystick line connected here
assign kbus[6] = kbus_kbd[6] & joy0_sel[4];
assign kbus[7] = kbus_kbd[7] & joy1_sel[4];
assign ROM_ADDR = c16_addr[13:0];
// 8501 CPU
mos8501 cpu (
@@ -130,7 +138,7 @@ assign kbus[7] = kbus_kbd[7] & joy1_sel[4];
);
// TED 8360 instance
wire irq_n, cpuclk, cs0, cs1;
wire irq_n, cpuclk;
ted mos8360(
.clk(CLK28),
@@ -149,8 +157,8 @@ ted mos8360(
.mux(mux),
.ras(RAS),
.cas(CAS),
.cs0(cs0),
.cs1(cs1),
.cs0(CS0),
.cs1(CS1),
.aec(aec),
.k(kbus),
.snd(sound),
@@ -163,23 +171,26 @@ ted mos8360(
kernal_rom #(.MODE_PAL(MODE_PAL)) kernal(
.clk(CLK28),
.address_in(kernal_dl_write?dl_addr:c16_addr[13:0]),
.data_out(kernal_data),
.data_out(kernal_data_int),
.data_in(dl_data),
.wr(kernal_dl_write),
.cs(cs1)
.cs(CS1)
);
wire [7:0] kernal_data_int;
assign kernal_data = INTERNAL_ROM ? kernal_data_int : (~CS1 & RW) ? DIN : 8'hFF;
// Basic rom
basic_rom basic(
.clk(CLK28),
.address_in(basic_dl_write?dl_addr:c16_addr[13:0]),
.data_out(basic_data),
.data_out(basic_data_int),
.data_in(dl_data),
.wr(basic_dl_write),
.cs(cs0)
.cs(CS0)
);
wire [7:0] basic_data_int;
assign basic_data = INTERNAL_ROM ? basic_data_int : (~CS0 & RW) ? DIN : 8'hFF;
// Color decoder to 12bit RGB
colors_to_rgb colordecode (
@@ -315,6 +326,7 @@ sid8580 sid8580
wire [7:0] sid6581_data;
wire [17:0] sid6581_audio;
sid_top #(.g_num_voices(3)) sid6581
(
.reset(sreset),
@@ -326,7 +338,7 @@ sid_top #(.g_num_voices(3)) sid6581
.wdata(c16_data),
.rdata(sid6581_data),
.extfilter_en(0), // disabled due to out of BRAM
.extfilter_en(1),
.sample_left(sid6581_audio)
);

37
cores/c16/c16_mist.v
View File

@@ -86,7 +86,8 @@ parameter CONF_STR = {
parameter CONF_STR_LEN = 11+17+18+18+21+20+28+18+22+9;
localparam TAP_MEM_START = 22'h20000;
localparam ROM_MEM_START = 25'h10000;
localparam TAP_MEM_START = 25'h20000;
reg uart_rxD;
reg uart_rxD2;
@@ -127,10 +128,14 @@ wire ps2_mouse_clk, ps2_mouse_data;
assign SDRAM_CKE = 1'b1;
// ram access signals from c16
wire [15:0] c16_sdram_addr = { c16_a_hi, c16_a_low };
wire c16_rom_access = (~c16_basic_sel | ~c16_kernal_sel) && c16_rw;
wire [15:0] c16_sdram_addr = c16_rom_access ? { 1'b0, ~c16_basic_sel, c16_rom_addr } : { c16_a_hi, c16_a_low };
wire [7:0] c16_sdram_data = c16_dout;
wire c16_sdram_wr = !c16_cas && !c16_rw;
wire c16_sdram_oe = !c16_cas && c16_rw;
wire c16_sdram_oe = (!c16_cas && c16_rw) || c16_rom_access;
wire c16_basic_sel;
wire c16_kernal_sel;
wire [13:0] c16_rom_addr;
// ram access signals from io controller
// ioctl_sdram_write
@@ -146,9 +151,18 @@ wire mux_sdram_oe = clkref ? c16_sdram_oe : tap_sdram_oe;
wire [15:0] sdram_din = { mux_sdram_data, mux_sdram_data };
wire [14:0] sdram_addr_64k = mux_sdram_addr[15:1]; // 64k mapping
wire [14:0] sdram_addr_16k = { 1'b0, mux_sdram_addr[13:7], 1'b0, mux_sdram_addr[6:1] }; // 16k
wire [23:0] sdram_addr = (clkref | (~clkref & prg_download)) ?
{ 9'd0, memory_16k?sdram_addr_16k:sdram_addr_64k } :
(tap_sdram_oe ? tap_play_addr[24:1] : ioctl_sdram_addr[24:1]);
wire [14:0] sdram_addr_c16ram = memory_16k?sdram_addr_16k:sdram_addr_64k;
reg [23:0] sdram_addr;
always @(*) begin
casex ({ clkref, c16_rom_access, prg_download, tap_sdram_oe })
'b0X00: sdram_addr = ioctl_sdram_addr[24:1];
'b0X01: sdram_addr = tap_play_addr[24:1];
'b0X1X: sdram_addr = { 9'd0, sdram_addr_c16ram };
'b10XX: sdram_addr = { 9'd0, sdram_addr_c16ram };
'b11XX: sdram_addr = { 8'd0,1'b1, 1'b0, ~c16_basic_sel, c16_rom_addr[13:1] };
endcase
end
wire sdram_wr = mux_sdram_wr;
wire sdram_oe = mux_sdram_oe;
@@ -307,7 +321,7 @@ wire rom_download = ioctl_downloading && ((ioctl_index == 8'h00) || (ioctl_index
wire prg_download = ioctl_downloading && (ioctl_index == 8'h01);
wire tap_download = ioctl_downloading && (ioctl_index == 8'h41);
wire c16_wait = 0;
wire c16_wait = rom_download | prg_download;
data_io data_io (
// SPI interface
@@ -411,6 +425,9 @@ always @(posedge clk28) begin
end else if (tap_download) begin
if(ioctl_addr == 16'h0000) ioctl_sdram_addr <= TAP_MEM_START;
ioctl_ram_wr <= 1'b1;
end else if (rom_download) begin
if((ioctl_index == 8'h0 && ioctl_addr == 16'h4000) || (ioctl_index == 8'h3 && ioctl_addr == 16'h0000)) ioctl_sdram_addr <= ROM_MEM_START;
if((ioctl_index == 8'h0 && ioctl_addr[15:14]) || ioctl_index == 8'h3) ioctl_ram_wr <= 1'b1;
end
end
@@ -627,7 +644,7 @@ sigma_delta_dac dac (
);
// include the c16 itself
C16 c16 (
C16 #(.INTERNAL_ROM(0)) c16 (
.CLK28 ( clk28 ),
.RESET ( reset ),
.WAIT ( c16_wait ),
@@ -645,6 +662,10 @@ C16 c16 (
.DOUT ( c16_dout ),
.DIN ( c16_din ),
.CS0 ( c16_basic_sel ),
.CS1 ( c16_kernal_sel ),
.ROM_ADDR( c16_rom_addr ),
.JOY0 ( jsB[4:0] ),
.JOY1 ( jsA[4:0] ),