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C64: use only the T65 CPU

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This commit is contained in:
Gyorgy Szombathelyi
2018-09-06 02:41:13 +02:00
parent a3c2f83e1b
commit 10f96bb44d
5 changed files with 50 additions and 1710 deletions
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49
cores/c64/rtl/cpu65xx_e.vhd
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@@ -1,49 +0,0 @@
-- -----------------------------------------------------------------------
--
-- FPGA 64
--
-- A fully functional commodore 64 implementation in a single FPGA
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
-- -----------------------------------------------------------------------
--
-- Interface to 6502/6510 core
--
-- -----------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity cpu65xx is
generic (
pipelineOpcode : boolean;
pipelineAluMux : boolean;
pipelineAluOut : boolean
);
port (
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
nmi_n : in std_logic;
nmi_ack : out std_logic;
irq_n : in std_logic;
so_n : in std_logic := '1';
di : in unsigned(7 downto 0);
do : out unsigned(7 downto 0);
addr : out unsigned(15 downto 0);
we : out std_logic;
debugOpcode : out unsigned(7 downto 0);
debugPc : out unsigned(15 downto 0);
debugA : out unsigned(7 downto 0);
debugX : out unsigned(7 downto 0);
debugY : out unsigned(7 downto 0);
debugS : out unsigned(7 downto 0)
);
end cpu65xx;

1565
cores/c64/rtl/cpu65xx_fast.vhd
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File diff suppressed because it is too large Load Diff

126
cores/c64/rtl/cpu_6510.vhd
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@@ -21,103 +21,65 @@ use ieee.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity cpu_6510 is
generic (
pipelineOpcode : boolean;
pipelineAluMux : boolean;
pipelineAluOut : boolean
);
port (
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
nmi_n : in std_logic;
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
nmi_n : in std_logic;
nmi_ack : out std_logic;
irq_n : in std_logic;
irq_n : in std_logic;
di : in unsigned(7 downto 0);
do : out unsigned(7 downto 0);
addr : out unsigned(15 downto 0);
we : out std_logic;
di : in unsigned(7 downto 0);
do : out unsigned(7 downto 0);
addr : out unsigned(15 downto 0);
we : out std_logic;
diIO : in unsigned(7 downto 0);
doIO : out unsigned(7 downto 0);
debugOpcode : out unsigned(7 downto 0);
debugPc : out unsigned(15 downto 0);
debugA : out unsigned(7 downto 0);
debugX : out unsigned(7 downto 0);
debugY : out unsigned(7 downto 0);
debugS : out unsigned(7 downto 0)
diIO : in unsigned(7 downto 0);
doIO : out unsigned(7 downto 0)
);
end cpu_6510;
-- -----------------------------------------------------------------------
architecture rtl of cpu_6510 is
signal localA : unsigned(15 downto 0);
signal localDi : unsigned(7 downto 0);
signal localDo : unsigned(7 downto 0);
signal localA : std_logic_vector(23 downto 0);
signal localDi : std_logic_vector(7 downto 0);
signal localDo : std_logic_vector(7 downto 0);
signal localWe : std_logic;
signal currentIO : unsigned(7 downto 0);
signal ioDir : unsigned(7 downto 0);
signal ioData : unsigned(7 downto 0);
signal currentIO : std_logic_vector(7 downto 0);
signal ioDir : std_logic_vector(7 downto 0);
signal ioData : std_logic_vector(7 downto 0);
signal accessIO : std_logic;
begin
cpuInstance: entity work.cpu65xx(fast)
generic map (
pipelineOpcode => pipelineOpcode,
pipelineAluMux => pipelineAluMux,
pipelineAluOut => pipelineAluOut
)
port map (
clk => clk,
enable => enable,
reset => reset,
nmi_n => nmi_n,
nmi_ack => nmi_ack,
irq_n => irq_n,
di => localDi,
do => localDo,
addr => localA,
we => localWe,
cpu: work.T65
port map(
Mode => "00",
Res_n => not reset,
Enable => enable,
Clk => clk,
Rdy => '1',
Abort_n => '1',
IRQ_n => irq_n,
NMI_n => nmi_n,
SO_n => '1',
R_W_n => localWe,
A => localA,
DI => localDi,
DO => localDo,
NMI_ack => nmi_ack
);
accessIO <= '1' when localA(15 downto 1) = X"000"&"000" else '0';
localDi <= localDo when localWe = '0' else std_logic_vector(di) when accessIO = '0' else ioDir when localA(0) = '0' else currentIO;
debugOpcode => debugOpcode,
debugPc => debugPc,
debugA => debugA,
debugX => debugX,
debugY => debugY,
debugS => debugS
);
process(localA)
begin
accessIO <= '0';
if localA(15 downto 1) = 0 then
accessIO <= '1';
end if;
end process;
process(di, localA, ioDir, currentIO, accessIO)
begin
localDi <= di;
if accessIO = '1' then
if localA(0) = '0' then
localDi <= ioDir;
else
localDi <= currentIO;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if accessIO = '1' then
if localWe = '1'
and enable = '1' then
if localWe = '0' and enable = '1' then
if localA(0) = '0' then
ioDir <= localDo;
else
@@ -130,12 +92,12 @@ begin
end if;
end if;
end process;
process(ioDir, ioData, diIO)
begin
for i in 0 to 7 loop
if ioDir(i) = '0' then
currentIO(i) <= diIO(i);
currentIO(i) <= std_logic(diIO(i));
else
currentIO(i) <= ioData(i);
end if;
@@ -143,8 +105,8 @@ begin
end process;
-- Cunnect zee wires
addr <= localA;
do <= localDo;
we <= localWe;
doIO <= currentIO;
addr <= unsigned(localA(15 downto 0));
do <= unsigned(localDo);
we <= not localWe;
doIO <= unsigned(currentIO);
end architecture;

15
cores/c64/rtl/fpga64_sid_iec.vhd
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@@ -633,11 +633,7 @@ sid_8580 : sid8580
-- 6510 CPU
-- -----------------------------------------------------------------------
cpu: entity work.cpu_6510
generic map (
pipelineOpcode => false,
pipelineAluMux => false,
pipelineAluOut => false
)
port map (
clk => clk32,
reset => reset,
@@ -652,14 +648,7 @@ sid_8580 : sid8580
we => cpuWe,
diIO => "00010111",
doIO => cpuIO,
debugOpcode => open,
debugPc => open,
debugA => open,
debugX => open,
debugY => open,
debugS => open
doIO => cpuIO
);
-- -----------------------------------------------------------------------

5
cores/c64/rtl/t65/T65.vhd
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@@ -152,7 +152,8 @@ entity T65 is
DO : out std_logic_vector(7 downto 0);
-- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB)
Regs : out std_logic_vector(63 downto 0);
DEBUG : out T_t65_dbg
DEBUG : out T_t65_dbg;
NMI_ack : out std_logic
);
end T65;
@@ -236,6 +237,8 @@ architecture rtl of T65 is
signal NMI_entered : std_logic;
begin
NMI_ack <= NMIAct;
-- gate Rdy with read/write to make an "OK, it's really OK to stop the processor
really_rdy <= Rdy or not(WRn_i);
Sync <= '1' when MCycle = "000" else '0';