[Archie] Add CMOS RAM upload

cores/archie/fpga/mist/archimedes_mist_top.v

@@ -83,8 +83,10 @@ wire			core_hs, core_vs;
 wire [15:0]	coreaud_l, coreaud_r;
 
 // data loading 
-wire 			loader_active /* synthesis keep */ ;
-wire 			loader_we /* synthesis keep */ ;
+wire        downloading;
+wire        loader_active = downloading && (dio_index == 1 || dio_index == 2);
+wire [7:0]  dio_index;
+wire 		loader_we /* synthesis keep */ ;
 reg			loader_stb = 1'b0 /* synthesis keep */ ;
 reg         rom_ready = 0;
 (*KEEP="TRUE"*)wire [3:0]	loader_sel /* synthesis keep */ ;
@@ -289,7 +291,6 @@ wire  [8:0] sd_buff_addr;
 wire  [1:0] img_mounted;
 wire [31:0] img_size;
 
-// de-multiplex spi outputs from user_io and data_io
 assign SPI_DO = (CONF_DATA0==0)?user_io_sdo:1'bZ;
 
 wire user_io_sdo;
@@ -336,8 +337,9 @@ DATA_IO  (
 	.ss				( SPI_SS2			),
 	.sdi				( SPI_DI				),
 
-	.downloading	( loader_active	),
+	.downloading	( downloading	),
 	.size				(						),
+	.index          ( dio_index ),
 
 	// ram interface
    .clk     		( clk_32m			),
@@ -463,7 +465,10 @@ i2cSlaveTop CMOS (
 	.rst		( ~pll_ready	),
 	.sdaIn	    ( i2c_din		),
 	.sdaOut	    ( i2c_dout		),
-	.scl		( i2c_clock		)
+	.scl		( i2c_clock		),
+	.we			( downloading && dio_index == 3 && loader_we ),
+	.addr		( loader_addr[7:0] ),
+	.data		( loader_data[7:0] )
 );
 
 audio	AUDIO	(

cores/archie/fpga/mist/data_io.v

@@ -31,6 +31,7 @@ module data_io #(parameter ADDR_WIDTH=24, START_ADDR = 0) (
 
 	output reg downloading, // signal indicating an active download
 	output [ADDR_WIDTH-1:0]     size, // number of bytes in input buffer
+	output reg [7:0] index, // menu index
 
 	// external ram interface
 	input 			    clk,
@@ -54,7 +55,6 @@ assign size = addr - START_ADDR;
 // this core supports only the display related OSD commands
 // of the minimig
 reg [6:0]      sbuf;
-reg [7:0]      cmd;
 reg [7:0]      data;
 reg [2:0]      bit_cnt;
 reg [2:0]      byte_cnt;
@@ -63,7 +63,7 @@ reg [ADDR_WIDTH-1:0] addr;
 
 localparam UIO_FILE_TX         = 8'h53;
 localparam UIO_FILE_TX_DAT     = 8'h54;
-
+localparam UIO_FILE_INDEX      = 8'h55;
 // data_io has its own SPI interface to the io controller
 
 // SPI bit and byte counters
@@ -71,11 +71,9 @@ always@(posedge sck or posedge ss) begin
 	if(ss == 1) begin
 		bit_cnt <= 0;
 		byte_cnt <= 0;
-		cmd <= 0;
 	end else begin
 		if((&bit_cnt)&&(~&byte_cnt)) begin
 			byte_cnt <= byte_cnt + 1'd1;
-			if (!byte_cnt) cmd <= {sbuf, sdi};
 		end
 		bit_cnt <= bit_cnt + 1'd1;
 	end
@@ -124,7 +122,7 @@ always @(posedge clk) begin
 
 	// strobe is set whenever a valid byte has been received
 	if (~spi_transfer_endD & spi_transfer_end) begin
-		abyte_cnt <= 8'd0;
+		abyte_cnt <= 0;
 	end else if (spi_receiver_strobeD ^ spi_receiver_strobe) begin
 
 		if(~&abyte_cnt)
@@ -154,6 +152,9 @@ always @(posedge clk) begin
 				data <= spi_byte_in;
 				wr <= 1;
 			end
+
+			// index
+			UIO_FILE_INDEX: index <= spi_byte_in;
 			endcase;
 		end
 	end

cores/archie/rtl/i2cslave/i2cSlave.v

@@ -44,21 +44,19 @@
 //
 `include "i2cSlave_define.v"
 
-
 module i2cSlave (
-  clk,
-  rst,
-  sdaIn,
-  sdaOut,
-  scl
+  input clk,
+  input rst,
+  input sdaIn,
+  output sdaOut,
+  input scl,
+  
+  // parallel write
+  input we,
+  input [7:0] addr,
+  input [7:0] data
 );
 
-input clk;
-input rst;
-input sdaIn;
-output sdaOut;
-input scl;
-
 // local wires and regs
 reg sdaDeb;
 reg sclDeb;
@@ -154,9 +152,9 @@ end
 
 registerInterface u_registerInterface(
   .clk(clk),
-  .addr(regAddr),
-  .dataIn(dataToRegIF),
-  .writeEn(writeEn),
+  .addr(we ? addr : regAddr),
+  .dataIn(we ? data : dataToRegIF),
+  .writeEn(writeEn | we),
   .dataOut(dataFromRegIF)
 );
 

cores/archie/rtl/i2cslave/i2cSlaveTop.v

@@ -46,29 +46,27 @@
 
 
 module i2cSlaveTop (
-  clk,
-  rst,
-  sdaIn,
-  sdaOut,
-  scl
+  input clk,
+  input rst,
+  input sdaIn,
+  output sdaOut,
+  input scl,
+  
+  // parallel write
+  input we,
+  input [7:0] addr,
+  input [7:0] data
 );
-input clk;
-input rst;
-input sdaIn;
-output sdaOut;
-input scl;
-
 
 i2cSlave u_i2cSlave(
   .clk(clk),
   .rst(rst),
   .sdaIn(sdaIn),
   .sdaOut(sdaOut),
-  .scl(scl)
+  .scl(scl),
+  .we(we),
+  .addr(addr),
+  .data(data)
 );
 
-
 endmodule
-
-
-