mirror of
https://github.com/mist-devel/mist-board.git
synced 2026-05-04 23:36:12 +00:00
[ATARI ST] Minor audio and video adjustments
This commit is contained in:
harbaum
@@ -61,7 +61,7 @@ library ieee;
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use ieee.std_logic_unsigned.all;
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entity YM2149 is
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port (
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port (
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-- data bus
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I_DA : in std_logic_vector(7 downto 0);
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O_DA : out std_logic_vector(7 downto 0);
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@@ -75,8 +75,8 @@ entity YM2149 is
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I_SEL_L : in std_logic;
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stereo : in std_logic;
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O_AUDIO_L : out std_logic_vector(7 downto 0);
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O_AUDIO_R : out std_logic_vector(7 downto 0);
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O_AUDIO_L : out std_logic_vector(9 downto 0);
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O_AUDIO_R : out std_logic_vector(9 downto 0);
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-- port a
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I_IOA : in std_logic_vector(7 downto 0);
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O_IOA : out std_logic_vector(7 downto 0);
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@@ -184,54 +184,6 @@ begin
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O_DA_OE_L <= not (busctrl_re);
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end process;
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-- CLOCKED
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--p_waddr : process
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--begin
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---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
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--wait until rising_edge(CLK);
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--if (RESET_L = '0') then
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--addr <= (others => '0');
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--else
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--if (busctrl_addr = '1') then
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--addr <= I_DA;
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--end if;
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--end if;
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--end process;
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--p_wdata : process
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--begin
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---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
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--wait until rising_edge(CLK);
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--env_reset <= '0';
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--if (RESET_L = '0') then
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--reg <= (others => (others => '0'));
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--env_reset <= '1';
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--else
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--env_reset <= '0';
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--if (busctrl_we = '1') then
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--case addr(3 downto 0) is
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--when x"0" => reg(0) <= I_DA;
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--when x"1" => reg(1) <= I_DA;
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--when x"2" => reg(2) <= I_DA;
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--when x"3" => reg(3) <= I_DA;
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--when x"4" => reg(4) <= I_DA;
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--when x"5" => reg(5) <= I_DA;
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--when x"6" => reg(6) <= I_DA;
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--when x"7" => reg(7) <= I_DA;
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--when x"8" => reg(8) <= I_DA;
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--when x"9" => reg(9) <= I_DA;
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--when x"A" => reg(10) <= I_DA;
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--when x"B" => reg(11) <= I_DA;
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--when x"C" => reg(12) <= I_DA;
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--when x"D" => reg(13) <= I_DA; env_reset <= '1';
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--when x"E" => reg(14) <= I_DA;
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--when x"F" => reg(15) <= I_DA;
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--when others => null;
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--end case;
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--end if;
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--end if;
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--end process;
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-- LATCHED, useful when emulating a real chip in circuit. Nasty as gated clock.
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p_waddr : process(reset_l, busctrl_addr)
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@@ -605,11 +557,11 @@ begin
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wait until rising_edge(CLK);
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if (RESET_L = '0') then
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O_AUDIO_L(7 downto 0) <= "00000000";
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O_AUDIO_R(7 downto 0) <= "00000000";
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O_AUDIO_L <= "0000000000";
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O_AUDIO_R <= "0000000000";
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else
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O_AUDIO_L(7 downto 0) <= vol_table_out_l(9 downto 2);
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O_AUDIO_R(7 downto 0) <= vol_table_out_r(9 downto 2);
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O_AUDIO_L <= vol_table_out_l;
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O_AUDIO_R <= vol_table_out_r;
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end if;
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end process;
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@@ -75,7 +75,7 @@ wire [7:0] port_b_out;
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assign floppy_side = port_a_out[0];
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assign floppy_sel = port_a_out[2:1];
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wire [7:0] ym_audio_out_l, ym_audio_out_r;
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wire [9:0] ym_audio_out_l, ym_audio_out_r;
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// extra joysticks are wired to the printer port
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// using the "gauntlet2 interface", fire of
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@@ -175,27 +175,24 @@ ste_dma_snd ste_dma_snd (
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// audio output processing
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// simple mixer for ste and ym audio. result is 9 bits
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// this will later be handled by the lmc1992
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wire [8:0] audio_mix_l = { 1'b0, ym_audio_out_l} + { 1'b0, ste_audio_out_l };
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wire [8:0] audio_mix_r = { 1'b0, ym_audio_out_r} + { 1'b0, ste_audio_out_r };
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// YM and STE audio channels are expanded to 14 bits and added resulting in 15 bits
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// for the sigmadelta dac take from the minimig
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// limit audio to 8 bit range
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wire [7:0] audio_out_l = audio_mix_l[8]?8'd255:audio_mix_l[7:0];
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wire [7:0] audio_out_r = audio_mix_r[8]?8'd255:audio_mix_r[7:0];
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// This should later be handled by the lmc1992
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sigma_delta_dac sigma_delta_dac_l (
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.DACout (audio_l),
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.DACin (audio_out_l),
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.CLK (clk_32),
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.RESET (reset)
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);
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wire [14:0] audio_mix_l =
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{ 1'b0, ym_audio_out_l, ym_audio_out_l[9:6]} +
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{ 1'b0, ste_audio_out_l, ste_audio_out_l[7:2] };
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wire [14:0] audio_mix_r =
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{ 1'b0, ym_audio_out_r, ym_audio_out_r[9:6]} +
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{ 1'b0, ste_audio_out_r, ste_audio_out_r[7:2] };
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sigma_delta_dac sigma_delta_dac_r (
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.DACout (audio_r),
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.DACin (audio_out_r),
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.CLK (clk_32),
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.RESET (reset)
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sigma_delta_dac sigma_delta_dac (
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.clk ( clk_32 ), // bus clock
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.ldatasum ( audio_mix_l ), // left channel data
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.rdatasum ( audio_mix_r ), // right channel data
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.left ( audio_l ), // left bitstream output
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.right ( audio_r ) // right bitsteam output
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);
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endmodule
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@@ -1,30 +1,29 @@
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# Copyright (C) 1991-2007 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
|
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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# If this file doesn't exist, and for assignments not listed, see file
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# assignment_defaults.qdf
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# Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
|
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# and any changes you make may be lost or overwritten.
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# Copyright (C) 1991-2007 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
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||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
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||||
# applicable agreement for further details.
|
||||
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# If this file doesn't exist, and for assignments not listed, see file
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# assignment_defaults.qdf
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||||
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# Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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set_global_assignment -name FAMILY "Cyclone III"
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set_global_assignment -name DEVICE EP3C25E144C8
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set_global_assignment -name TOP_LEVEL_ENTITY mist_top
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set_global_assignment -name TOP_LEVEL_ENTITY mist_top
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:27:29 OCTOBER 30, 2007"
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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@@ -32,8 +31,8 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
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set_global_assignment -name FITTER_EFFORT "AUTO FIT"
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set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
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set_global_assignment -name FITTER_EFFORT "FAST FIT"
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set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
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@@ -41,7 +40,7 @@ set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
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set_global_assignment -name GENERATE_RBF_FILE ON
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set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_location_assignment PIN_7 -to LED
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set_location_assignment PIN_22 -to CLOCK_50[0]
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set_location_assignment PIN_23 -to CLOCK_50[1]
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@@ -80,7 +79,7 @@ set_location_assignment PIN_127 -to SPI_SS2
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set_location_assignment PIN_91 -to SPI_SS3
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set_location_assignment PIN_90 -to SPI_SS4
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set_location_assignment PIN_13 -to CONF_DATA0
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set_location_assignment PIN_49 -to SDRAM_A[0]
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set_location_assignment PIN_44 -to SDRAM_A[1]
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set_location_assignment PIN_42 -to SDRAM_A[2]
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@@ -120,16 +119,16 @@ set_location_assignment PIN_66 -to SDRAM_nWE
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set_location_assignment PIN_59 -to SDRAM_nCS
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set_location_assignment PIN_33 -to SDRAM_CKE
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set_location_assignment PIN_43 -to SDRAM_CLK
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set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
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set_global_assignment -name SMART_RECOMPILE ON
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
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set_global_assignment -name USE_SIGNALTAP_FILE tg68k.stp
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
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||||
set_global_assignment -name FMAX_REQUIREMENT "114 MHz"
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
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||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
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||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name USE_CONFIGURATION_DEVICE ON
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@@ -147,16 +146,16 @@ set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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||||
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
|
||||
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
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||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
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||||
|
||||
|
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out
|
||||
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
|
||||
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0
|
||||
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY OFF
|
||||
|
||||
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
@@ -203,7 +202,7 @@ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
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||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
|
||||
|
||||
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
|
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@@ -220,7 +219,7 @@ set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
|
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
|
||||
|
||||
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1]
|
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2]
|
||||
@@ -237,7 +236,7 @@ set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12]
|
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15]
|
||||
|
||||
|
||||
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_8
|
||||
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_128
|
||||
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SDRAM_CLK
|
||||
@@ -281,66 +280,105 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CLK
|
||||
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]
|
||||
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]
|
||||
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]
|
||||
|
||||
|
||||
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_32
|
||||
|
||||
|
||||
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION ON
|
||||
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R[5]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R[4]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R[3]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R[2]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B[5]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B[4]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B[3]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B[2]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G[5]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G[4]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G[3]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G[2]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_VS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_HS
|
||||
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to AUDIO_L
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to AUDIO_R
|
||||
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[0]
|
||||
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[0]
|
||||
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[0]
|
||||
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_HS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_VS
|
||||
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_L
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_R
|
||||
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to UART_RX
|
||||
set_global_assignment -name VERILOG_FILE sigma_delta_dac.v
|
||||
set_global_assignment -name SOURCE_FILE font8x8.memh
|
||||
set_global_assignment -name VERILOG_FILE overlay.v
|
||||
set_global_assignment -name VERILOG_FILE font.v
|
||||
set_global_assignment -name VERILOG_FILE scandoubler.v
|
||||
set_global_assignment -name VERILOG_FILE shifter.v
|
||||
set_global_assignment -name VERILOG_FILE sync_adjust.v
|
||||
set_global_assignment -name QIP_FILE pll_mfp1.qip
|
||||
set_global_assignment -name VERILOG_FILE acsi.v
|
||||
set_global_assignment -name VERILOG_FILE fdc.v
|
||||
set_global_assignment -name VERILOG_FILE mfp_srff16.v
|
||||
set_global_assignment -name VERILOG_FILE viking.v
|
||||
set_global_assignment -name VERILOG_FILE cache.v
|
||||
set_global_assignment -name VERILOG_FILE mste_ctrl.v
|
||||
set_global_assignment -name VERILOG_FILE ethernec.v
|
||||
set_global_assignment -name VERILOG_FILE osd.v
|
||||
set_global_assignment -name VERILOG_FILE video_modes.v
|
||||
set_global_assignment -name VERILOG_FILE blitter.v
|
||||
set_global_assignment -name VERILOG_FILE mfp_timer.v
|
||||
set_global_assignment -name VHDL_FILE vol_table_array.vhd
|
||||
set_global_assignment -name VHDL_FILE YM2149_volmix.vhd
|
||||
set_global_assignment -name VERILOG_FILE acia.v
|
||||
set_global_assignment -name VERILOG_FILE blitter.v
|
||||
set_global_assignment -name VHDL_FILE TG68K_ALU.vhd
|
||||
set_global_assignment -name VHDL_FILE TG68K_Pack.vhd
|
||||
set_global_assignment -name VHDL_FILE TG68KdotC_Kernel.vhd
|
||||
set_global_assignment -name SDC_FILE mist.sdc
|
||||
set_global_assignment -name VERILOG_FILE sdram.v
|
||||
set_global_assignment -name VERILOG_FILE clock.v
|
||||
set_global_assignment -name VERILOG_FILE mist_top.v
|
||||
set_global_assignment -name VERILOG_FILE user_io.v
|
||||
set_global_assignment -name VERILOG_FILE video.v
|
||||
set_global_assignment -name VERILOG_FILE shifter.v
|
||||
set_global_assignment -name VERILOG_FILE scandoubler.v
|
||||
set_global_assignment -name VERILOG_FILE overlay.v
|
||||
set_global_assignment -name VERILOG_FILE font.v
|
||||
set_global_assignment -name VERILOG_FILE sync_adjust.v
|
||||
set_global_assignment -name VERILOG_FILE viking.v
|
||||
set_global_assignment -name VERILOG_FILE video_modes.v
|
||||
set_global_assignment -name VERILOG_FILE io_fifo.v
|
||||
set_global_assignment -name VERILOG_FILE osd.v
|
||||
set_global_assignment -name VERILOG_FILE fdc.v
|
||||
set_global_assignment -name VERILOG_FILE acsi.v
|
||||
set_global_assignment -name VERILOG_FILE mfp.v
|
||||
set_global_assignment -name VERILOG_FILE dma.v
|
||||
set_global_assignment -name VERILOG_FILE sigma_delta_dac.v
|
||||
set_global_assignment -name VERILOG_FILE mmu.v
|
||||
set_global_assignment -name VERILOG_FILE ste_dma_snd.v
|
||||
set_global_assignment -name VERILOG_FILE audio.v
|
||||
set_global_assignment -name VERILOG_FILE ste_joystick.v
|
||||
set_global_assignment -name VERILOG_FILE mste_ctrl.v
|
||||
set_global_assignment -name QIP_FILE pll_mfp1.qip
|
||||
set_global_assignment -name VERILOG_FILE ste_dma_snd.v
|
||||
set_global_assignment -name SIGNALTAP_FILE data_io.stp
|
||||
set_global_assignment -name SIGNALTAP_FILE cpu.stp
|
||||
set_global_assignment -name SIGNALTAP_FILE sdram.stp
|
||||
set_global_assignment -name VERILOG_FILE sdram.v
|
||||
set_global_assignment -name SIGNALTAP_FILE tg68k.stp
|
||||
set_global_assignment -name SIGNALTAP_FILE tg68_bare.stp
|
||||
set_global_assignment -name SIGNALTAP_FILE irq.stp
|
||||
set_global_assignment -name SIGNALTAP_FILE cache.stp
|
||||
set_global_assignment -name VERILOG_FILE io_fifo.v
|
||||
set_global_assignment -name VERILOG_FILE mfp_hbit16.v
|
||||
set_global_assignment -name VERILOG_FILE audio.v
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -1,32 +1,129 @@
|
||||
module sigma_delta_dac(
|
||||
output reg DACout, //Average Output feeding analog lowpass
|
||||
input [MSBI:0] DACin, //DAC input (excess 2**MSBI)
|
||||
input CLK,
|
||||
input RESET
|
||||
// sigmadelta.v
|
||||
// two channel second order sigma delta dac
|
||||
// taken from Minimig
|
||||
|
||||
// audio data processing
|
||||
// stereo sigma/delta bitstream modulator
|
||||
module sigma_delta_dac (
|
||||
input clk, // bus clock
|
||||
input [14:0] ldatasum, // left channel data
|
||||
input [14:0] rdatasum, // right channel data
|
||||
output reg left=0, // left bitstream output
|
||||
output reg right=0 // right bitsteam output
|
||||
);
|
||||
|
||||
parameter MSBI = 7;
|
||||
//--------------------------------------------------------------------------------------
|
||||
|
||||
reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder
|
||||
reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder
|
||||
reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder
|
||||
reg [MSBI+2:0] DeltaB; //B input of Delta Adder
|
||||
// local signals
|
||||
localparam DW = 15;
|
||||
localparam CW = 2;
|
||||
localparam RW = 4;
|
||||
localparam A1W = 2;
|
||||
localparam A2W = 5;
|
||||
|
||||
always @ (*)
|
||||
DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
|
||||
wire [DW+2+0 -1:0] sd_l_er0, sd_r_er0;
|
||||
reg [DW+2+0 -1:0] sd_l_er0_prev=0, sd_r_er0_prev=0;
|
||||
wire [DW+A1W+2-1:0] sd_l_aca1, sd_r_aca1;
|
||||
wire [DW+A2W+2-1:0] sd_l_aca2, sd_r_aca2;
|
||||
reg [DW+A1W+2-1:0] sd_l_ac1=0, sd_r_ac1=0;
|
||||
reg [DW+A2W+2-1:0] sd_l_ac2=0, sd_r_ac2=0;
|
||||
wire [DW+A2W+3-1:0] sd_l_quant, sd_r_quant;
|
||||
|
||||
always @(*)
|
||||
DeltaAdder = DACin + DeltaB;
|
||||
|
||||
always @(*)
|
||||
SigmaAdder = DeltaAdder + SigmaLatch;
|
||||
|
||||
always @(posedge CLK or posedge RESET)
|
||||
if(RESET) begin
|
||||
SigmaLatch <= 1'b1 << (MSBI+1);
|
||||
DACout <= 1'b0;
|
||||
end else begin
|
||||
SigmaLatch <= SigmaAdder;
|
||||
DACout <= SigmaLatch[MSBI+2];
|
||||
end
|
||||
endmodule
|
||||
// LPF noise LFSR
|
||||
reg [24-1:0] seed1 = 24'h654321;
|
||||
reg [19-1:0] seed2 = 19'h12345;
|
||||
reg [24-1:0] seed_sum=0, seed_prev=0, seed_out=0;
|
||||
always @ (posedge clk) begin
|
||||
if (&seed1)
|
||||
seed1 <= #1 24'h654321;
|
||||
else
|
||||
seed1 <= #1 {seed1[22:0], ~(seed1[23] ^ seed1[22] ^ seed1[21] ^ seed1[16])};
|
||||
end
|
||||
always @ (posedge clk) begin
|
||||
if (&seed2)
|
||||
seed2 <= #1 19'h12345;
|
||||
else
|
||||
seed2 <= #1 {seed2[17:0], ~(seed2[18] ^ seed2[17] ^ seed2[16] ^ seed2[13] ^ seed2[0])};
|
||||
end
|
||||
always @ (posedge clk) begin
|
||||
seed_sum <= #1 seed1 + {5'b0, seed2};
|
||||
seed_prev <= #1 seed_sum;
|
||||
seed_out <= #1 seed_sum - seed_prev;
|
||||
end
|
||||
|
||||
// linear interpolate
|
||||
localparam ID=4; // counter size, also 2^ID = interpolation rate
|
||||
reg [ID+0-1:0] int_cnt = 0;
|
||||
always @ (posedge clk) int_cnt <= #1 int_cnt + 'd1;
|
||||
|
||||
reg [DW+0-1:0] ldata_cur=0, ldata_prev=0;
|
||||
reg [DW+0-1:0] rdata_cur=0, rdata_prev=0;
|
||||
wire [DW+1-1:0] ldata_step, rdata_step;
|
||||
reg [DW+ID-1:0] ldata_int=0, rdata_int=0;
|
||||
wire [DW+0-1:0] ldata_int_out, rdata_int_out;
|
||||
assign ldata_step = {ldata_cur[DW-1], ldata_cur} - {ldata_prev[DW-1], ldata_prev}; // signed subtract
|
||||
assign rdata_step = {rdata_cur[DW-1], rdata_cur} - {rdata_prev[DW-1], rdata_prev}; // signed subtract
|
||||
always @ (posedge clk) begin
|
||||
if (~|int_cnt) begin
|
||||
ldata_prev <= #1 ldata_cur;
|
||||
ldata_cur <= #1 ldatasum; //{~ldatasum[DW-1], ldatasum[DW-2:0]}; // convert to offset binary, samples no longer signed!
|
||||
rdata_prev <= #1 rdata_cur;
|
||||
rdata_cur <= #1 rdatasum; //{~rdatasum[DW-1], rdatasum[DW-2:0]}; // convert to offset binary, samples no longer signed!
|
||||
ldata_int <= #1 {ldata_cur[DW-1], ldata_cur, {ID{1'b0}}};
|
||||
rdata_int <= #1 {rdata_cur[DW-1], rdata_cur, {ID{1'b0}}};
|
||||
end else begin
|
||||
ldata_int <= #1 ldata_int + {{ID{ldata_step[DW+1-1]}}, ldata_step};
|
||||
rdata_int <= #1 rdata_int + {{ID{rdata_step[DW+1-1]}}, rdata_step};
|
||||
end
|
||||
end
|
||||
assign ldata_int_out = ldata_int[DW+ID-1:ID];
|
||||
assign rdata_int_out = rdata_int[DW+ID-1:ID];
|
||||
|
||||
// input gain x3
|
||||
wire [DW+2-1:0] ldata_gain, rdata_gain;
|
||||
assign ldata_gain = {ldata_int_out[DW-1], ldata_int_out, 1'b0} + {{(2){ldata_int_out[DW-1]}}, ldata_int_out};
|
||||
assign rdata_gain = {rdata_int_out[DW-1], rdata_int_out, 1'b0} + {{(2){rdata_int_out[DW-1]}}, rdata_int_out};
|
||||
|
||||
/*
|
||||
// random dither to 15 bits
|
||||
reg [DW-1:0] ldata=0, rdata=0;
|
||||
always @ (posedge clk) begin
|
||||
ldata <= #1 ldata_gain[DW+2-1:2] + ( (~(&ldata_gain[DW+2-1-1:2]) && (ldata_gain[1:0] > seed_out[1:0])) ? 15'd1 : 15'd0 );
|
||||
rdata <= #1 rdata_gain[DW+2-1:2] + ( (~(&ldata_gain[DW+2-1-1:2]) && (ldata_gain[1:0] > seed_out[1:0])) ? 15'd1 : 15'd0 );
|
||||
end
|
||||
*/
|
||||
|
||||
// accumulator adders
|
||||
assign sd_l_aca1 = {{(A1W){ldata_gain[DW+2-1]}}, ldata_gain} - {{(A1W){sd_l_er0[DW+2-1]}}, sd_l_er0} + sd_l_ac1;
|
||||
assign sd_r_aca1 = {{(A1W){rdata_gain[DW+2-1]}}, rdata_gain} - {{(A1W){sd_r_er0[DW+2-1]}}, sd_r_er0} + sd_r_ac1;
|
||||
|
||||
assign sd_l_aca2 = {{(A2W-A1W){sd_l_aca1[DW+A1W+2-1]}}, sd_l_aca1} - {{(A2W){sd_l_er0[DW+2-1]}}, sd_l_er0} - {{(A2W+1){sd_l_er0_prev[DW+2-1]}}, sd_l_er0_prev[DW+2-1:1]} + sd_l_ac2;
|
||||
assign sd_r_aca2 = {{(A2W-A1W){sd_r_aca1[DW+A1W+2-1]}}, sd_r_aca1} - {{(A2W){sd_r_er0[DW+2-1]}}, sd_r_er0} - {{(A2W+1){sd_r_er0_prev[DW+2-1]}}, sd_r_er0_prev[DW+2-1:1]} + sd_r_ac2;
|
||||
|
||||
// accumulators
|
||||
always @ (posedge clk) begin
|
||||
sd_l_ac1 <= #1 sd_l_aca1;
|
||||
sd_r_ac1 <= #1 sd_r_aca1;
|
||||
sd_l_ac2 <= #1 sd_l_aca2;
|
||||
sd_r_ac2 <= #1 sd_r_aca2;
|
||||
end
|
||||
|
||||
// value for quantizaton
|
||||
assign sd_l_quant = {sd_l_ac2[DW+A2W+2-1], sd_l_ac2} + {{(DW+A2W+3-RW){seed_out[RW-1]}}, seed_out[RW-1:0]};
|
||||
assign sd_r_quant = {sd_r_ac2[DW+A2W+2-1], sd_r_ac2} + {{(DW+A2W+3-RW){seed_out[RW-1]}}, seed_out[RW-1:0]};
|
||||
|
||||
// error feedback
|
||||
assign sd_l_er0 = sd_l_quant[DW+A2W+3-1] ? {1'b1, {(DW+2-1){1'b0}}} : {1'b0, {(DW+2-1){1'b1}}};
|
||||
assign sd_r_er0 = sd_r_quant[DW+A2W+3-1] ? {1'b1, {(DW+2-1){1'b0}}} : {1'b0, {(DW+2-1){1'b1}}};
|
||||
always @ (posedge clk) begin
|
||||
sd_l_er0_prev <= #1 (&sd_l_er0) ? sd_l_er0 : sd_l_er0+1;
|
||||
sd_r_er0_prev <= #1 (&sd_r_er0) ? sd_r_er0 : sd_r_er0+1;
|
||||
end
|
||||
|
||||
// output
|
||||
always @ (posedge clk) begin
|
||||
left <= #1 (~|ldata_gain) ? ~left : ~sd_l_er0[DW+2-1];
|
||||
right <= #1 (~|rdata_gain) ? ~right : ~sd_r_er0[DW+2-1];
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -125,18 +125,25 @@ overlay overlay (
|
||||
.val_d ( dbg_val_d ),
|
||||
.val_s ( dbg_val_s ),
|
||||
|
||||
.red_in ( {stvid_r, 2'b00}),
|
||||
.green_in ( {stvid_g, 2'b00}),
|
||||
.blue_in ( {stvid_b, 2'b00}),
|
||||
.hs_in ( stvid_hs ),
|
||||
.vs_in ( stvid_vs ),
|
||||
.red_in ( stvid6_r ),
|
||||
.green_in ( stvid6_g ),
|
||||
.blue_in ( stvid6_b ),
|
||||
.hs_in ( stvid_hs ),
|
||||
.vs_in ( stvid_vs ),
|
||||
|
||||
// receive signal with OSD overlayed
|
||||
.red_out ( ovl_r ),
|
||||
.green_out ( ovl_g ),
|
||||
.blue_out ( ovl_b )
|
||||
.red_out ( ovl_r ),
|
||||
.green_out ( ovl_g ),
|
||||
.blue_out ( ovl_b )
|
||||
);
|
||||
|
||||
// expand ST(E) 3/4 bit colors to MISTs 6 bit range
|
||||
// in 3 bit ST mode we can simply double each bit to achieve 6 bits
|
||||
// in 4 bit STE mode the mapping isn't linear
|
||||
wire [5:0] stvid6_r = ste?{stvid_r, stvid_r[3:2]}:{stvid_r[3:1],stvid_r[3:1]};
|
||||
wire [5:0] stvid6_g = ste?{stvid_g, stvid_g[3:2]}:{stvid_g[3:1],stvid_g[3:1]};
|
||||
wire [5:0] stvid6_b = ste?{stvid_b, stvid_b[3:2]}:{stvid_b[3:1],stvid_b[3:1]};
|
||||
|
||||
// ------------- combine scandoubled shifter with viking -------------
|
||||
wire [3:0] stvid_r = viking_enable?viking_r:shifter_sd_sblank_r;
|
||||
wire [3:0] stvid_g = viking_enable?viking_g:shifter_sd_sblank_g;
|
||||
@@ -146,9 +153,9 @@ wire stvid_vs = viking_enable?viking_vs:vga_vs;
|
||||
|
||||
// -------- make sure adjusted video blanks during sync phase -------
|
||||
wire n_sync_adjusted = shifter_sd_adjusted_hs && shifter_sd_adjusted_vs;
|
||||
wire [3:0] shifter_sd_sblank_r = n_sync_adjusted?shifter_sd_r:3'b000;
|
||||
wire [3:0] shifter_sd_sblank_g = n_sync_adjusted?shifter_sd_g:3'b000;
|
||||
wire [3:0] shifter_sd_sblank_b = n_sync_adjusted?shifter_sd_b:3'b000;
|
||||
wire [3:0] shifter_sd_sblank_r = n_sync_adjusted?shifter_sd_r:4'b0000;
|
||||
wire [3:0] shifter_sd_sblank_g = n_sync_adjusted?shifter_sd_g:4'b0000;
|
||||
wire [3:0] shifter_sd_sblank_b = n_sync_adjusted?shifter_sd_b:4'b0000;
|
||||
|
||||
// --------------- apply screen position adjustments -----------------
|
||||
|
||||
|
||||
Reference in New Issue
Block a user