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mirror of https://github.com/mist-devel/mist-board.git synced 2026-02-02 06:21:12 +00:00

Cleanup more registers on reset

This commit is contained in:
Sebastien Delestaing
2016-09-20 11:34:25 +02:00
parent f7ee9f1e4d
commit 2082bffe09
3 changed files with 30 additions and 18 deletions

View File

@@ -212,9 +212,9 @@ end
wire strt = (start_cnt != 0);
wire sel = (select_cnt != 0);
wire [7:0] nes_joy_A = { joyB[0], joyB[1], joyB[2], joyB[3],
wire [7:0] nes_joy_A = reset_nes ? 8'd0 : { joyB[0], joyB[1], joyB[2], joyB[3],
joyB[7] | strt, joyB[6] | sel, joyB[5], joyB[4] } | kbd_joy0;
wire [7:0] nes_joy_B = { joyA[0], joyA[1], joyA[2], joyA[3],
wire [7:0] nes_joy_B = reset_nes ? 8'd0 : { joyA[0], joyA[1], joyA[2], joyA[3],
joyA[7], joyA[6], joyA[5], joyA[4] } | kbd_joy1;
wire clock_locked;
@@ -264,16 +264,22 @@ wire [7:0] nes_joy_B = { joyA[0], joyA[1], joyA[2], joyA[3],
reg [1:0] nes_ce;
always @(posedge clk) begin
if (joypad_strobe) begin
joypad_bits <= nes_joy_A;
joypad_bits2 <= nes_joy_B;
end
if (!joypad_clock[0] && last_joypad_clock[0])
joypad_bits <= {1'b0, joypad_bits[7:1]};
if (!joypad_clock[1] && last_joypad_clock[1])
joypad_bits2 <= {1'b0, joypad_bits2[7:1]};
last_joypad_clock <= joypad_clock;
always @(posedge clk) begin
if (reset_nes) begin
joypad_bits <= 8'd0;
joypad_bits2 <= 8'd0;
last_joypad_clock <= 2'b00;
end else begin
if (joypad_strobe) begin
joypad_bits <= nes_joy_A;
joypad_bits2 <= nes_joy_B;
end
if (!joypad_clock[0] && last_joypad_clock[0])
joypad_bits <= {1'b0, joypad_bits[7:1]};
if (!joypad_clock[1] && last_joypad_clock[1])
joypad_bits2 <= {1'b0, joypad_bits2[7:1]};
last_joypad_clock <= joypad_clock;
end
end
@@ -291,7 +297,6 @@ wire [7:0] nes_joy_B = { joyA[0], joyA[1], joyA[2], joyA[3],
mapper_flags, loader_done, loader_fail);
wire reset_nes = (init_reset || buttons[1] || arm_reset || reset_osd || download_reset);
wire run_mem = (nes_ce == 0) && !reset_nes;
wire run_nes = (nes_ce == 3) && !reset_nes;
// NES is clocked at every 4th cycle.

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@@ -38,8 +38,10 @@ assign joystick_1 = joy_num ? buttons : 7'b0;
always @(posedge reset or posedge clk) begin
if(reset) begin
pressed <= 1'b1;
pressed <= 1'b0;
e0 <= 1'b0;
joy_num <= 1'b0;
buttons <= 8'd0;
end else begin
if (keyb_valid) begin
if (keyb_data == 8'HE0)

View File

@@ -93,7 +93,7 @@ endmodule
// Data read by PPU will be available on the next clock cycle.
// Data read by CPU will be available within at most 2 clock cycles.
module MemoryMultiplex(input clk, input ce,
module MemoryMultiplex(input clk, input ce, input reset,
input [21:0] prg_addr, input prg_read, input prg_write, input [7:0] prg_din,
input [21:0] chr_addr, input chr_read, input chr_write, input [7:0] chr_din,
// Access signals for the SRAM.
@@ -108,7 +108,10 @@ module MemoryMultiplex(input clk, input ce,
assign memory_read_ppu = chr_read;
assign memory_read_cpu = !(chr_read || chr_write) && (prg_read || saved_prg_read);
assign memory_dout = chr_write ? chr_din : prg_din;
always @(posedge clk) if (ce) begin
always @(posedge clk) if (reset) begin
saved_prg_read <= 0;
saved_prg_write <= 0;
end else if (ce) begin
if (chr_read || chr_write) begin
saved_prg_read <= prg_read || saved_prg_read;
saved_prg_write <= prg_write || saved_prg_write;
@@ -280,12 +283,14 @@ module NES(input clk, input reset, input ce,
end
// -- Multiplexes CPU and PPU accesses into one single RAM
MemoryMultiplex mem(clk, ce, prg_linaddr, prg_read && prg_allow, prg_write && prg_allow, prg_din,
MemoryMultiplex mem(clk, ce, reset, prg_linaddr, prg_read && prg_allow, prg_write && prg_allow, prg_din,
chr_linaddr, chr_read, chr_write && (chr_allow || vram_ce), chr_from_ppu,
memory_addr, memory_read_cpu, memory_read_ppu, memory_write, memory_dout);
always @* begin
if (apu_cs) begin
if (reset)
from_data_bus <= 0;
else if (apu_cs) begin
if (joypad1_cs)
from_data_bus = {7'b0100000, joypad_data[0]};
else if (joypad2_cs)