BBC: Update VIA

cores/bbc/fpga/mist/bbc_mist_top.qsf

@@ -193,7 +193,7 @@ set_global_assignment -name VERILOG_FILE clockgen.v
 set_global_assignment -name VERILOG_FILE ../rtl/scandoubler.v
 set_global_assignment -name VERILOG_FILE ../../rtl/bbc.v
 set_global_assignment -name CDF_FILE output_files/Chain4.cdf
-set_global_assignment -name VERILOG_FILE ../../rtl/m6522.v
+set_global_assignment -name VHDL_FILE ../../rtl/m6522.vhd
 set_global_assignment -name QIP_FILE smmc.qip
 set_global_assignment -name QIP_FILE os12.qip
 set_global_assignment -name QIP_FILE basic2.qip

cores/bbc/fpga/mist/bbc_mist_top.v

@@ -208,31 +208,29 @@ user_io #(.STRLEN(CONF_STR_LEN)) user_io(
 );
 
 // wire the sd card to the user port
-wire sd_sck = user_via_pb_out[1];
-wire sd_cs = 1'b0;
-wire sd_sdi = user_via_pb_out[0];
-wire sd_sdo = user_via_cb2_in;
-assign user_via_cb1_in = user_via_pb_out[1];
+wire sd_sck;
+wire sd_cs;
+wire sd_sdi;
+wire sd_sdo;
 
-sd_card sd_card (
-   // connection to io controller
+ sd_card sd_card (
+	// connection to io controller
 	.clk(clk_32m),
-   .io_lba (sd_lba ),
-   .io_rd  (sd_rd),
-   .io_wr  (sd_wr),
-   .io_ack (sd_ack),
+	.io_lba (sd_lba ),
+	.io_rd  (sd_rd),
+	.io_wr  (sd_wr),
+	.io_ack (sd_ack),
 	.io_ack_conf (sd_ack_conf      ),
-   .io_conf (sd_conf),
-   .io_sdhc (sd_sdhc),
-   .io_din (sd_dout),
-   .io_din_strobe (sd_dout_strobe),
-   .io_dout (sd_din),
-   .io_dout_strobe ( sd_din_strobe),
+	.io_conf (sd_conf),
+	.io_sdhc (sd_sdhc),
+	.io_din (sd_dout),
+	.io_din_strobe (sd_dout_strobe),
+	.io_dout (sd_din),
+	.io_dout_strobe ( sd_din_strobe),
 	.io_buff_addr  (sd_buff_addr     ),
- 
    .allow_sdhc ( 1'b1),   // SDHC not supported
-
-   // connection to local CPU
+ 
+    // connection to local CPU
    .sd_cs   ( sd_cs          ),
    .sd_sck  ( sd_sck         ),
    .sd_sdi  ( sd_sdi         ),
@@ -325,11 +323,12 @@ bbc BBC(
     .VID_ADR    ( vid_adr       ),
     .VID_DI     ( vid_data      ),
 	
-    .SHIFT     ( autoboot_shift ),
-	
-	 .user_via_pb_out ( user_via_pb_out   ),
-	 .user_via_cb1_in ( user_via_cb1_in   ),
-	 .user_via_cb2_in ( user_via_cb2_in   ),
+    .SHIFT      ( autoboot_shift ),
+
+	 .SDCLK      (sd_sck         ),
+	 .SDSS       (sd_cs          ),
+	 .SDMISO     (sd_sdo         ),
+	 .SDMOSI     (sd_sdi         ),
 
 	 .joy_but    ( { joystick_1[4], joystick_0[4] } ),
 	 .joy0_axis0 ( joystick_analog_0[15:8] ),
@@ -467,7 +466,6 @@ wire sideways_ram =
 
 // status[2] is '1' of low mapping is selected in the menu
 wire basic_map = status[2]?(mem_romsel == 4'h0):(mem_romsel == 4'he);
-//wire smmc_map = 0;
 wire smmc_map = status[2]?(mem_romsel == 4'h2):(mem_romsel == 4'hc);
 	
 assign mem_di = 

cores/bbc/rtl/bbc.v

@@ -38,11 +38,11 @@ module bbc(
 
 	// externally pressed "shift" key for autoboot
 	input          SHIFT,
-	
-	// expose pins required for mmc
-	output [7:0]   user_via_pb_out,
-	input          user_via_cb1_in,
-	input          user_via_cb2_in,
+
+	output         SDSS,
+	output         SDCLK,
+	output         SDMOSI,
+	input          SDMISO,
 	
 	// analog joystick input 
 	input [1:0]	 	joy_but,
@@ -176,7 +176,8 @@ wire    [7:0] sound_di;
 wire    [7:0] sound_ao;
 
 //  System VIA signals
-wire    [7:0] sys_via_do; 
+wire    [7:0] sys_via_do;
+reg     [7:0] sys_via_do_r;
 wire    sys_via_do_oe_n; 
 wire    sys_via_irq_n; 
 wire     sys_via_ca1_in; 
@@ -197,7 +198,8 @@ wire    [7:0] sys_via_pb_out;
 wire    [7:0] sys_via_pb_oe_n; 
 
 //  User VIA signals
-wire    [7:0] user_via_do; 
+wire    [7:0] user_via_do;
+reg     [7:0] user_via_do_r;
 wire    user_via_do_oe_n; 
 wire    user_via_irq_n; 
 reg     user_via_ca1_in; 
@@ -207,16 +209,28 @@ wire    user_via_ca2_oe_n;
 wire    [7:0] user_via_pa_in; 
 wire    [7:0] user_via_pa_out; 
 wire    [7:0] user_via_pa_oe_n; 
-//TH wire     user_via_cb1_in; 
+wire     user_via_cb1_in; 
 wire    user_via_cb1_out; 
 wire    user_via_cb1_oe_n; 
-//TH wire     user_via_cb2_in; 
+wire     user_via_cb2_in; 
 wire    user_via_cb2_out; 
 wire    user_via_cb2_oe_n; 
 wire    [7:0] user_via_pb_in; 
-//TH wire    [7:0] user_via_pb_out; 
+wire    [7:0] user_via_pb_out; 
 wire    [7:0] user_via_pb_oe_n; 
 
+// MMC
+// SDCLK is driven from either PB1 or CB1 depending on the SR Mode
+wire   sdclk_int = ~user_via_pb_oe_n[1] ? user_via_pb_out[1] : 
+						(~user_via_cb1_oe_n ? user_via_cb1_out : 1);
+assign SDCLK = sdclk_int;
+assign user_via_cb1_in = sdclk_int;
+// SDMOSI is always driven from PB0
+assign SDMOSI = ~user_via_pb_oe_n[0] ? user_via_pb_out[0] : 1;
+// SDMISO is always read from CB2
+assign user_via_cb2_in = SDMISO;
+assign SDSS = 0;
+
 // calulation for display address
 
 reg     [3:0]  process_3_aa; 
@@ -297,38 +311,44 @@ cpu CPU (
 
 assign cpu_r_nw = ~cpu_we;
 
-
 m6522 SYS_VIA (	
 	  //  System VIA is reset by power on reset only
-	 .ENA_4(mhz4_clken),
-	 .CLK(CLK32M_I),
+
 	 .I_RS(cpu_a[3:0]),
 	 .I_DATA(cpu_do),
 	 .O_DATA(sys_via_do),
 	 .O_DATA_OE_L(sys_via_do_oe_n),
+
 	 .I_RW_L(cpu_r_nw),
 	 .I_CS1(sys_via_enable),
 	 .I_CS2_L(1'b 0), // nCS2(1'b 0),	 
 	 .O_IRQ_L(sys_via_irq_n),
- 	 .I_P2_H(mhz1_clken),
-	 .RESET_L(reset_n),
-	 
+
 	 .I_CA1(sys_via_ca1_in),
 	 .I_CA2(sys_via_ca2_in),
 	 .O_CA2(sys_via_ca2_out),
 	 .O_CA2_OE_L(sys_via_ca2_oe_n),
+
 	 .I_PA(sys_via_pa_in),
 	 .O_PA(sys_via_pa_out),
 	 .O_PA_OE_L(sys_via_pa_oe_n),
+
 	 .I_CB1(sys_via_cb1_in),
 	 .O_CB1(sys_via_cb1_out),
 	 .O_CB1_OE_L(sys_via_cb1_oe_n),
+
 	 .I_CB2(sys_via_cb2_in),
 	 .O_CB2(sys_via_cb2_out),
 	 .O_CB2_OE_L(sys_via_cb2_oe_n),
+
 	 .I_PB(sys_via_pb_in),
 	 .O_PB(sys_via_pb_out),
-	 .O_PB_OE_L(sys_via_pb_oe_n)
+	 .O_PB_OE_L(sys_via_pb_oe_n),
+
+	 .I_P2_H(mhz1_clken),
+	 .RESET_L(reset_n),
+	 .ENA_4(mhz4_clken),
+	 .CLK(CLK32M_I)
 );
 
 m6522 USER_VIA (	
@@ -490,6 +510,15 @@ initial begin : via_init
 	
 end
 
+// This is needed as in v003 of the 6522 data out is only valid while I_P2_H is asserted
+// I_P2_H is driven from mhz1_clken
+always @(posedge CLK32M_I) begin 
+	if (mhz1_clken) begin
+		user_via_do_r <= user_via_do;
+		sys_via_do_r  <= sys_via_do;
+	end
+end
+
 // rom select latch
 always @(posedge CLK32M_I) begin 
 
@@ -619,8 +648,8 @@ assign cpu_di = ram_enable === 1'b 1 ? MEM_DI :
 	mos_enable === 1'b 1 ? MEM_DI :
 	crtc_enable === 1'b 1 ? crtc_do : 
 	acia_enable === 1'b 1 ? 8'b 00000010 : 
-	sys_via_enable === 1'b 1 ? sys_via_do : 
-	user_via_enable === 1'b 1 ? user_via_do : 
+	sys_via_enable === 1'b 1 ? sys_via_do_r : 
+	user_via_enable === 1'b 1 ? user_via_do_r : 
 	adc_enable === 1'b 1 ? adc_do : 
 	//tube_enable === 1'b 1 ? tube_do : 
 	//adlc_enable === 1'b 1 ? bbcddr_out :