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Import of Atari ST core

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harbaum
2013-03-25 13:38:58 +00:00
commit 32457ab86e
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53
cores/mist/Makefile Normal file
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### programs ###
MAP=quartus_map
FIT=quartus_fit
ASM=quartus_asm
PGM=quartus_pgm
### project ###
PROJECT=mist
TODAY = `date +"%m/%d/%y"`
### build rules ###
# all
all:
@echo Making FPGA programming files ...
@make map
@make fit
@make asm
map:
@echo Running mapper ...
@$(MAP) $(PROJECT)
fit:
@echo Running fitter ...
@$(FIT) $(PROJECT)
asm:
@echo Running assembler ...
@$(ASM) $(PROJECT)
run:
@$(PGM) -c USB-Blaster -m jtag -o "p;./out/$(PROJECT).sof"
run2:
@$(PGM) -c USB-Blaster\(Altera\) -m jtag -o "p;./out/$(PROJECT).sof"
# clean
clean:
@echo clean
@rm -rf ./out/
@rm -rf ./db/
@rm -rf ./incremental_db/
release:
make
cd ./out; cp mist.rbf core.rbf ; cp ../../../tos/system.fnt .; cp ../readme.txt .; zip ../../../www/mist.zip core.rbf system.fnt readme.txt ; rm core.rbf system.fnt
make clean
cd ..; tar --exclude=.svn --exclude=old --exclude=old --exclude=*.orig --exclude=\*.bak --exclude=Makefile --exclude=greybox_tmp --exclude=out --exclude=db --exclude=incremental_db --exclude=\*~ -z -c -v -f ../www/mist_hdl.tgz mist-core-atarist
cp ../../www/files.html files.tmp
sed -e "s|Mist core updated on [0-9/]*.|Mist core updated on $(TODAY).|g" files.tmp > ../../www/files.html
rm files.tmp

426
cores/mist/TG68K.vhd Normal file
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------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2011 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This is the TOP-Level for TG68KdotC_Kernel to generate 68K Bus signals --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TG68K is
port(
clk : in std_logic;
reset : in std_logic;
clkena_in : in std_logic:='1';
IPL : in std_logic_vector(2 downto 0):="111";
berr : in std_logic:='0';
dtack : in std_logic;
vpa : in std_logic:='1';
ein : in std_logic:='1';
addr : buffer std_logic_vector(31 downto 0);
data_read : in std_logic_vector(15 downto 0);
data_write : out std_logic_vector(15 downto 0);
as : out std_logic;
uds : out std_logic;
lds : out std_logic;
rw : out std_logic;
e : out std_logic;
vma : buffer std_logic:='1';
wrd : out std_logic;
ena7RDreg : in std_logic:='1';
ena7WRreg : in std_logic:='1';
enaWRreg : in std_logic:='1';
fromram : in std_logic_vector(15 downto 0);
ramready : in std_logic:='0';
cpu : in std_logic_vector(1 downto 0);
memcfg : in std_logic_vector(5 downto 0);
ramaddr : out std_logic_vector(31 downto 0);
cpustate : out std_logic_vector(5 downto 0);
nResetOut : out std_logic;
skipFetch : out std_logic;
cpuDMA : buffer std_logic;
ramlds : out std_logic;
ramuds : out std_logic
);
end TG68K;
ARCHITECTURE logic OF TG68K IS
COMPONENT TG68KdotC_Kernel
generic(
SR_Read : integer:= 2; --0=>user, 1=>privileged, 2=>switchable with CPU(0)
VBR_Stackframe : integer:= 2; --0=>no, 1=>yes/extended, 2=>switchable with CPU(0)
extAddr_Mode : integer:= 2; --0=>no, 1=>yes, 2=>switchable with CPU(1)
MUL_Mode : integer := 2; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode : integer := 2; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
BitField : integer := 2 --0=>no, 1=>yes, 2=>switchable with CPU(1)
);
port(clk : in std_logic;
nReset : in std_logic; --low active
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
IPL_autovector : in std_logic:='0';
berr : in std_logic:='0';
CPU : in std_logic_vector(1 downto 0):="00"; -- 00->68000 01->68010 11->68020(only same parts - yet)
addr : buffer std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
nWr : out std_logic;
nUDS, nLDS : out std_logic;
nResetOut : out std_logic;
FC : out std_logic_vector(2 downto 0);
-- for debug
busstate : out std_logic_vector(1 downto 0); -- 00-> fetch code 10->read data 11->write data 01->no memaccess
skipFetch : out std_logic;
regin : buffer std_logic_vector(31 downto 0)
);
END COMPONENT;
SIGNAL cpuaddr : std_logic_vector(31 downto 0);
SIGNAL t_addr : std_logic_vector(31 downto 0);
-- SIGNAL data_write : std_logic_vector(15 downto 0);
-- SIGNAL t_data : std_logic_vector(15 downto 0);
SIGNAL r_data : std_logic_vector(15 downto 0);
SIGNAL cpuIPL : std_logic_vector(2 downto 0);
SIGNAL addr_akt_s : std_logic;
SIGNAL addr_akt_e : std_logic;
SIGNAL data_akt_s : std_logic;
SIGNAL data_akt_e : std_logic;
SIGNAL as_s : std_logic;
SIGNAL as_e : std_logic;
SIGNAL uds_s : std_logic;
SIGNAL uds_e : std_logic;
SIGNAL lds_s : std_logic;
SIGNAL lds_e : std_logic;
SIGNAL rw_s : std_logic;
SIGNAL rw_e : std_logic;
SIGNAL vpad : std_logic;
SIGNAL waitm : std_logic;
SIGNAL clkena_e : std_logic;
SIGNAL S_state : std_logic_vector(1 downto 0);
SIGNAL S_stated : std_logic_vector(1 downto 0);
SIGNAL decode : std_logic;
SIGNAL wr : std_logic;
SIGNAL uds_in : std_logic;
SIGNAL berr_in : std_logic;
SIGNAL lds_in : std_logic;
SIGNAL state : std_logic_vector(1 downto 0);
SIGNAL clkena : std_logic;
-- SIGNAL n_clk : std_logic;
SIGNAL vmaena : std_logic;
SIGNAL vmaenad : std_logic;
SIGNAL state_ena : std_logic;
SIGNAL sync_state3 : std_logic;
SIGNAL eind : std_logic;
SIGNAL eindd : std_logic;
SIGNAL sel_autoconfig: std_logic;
SIGNAL autoconfig_out: std_logic;
SIGNAL autoconfig_data: std_logic_vector(3 downto 0);
SIGNAL sel_fast: std_logic;
SIGNAL slower : std_logic_vector(3 downto 0);
type sync_states is (sync0, sync1, sync2, sync3, sync4, sync5, sync6, sync7, sync8, sync9);
signal sync_state : sync_states;
SIGNAL datatg68 : std_logic_vector(15 downto 0);
SIGNAL ramcs : std_logic;
BEGIN
-- n_clk <= NOT clk;
-- wrd <= data_akt_e OR data_akt_s;
wrd <= wr;
addr <= cpuaddr;-- WHEN addr_akt_e='1' ELSE t_addr WHEN addr_akt_s='1' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
-- data <= data_write WHEN data_akt_e='1' ELSE t_data WHEN data_akt_s='1' ELSE "ZZZZZZZZZZZZZZZZ";
-- datatg68 <= fromram WHEN sel_fast='1' ELSE r_data;
datatg68 <= fromram WHEN sel_fast='1' ELSE r_data WHEN sel_autoconfig='0' ELSE autoconfig_data&r_data(11 downto 0);
-- toram <= data_write;
sel_autoconfig <= '1' when cpuaddr(23 downto 19)="11101" AND autoconfig_out='1' ELSE '0'; --$E80000 - $EFFFFF
--TH sel_fast <= '1' when state/="01" AND (cpuaddr(23 downto 21)="001" OR cpuaddr(23 downto 21)="010" OR cpuaddr(23 downto 21)="011" OR cpuaddr(23 downto 21)="100") ELSE '0'; --$200000 - $9FFFFF
-- sel_fast <= '1' when cpuaddr(23 downto 21)="001" OR cpuaddr(23 downto 21)="010" ELSE '0'; --$200000 - $5FFFFF
-- sel_fast <= '1' when cpuaddr(23 downto 19)="11111" ELSE '0'; --$F800000;
sel_fast <= '0'; --$200000 - $9FFFFF
-- sel_fast <= '1' when cpuaddr(24)='1' AND state/="01" ELSE '0'; --$1000000 - $1FFFFFF
ramcs <= (NOT sel_fast) or slower(0);-- OR (state(0) AND NOT state(1));
-- cpuDMA <= NOT ramcs;
cpuDMA <= sel_fast;
cpustate <= clkena&slower(1 downto 0)&ramcs&state;
ramlds <= lds_in;
ramuds <= uds_in;
-- ramaddr(23 downto 0) <= cpuaddr(23 downto 0);
-- ramaddr(24) <= sel_fast;
-- ramaddr(31 downto 25) <= cpuaddr(31 downto 25);
ramaddr(23 downto 0) <= cpuaddr(23) & sel_fast & cpuaddr(21 downto 0);
ramaddr(31 downto 24) <= cpuaddr(31 downto 24);
pf68K_Kernel_inst: TG68KdotC_Kernel
generic map(
SR_Read => 2, --0=>user, 1=>privileged, 2=>switchable with CPU(0)
VBR_Stackframe => 2, --0=>no, 1=>yes/extended, 2=>switchable with CPU(0)
extAddr_Mode => 2, --0=>no, 1=>yes, 2=>switchable with CPU(1)
MUL_Mode => 2, --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode => 2 --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
)
PORT MAP(
clk => clk, -- : in std_logic;
nReset => reset, -- : in std_logic:='1'; --low active
clkena_in => clkena, -- : in std_logic:='1';
-- data_in => r_data, -- : in std_logic_vector(15 downto 0);
-- data_in => data_read, -- : in std_logic_vector(15 downto 0);
data_in => datatg68, -- : in std_logic_vector(15 downto 0);
IPL => cpuIPL, -- : in std_logic_vector(2 downto 0):="111";
IPL_autovector => '0', -- TH -- : in std_logic:='0';
addr => cpuaddr, -- : buffer std_logic_vector(31 downto 0);
data_write => data_write, -- : out std_logic_vector(15 downto 0);
berr => berr_in,
busstate => state, -- : buffer std_logic_vector(1 downto 0);
regin => open, -- : out std_logic_vector(31 downto 0);
nWr => wr, -- : out std_logic;
nUDS => uds_in,
nLDS => lds_in, -- : out std_logic;
nResetOut => nResetOut,
CPU => cpu,
skipFetch => skipFetch -- : out std_logic
);
PROCESS (clk)
BEGIN
autoconfig_data <= "1111";
IF memcfg(5 downto 4)/="00" THEN
CASE cpuaddr(6 downto 1) IS
WHEN "000000" => autoconfig_data <= "1110"; --normal card, add mem, no ROM
WHEN "000001" =>
CASE memcfg(5 downto 4) IS
WHEN "01" => autoconfig_data <= "0110"; --2MB
WHEN "10" => autoconfig_data <= "0111"; --4MB
-- WHEN OTHERS => autoconfig_data <= "0000"; --8MB
WHEN OTHERS => autoconfig_data <= "0111"; --4MB
END CASE;
WHEN "001000" => autoconfig_data <= "1110"; --4626=icomp
WHEN "001001" => autoconfig_data <= "1101";
WHEN "001010" => autoconfig_data <= "1110";
WHEN "001011" => autoconfig_data <= "1101";
WHEN "010011" => autoconfig_data <= "1110"; --serial=1
WHEN OTHERS => null;
END CASE;
END IF;
IF rising_edge(clk) THEN
IF reset='0' THEN
autoconfig_out <= '1'; --autoconfig on
ELSIF enaWRreg='1' THEN
IF sel_autoconfig='1' AND state="11"AND uds_in='0' AND cpuaddr(6 downto 1)="100100" THEN
autoconfig_out <= '0'; --autoconfig off
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF reset='0' THEN
vmaena <= '0';
vmaenad <= '0';
sync_state3 <= '0';
ELSIF ena7RDreg='1' THEN
vmaena <= '0';
sync_state3 <= '0';
IF state/="01" OR state_ena='1' THEN
vmaenad <= vmaena;
END IF;
IF sync_state=sync5 THEN
e <= '1';
END IF;
IF sync_state=sync3 THEN
sync_state3 <= '1';
END IF;
IF sync_state=sync9 THEN
e <= '0';
vmaena <= NOT vma;
END IF;
END IF;
END IF;
IF rising_edge(clk) THEN
S_stated <= S_state;
IF ena7WRreg='1' THEN
eind <= ein;
eindd <= eind;
CASE sync_state IS
WHEN sync0 => sync_state <= sync1;
WHEN sync1 => sync_state <= sync2;
WHEN sync2 => sync_state <= sync3;
WHEN sync3 => sync_state <= sync4;
vma <= vpa;
WHEN sync4 => sync_state <= sync5;
WHEN sync5 => sync_state <= sync6;
WHEN sync6 => sync_state <= sync7;
WHEN sync7 => sync_state <= sync8;
WHEN sync8 => sync_state <= sync9;
WHEN OTHERS => sync_state <= sync0;
vma <= '1';
END CASE;
IF eind='1' AND eindd='0' THEN
sync_state <= sync7;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
state_ena <= '0';
IF clkena_in='1' AND enaWRreg='1' AND (state="01" OR (ena7RDreg='1' AND clkena_e='1') OR ramready='1') THEN
clkena <= '1';
ELSE
clkena <= '0';
END IF;
IF state="01" THEN
state_ena <= '1';
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
slower <= "0111";
ELSE
slower(3 downto 0) <= '0'&slower(3 downto 1); -- enaWRreg&slower(3 downto 1);
-- slower(0) <= NOT slower(3) AND NOT slower(2);
END IF;
END IF;
END PROCESS;
PROCESS (clk, reset, state, as_s, as_e, rw_s, rw_e, uds_s, uds_e, lds_s, lds_e)
BEGIN
IF state="01" THEN
as <= '1';
rw <= '1';
uds <= '1';
lds <= '1';
ELSE
as <= (as_s AND as_e) OR sel_fast;
rw <= rw_s AND rw_e;
uds <= uds_s AND uds_e;
lds <= lds_s AND lds_e;
END IF;
IF reset='0' THEN
S_state <= "00";
as_s <= '1';
rw_s <= '1';
uds_s <= '1';
lds_s <= '1';
addr_akt_s <= '0';
data_akt_s <= '0';
ELSIF rising_edge(clk) THEN
IF ena7WRreg='1' THEN
as_s <= '1';
rw_s <= '1';
uds_s <= '1';
lds_s <= '1';
addr_akt_s <= '0';
data_akt_s <= '0';
CASE S_state IS
WHEN "00" => IF state/="01" AND sel_fast='0' THEN
uds_s <= uds_in;
lds_s <= lds_in;
S_state <= "01";
END IF;
WHEN "01" => as_s <= '0';
rw_s <= wr;
uds_s <= uds_in;
lds_s <= lds_in;
S_state <= "10";
t_addr <= cpuaddr;
-- t_data <= data_write;
WHEN "10" =>
addr_akt_s <= '1';
data_akt_s <= NOT wr;
r_data <= data_read;
IF waitm='0' OR (vma='0' AND sync_state=sync9) THEN
S_state <= "11";
ELSE
as_s <= '0';
rw_s <= wr;
uds_s <= uds_in;
lds_s <= lds_in;
END IF;
WHEN "11" =>
S_state <= "00";
WHEN OTHERS => null;
END CASE;
END IF;
END IF;
IF reset='0' THEN
as_e <= '1';
rw_e <= '1';
uds_e <= '1';
lds_e <= '1';
clkena_e <= '0';
addr_akt_e <= '0';
data_akt_e <= '0';
berr_in <= '0';
ELSIF rising_edge(clk) THEN
IF ena7RDreg='1' THEN
as_e <= '1';
rw_e <= '1';
uds_e <= '1';
lds_e <= '1';
clkena_e <= '0';
addr_akt_e <= '0';
data_akt_e <= '0';
CASE S_state IS
WHEN "00" => addr_akt_e <= '1';
cpuIPL <= IPL;
IF sel_fast='0' THEN
IF state/="01" THEN
as_e <= '0';
END IF;
rw_e <= wr;
data_akt_e <= NOT wr;
IF wr='1' THEN
uds_e <= uds_in;
lds_e <= lds_in;
END IF;
END IF;
WHEN "01" => addr_akt_e <= '1';
data_akt_e <= NOT wr;
as_e <= '0';
rw_e <= wr;
uds_e <= uds_in;
lds_e <= lds_in;
WHEN "10" => rw_e <= wr;
addr_akt_e <= '1';
data_akt_e <= NOT wr;
cpuIPL <= IPL;
waitm <= dtack AND NOT berr;
berr_in <= berr;
WHEN OTHERS => --null;
clkena_e <= '1';
END CASE;
END IF;
END IF;
END PROCESS;
END;

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------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2011 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use work.TG68K_Pack.all;
entity TG68K_ALU is
generic(
MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode : integer := 0 --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
);
port(clk : in std_logic;
Reset : in std_logic;
clkena_lw : in std_logic:='1';
execOPC : in bit;
exe_condition : in std_logic;
exec_tas : in std_logic;
long_start : in bit;
movem_presub : in bit;
set_stop : in bit;
Z_error : in bit;
rot_bits : in std_logic_vector(1 downto 0);
exec : in bit_vector(lastOpcBit downto 0);
OP1out : in std_logic_vector(31 downto 0);
OP2out : in std_logic_vector(31 downto 0);
reg_QA : in std_logic_vector(31 downto 0);
reg_QB : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(15 downto 0);
datatype : in std_logic_vector(1 downto 0);
exe_opcode : in std_logic_vector(15 downto 0);
exe_datatype : in std_logic_vector(1 downto 0);
sndOPC : in std_logic_vector(15 downto 0);
last_data_read : in std_logic_vector(15 downto 0);
data_read : in std_logic_vector(15 downto 0);
FlagsSR : in std_logic_vector(7 downto 0);
micro_state : in micro_states;
bf_ext_in : in std_logic_vector(7 downto 0);
bf_ext_out : out std_logic_vector(7 downto 0);
bf_shift : in std_logic_vector(5 downto 0);
bf_width : in std_logic_vector(5 downto 0);
bf_loffset : in std_logic_vector(4 downto 0);
set_V_Flag : buffer bit;
Flags : buffer std_logic_vector(7 downto 0);
c_out : buffer std_logic_vector(2 downto 0);
addsub_q : buffer std_logic_vector(31 downto 0);
ALUout : out std_logic_vector(31 downto 0)
);
end TG68K_ALU;
architecture logic of TG68K_ALU is
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- ALU and more
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
signal OP1in : std_logic_vector(31 downto 0);
signal addsub_a : std_logic_vector(31 downto 0);
signal addsub_b : std_logic_vector(31 downto 0);
signal notaddsub_b : std_logic_vector(33 downto 0);
signal add_result : std_logic_vector(33 downto 0);
signal addsub_ofl : std_logic_vector(2 downto 0);
signal opaddsub : bit;
signal c_in : std_logic_vector(3 downto 0);
signal flag_z : std_logic_vector(2 downto 0);
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
signal CCRin : std_logic_vector(7 downto 0);
signal niba_l : std_logic_vector(5 downto 0);
signal niba_h : std_logic_vector(5 downto 0);
signal niba_lc : std_logic;
signal niba_hc : std_logic;
signal bcda_lc : std_logic;
signal bcda_hc : std_logic;
signal nibs_l : std_logic_vector(5 downto 0);
signal nibs_h : std_logic_vector(5 downto 0);
signal nibs_lc : std_logic;
signal nibs_hc : std_logic;
signal bcd_a : std_logic_vector(8 downto 0);
signal bcd_s : std_logic_vector(8 downto 0);
signal result_mulu : std_logic_vector(63 downto 0);
signal result_div : std_logic_vector(63 downto 0);
signal set_mV_Flag : std_logic;
signal V_Flag : bit;
signal rot_rot : std_logic;
signal rot_lsb : std_logic;
signal rot_msb : std_logic;
signal rot_X : std_logic;
signal rot_C : std_logic;
signal rot_out : std_logic_vector(31 downto 0);
signal asl_VFlag : std_logic;
signal bit_bits : std_logic_vector(1 downto 0);
signal bit_number : std_logic_vector(4 downto 0);
signal bits_out : std_logic_vector(31 downto 0);
signal one_bit_in : std_logic;
signal bchg : std_logic;
signal bset : std_logic;
signal mulu_sign : std_logic;
signal mulu_signext : std_logic_vector(16 downto 0);
signal muls_msb : std_logic;
signal mulu_reg : std_logic_vector(63 downto 0);
signal FAsign : std_logic;
signal faktorA : std_logic_vector(31 downto 0);
signal faktorB : std_logic_vector(31 downto 0);
signal div_reg : std_logic_vector(63 downto 0);
signal div_quot : std_logic_vector(63 downto 0);
signal div_ovl : std_logic;
signal div_neg : std_logic;
signal div_bit : std_logic;
signal div_sub : std_logic_vector(32 downto 0);
signal div_over : std_logic_vector(32 downto 0);
signal nozero : std_logic;
signal div_qsign : std_logic;
signal divisor : std_logic_vector(63 downto 0);
signal divs : std_logic;
signal signedOP : std_logic;
signal OP1_sign : std_logic;
signal OP2_sign : std_logic;
signal OP2outext : std_logic_vector(15 downto 0);
signal in_offset : std_logic_vector(5 downto 0);
-- signal in_width : std_logic_vector(5 downto 0);
signal datareg : std_logic_vector(31 downto 0);
signal insert : std_logic_vector(31 downto 0);
-- signal bf_result : std_logic_vector(31 downto 0);
-- signal bf_offset : std_logic_vector(5 downto 0);
-- signal bf_width : std_logic_vector(5 downto 0);
-- signal bf_firstbit : std_logic_vector(5 downto 0);
signal bf_datareg : std_logic_vector(31 downto 0);
-- signal bf_out : std_logic_vector(31 downto 0);
signal result : std_logic_vector(39 downto 0);
signal result_tmp : std_logic_vector(39 downto 0);
signal sign : std_logic_vector(31 downto 0);
signal bf_set1 : std_logic_vector(39 downto 0);
signal inmux0 : std_logic_vector(39 downto 0);
signal inmux1 : std_logic_vector(39 downto 0);
signal inmux2 : std_logic_vector(39 downto 0);
signal inmux3 : std_logic_vector(31 downto 0);
signal copymux0 : std_logic_vector(39 downto 0);
signal copymux1 : std_logic_vector(39 downto 0);
signal copymux2 : std_logic_vector(39 downto 0);
signal copymux3 : std_logic_vector(31 downto 0);
signal bf_set2 : std_logic_vector(31 downto 0);
-- signal bf_set3 : std_logic_vector(31 downto 0);
signal shift : std_logic_vector(39 downto 0);
signal copy : std_logic_vector(39 downto 0);
-- signal offset : std_logic_vector(5 downto 0);
-- signal width : std_logic_vector(5 downto 0);
signal bf_firstbit : std_logic_vector(5 downto 0);
signal mux : std_logic_vector(3 downto 0);
signal bitnr : std_logic_vector(4 downto 0);
signal mask : std_logic_vector(31 downto 0);
signal bf_bset : std_logic;
signal bf_NFlag : std_logic;
signal bf_bchg : std_logic;
signal bf_ins : std_logic;
signal bf_exts : std_logic;
signal bf_fffo : std_logic;
signal bf_d32 : std_logic;
signal bf_s32 : std_logic;
signal index : std_logic_vector(4 downto 0);
-- signal i : integer range 0 to 31;
-- signal i : integer range 0 to 31;
-- signal i : std_logic_vector(5 downto 0);
BEGIN
-----------------------------------------------------------------------------
-- set OP1in
-----------------------------------------------------------------------------
PROCESS (OP2out, reg_QB, opcode, OP1out, OP1in, exe_datatype, addsub_q, execOPC, exec,
bcd_a, bcd_s, result_mulu, result_div, exe_condition, bf_shift,
Flags, FlagsSR, bits_out, exec_tas, rot_out, exe_opcode, result, bf_fffo, bf_firstbit, bf_datareg)
BEGIN
ALUout <= OP1in;
ALUout(7) <= OP1in(7) OR exec_tas;
IF exec(opcBFwb)='1' THEN
ALUout <= result(31 downto 0);
IF bf_fffo='1' THEN
ALUout <= (OTHERS =>'0');
ALUout(5 downto 0) <= bf_firstbit + bf_shift;
END IF;
END IF;
OP1in <= addsub_q;
IF exec(opcABCD)='1' THEN
OP1in(7 downto 0) <= bcd_a(7 downto 0);
ELSIF exec(opcSBCD)='1' THEN
OP1in(7 downto 0) <= bcd_s(7 downto 0);
ELSIF exec(opcMULU)='1' AND MUL_Mode/=3 THEN
IF exec(write_lowlong)='1' AND (MUL_Mode=1 OR MUL_Mode=2) THEN
OP1in <= result_mulu(31 downto 0);
ELSE
OP1in <= result_mulu(63 downto 32);
END IF;
ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
-- IF exe_opcode(15)='1' THEN
OP1in <= result_div(47 downto 32)&result_div(15 downto 0);
ELSE --64bit
IF exec(write_reminder)='1' THEN
OP1in <= result_div(63 downto 32);
ELSE
OP1in <= result_div(31 downto 0);
END IF;
END IF;
ELSIF exec(opcOR)='1' THEN
OP1in <= OP2out OR OP1out;
ELSIF exec(opcAND)='1' THEN
OP1in <= OP2out AND OP1out;
ELSIF exec(opcScc)='1' THEN
OP1in(7 downto 0) <= (others=>exe_condition);
ELSIF exec(opcEOR)='1' THEN
OP1in <= OP2out XOR OP1out;
ELSIF exec(opcMOVE)='1' OR exec(exg)='1' THEN
-- OP1in <= OP2out(31 downto 8)&(OP2out(7)OR exec_tas)&OP2out(6 downto 0);
OP1in <= OP2out;
ELSIF exec(opcROT)='1' THEN
OP1in <= rot_out;
ELSIF exec(opcSWAP)='1' THEN
OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
ELSIF exec(opcBITS)='1' THEN
OP1in <= bits_out;
ELSIF exec(opcBF)='1' THEN
OP1in <= bf_datareg;
ELSIF exec(opcMOVESR)='1' THEN
OP1in(7 downto 0) <= Flags;
IF exe_datatype="00" THEN
OP1in(15 downto 8) <= "00000000";
ELSE
OP1in(15 downto 8) <= FlagsSR;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- addsub
-----------------------------------------------------------------------------
PROCESS (OP1out, OP2out, execOPC, datatype, Flags, long_start, movem_presub, exe_datatype, exec, addsub_a, addsub_b, opaddsub,
notaddsub_b, add_result, c_in, sndOPC)
BEGIN
addsub_a <= OP1out;
IF exec(get_bfoffset)='1' THEN
IF sndOPC(11)='1' THEN
addsub_a <= OP1out(31)&OP1out(31)&OP1out(31)&OP1out(31 downto 3);
ELSE
addsub_a <= "000000000000000000000000000000"&sndOPC(10 downto 9);
END IF;
END IF;
IF exec(subidx)='1' THEN
opaddsub <= '1';
ELSE
opaddsub <= '0';
END IF;
c_in(0) <='0';
addsub_b <= OP2out;
IF execOPC='0' AND exec(OP2out_one)='0' AND exec(get_bfoffset)='0'THEN
IF long_start='0' AND datatype="00" AND exec(use_SP)='0' THEN
addsub_b <= "00000000000000000000000000000001";
ELSIF long_start='0' AND exe_datatype="10" AND (exec(presub) OR exec(postadd) OR movem_presub)='1' THEN
IF exec(movem_action)='1' THEN
addsub_b <= "00000000000000000000000000000110";
ELSE
addsub_b <= "00000000000000000000000000000100";
END IF;
ELSE
addsub_b <= "00000000000000000000000000000010";
END IF;
ELSE
IF (exec(use_XZFlag)='1' AND Flags(4)='1') OR exec(opcCHK)='1' THEN
c_in(0) <= '1';
END IF;
opaddsub <= exec(addsub);
END IF;
IF opaddsub='0' OR long_start='1' THEN --ADD
notaddsub_b <= '0'&addsub_b&c_in(0);
ELSE --SUB
notaddsub_b <= NOT ('0'&addsub_b&c_in(0));
END IF;
add_result <= (('0'&addsub_a&notaddsub_b(0))+notaddsub_b);
c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
c_in(3) <= add_result(33);
addsub_q <= add_result(32 downto 1);
addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7)); --V Byte
addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15)); --V Word
addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31)); --V Long
c_out <= c_in(3 downto 1);
END PROCESS;
------------------------------------------------------------------------------
--ALU
------------------------------------------------------------------------------
PROCESS (OP1out, OP2out, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, Flags)
BEGIN
--BCD_ARITH-------------------------------------------------------------------
--ADC
bcd_a <= niba_hc&(niba_h(4 downto 1)+('0',niba_hc,niba_hc,'0'))&(niba_l(4 downto 1)+('0',niba_lc,niba_lc,'0'));
niba_l <= ('0'&OP1out(3 downto 0)&'1') + ('0'&OP2out(3 downto 0)&Flags(4));
niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
niba_h <= ('0'&OP1out(7 downto 4)&'1') + ('0'&OP2out(7 downto 4)&niba_lc);
niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
--SBC
bcd_s <= nibs_hc&(nibs_h(4 downto 1)-('0',nibs_hc,nibs_hc,'0'))&(nibs_l(4 downto 1)-('0',nibs_lc,nibs_lc,'0'));
nibs_l <= ('0'&OP1out(3 downto 0)&'0') - ('0'&OP2out(3 downto 0)&Flags(4));
nibs_lc <= nibs_l(5);
nibs_h <= ('0'&OP1out(7 downto 4)&'0') - ('0'&OP2out(7 downto 4)&nibs_lc);
nibs_hc <= nibs_h(5);
END PROCESS;
-----------------------------------------------------------------------------
-- Bits
-----------------------------------------------------------------------------
PROCESS (clk, exe_opcode, OP1out, OP2out, one_bit_in, bchg, bset, bit_Number, sndOPC)
BEGIN
IF rising_edge(clk) THEN
IF clkena_lw = '1' THEN
bchg <= '0';
bset <= '0';
CASE opcode(7 downto 6) IS
WHEN "01" => --bchg
bchg <= '1';
WHEN "11" => --bset
bset <= '1';
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
IF exe_opcode(8)='0' THEN
IF exe_opcode(5 downto 4)="00" THEN
bit_number <= sndOPC(4 downto 0);
ELSE
bit_number <= "00"&sndOPC(2 downto 0);
END IF;
ELSE
IF exe_opcode(5 downto 4)="00" THEN
bit_number <= reg_QB(4 downto 0);
ELSE
bit_number <= "00"&reg_QB(2 downto 0);
END IF;
END IF;
one_bit_in <= OP1out(to_integer(unsigned(bit_Number)));
bits_out <= OP1out;
bits_out(to_integer(unsigned(bit_Number))) <= (bchg AND NOT one_bit_in) OR bset ;
END PROCESS;
-----------------------------------------------------------------------------
-- Bit Field
-----------------------------------------------------------------------------
PROCESS (clk, mux, mask, bitnr, bf_ins, bf_bchg, bf_bset, bf_exts, bf_shift, inmux0, inmux1, inmux2, inmux3, bf_set2, OP1out, OP2out, result_tmp, bf_ext_in,
shift, datareg, bf_NFlag, result, reg_QB, sign, bf_d32, bf_s32, copy, bf_loffset, copymux0, copymux1, copymux2, copymux3, bf_width)
BEGIN
IF rising_edge(clk) THEN
IF clkena_lw = '1' THEN
bf_bset <= '0';
bf_bchg <= '0';
bf_ins <= '0';
bf_exts <= '0';
bf_fffo <= '0';
bf_d32 <= '0';
bf_s32 <= '0';
CASE opcode(10 downto 8) IS
WHEN "010" => bf_bchg <= '1'; --BFCHG
WHEN "011" => bf_exts <= '1'; --BFEXTS
-- WHEN "100" => insert <= (OTHERS =>'0'); --BFCLR
WHEN "101" => bf_fffo <= '1'; --BFFFO
WHEN "110" => bf_bset <= '1'; --BFSET
WHEN "111" => bf_ins <= '1'; --BFINS
bf_s32 <= '1';
WHEN OTHERS => NULL;
END CASE;
IF opcode(4 downto 3)="00" THEN
bf_d32 <= '1';
END IF;
bf_ext_out <= result(39 downto 32);
END IF;
END IF;
shift <= bf_ext_in&OP2out;
IF bf_s32='1' THEN
shift(39 downto 32) <= OP2out(7 downto 0);
END IF;
IF bf_shift(0)='1' THEN
inmux0 <= shift(0)&shift(39 downto 1);
ELSE
inmux0 <= shift;
END IF;
IF bf_shift(1)='1' THEN
inmux1 <= inmux0(1 downto 0)&inmux0(39 downto 2);
ELSE
inmux1 <= inmux0;
END IF;
IF bf_shift(2)='1' THEN
inmux2 <= inmux1(3 downto 0)&inmux1(39 downto 4);
ELSE
inmux2 <= inmux1;
END IF;
IF bf_shift(3)='1' THEN
inmux3 <= inmux2(7 downto 0)&inmux2(31 downto 8);
ELSE
inmux3 <= inmux2(31 downto 0);
END IF;
IF bf_shift(4)='1' THEN
bf_set2(31 downto 0) <= inmux3(15 downto 0)&inmux3(31 downto 16);
ELSE
bf_set2(31 downto 0) <= inmux3;
END IF;
IF bf_loffset(4)='1' THEN
copymux3 <= sign(15 downto 0)&sign(31 downto 16);
ELSE
copymux3 <= sign;
END IF;
IF bf_loffset(3)='1' THEN
copymux2(31 downto 0) <= copymux3(23 downto 0)&copymux3(31 downto 24);
ELSE
copymux2(31 downto 0) <= copymux3;
END IF;
IF bf_d32='1' THEN
copymux2(39 downto 32) <= copymux3(7 downto 0);
ELSE
copymux2(39 downto 32) <= "11111111";
END IF;
IF bf_loffset(2)='1' THEN
copymux1 <= copymux2(35 downto 0)&copymux2(39 downto 36);
ELSE
copymux1 <= copymux2;
END IF;
IF bf_loffset(1)='1' THEN
copymux0 <= copymux1(37 downto 0)&copymux1(39 downto 38);
ELSE
copymux0 <= copymux1;
END IF;
IF bf_loffset(0)='1' THEN
copy <= copymux0(38 downto 0)&copymux0(39);
ELSE
copy <= copymux0;
END IF;
result_tmp <= bf_ext_in&OP1out;
IF bf_ins='1' THEN
datareg <= reg_QB;
ELSE
datareg <= bf_set2;
END IF;
IF bf_ins='1' THEN
result(31 downto 0) <= bf_set2;
result(39 downto 32) <= bf_set2(7 downto 0);
ELSIF bf_bchg='1' THEN
result(31 downto 0) <= NOT OP1out;
result(39 downto 32) <= NOT bf_ext_in;
ELSE
result <= (OTHERS => '0');
END IF;
IF bf_bset='1' THEN
result <= (OTHERS => '1');
END IF;
sign <= (OTHERS => '0');
bf_NFlag <= datareg(to_integer(unsigned(bf_width)));
FOR i in 0 to 31 LOOP
IF i>bf_width(4 downto 0) THEN
datareg(i) <= '0';
sign(i) <= '1';
END IF;
END LOOP;
FOR i in 0 to 39 LOOP
IF copy(i)='1' THEN
result(i) <= result_tmp(i);
END IF;
END LOOP;
IF bf_exts='1' AND bf_NFlag='1' THEN
bf_datareg <= datareg OR sign;
ELSE
bf_datareg <= datareg;
END IF;
-- bf_datareg <= copy(31 downto 0);
-- result(31 downto 0)<=datareg;
--BFFFO
mask <= datareg;
bf_firstbit <= '0'&bitnr;
bitnr <= "11111";
IF mask(31 downto 28)="0000" THEN
IF mask(27 downto 24)="0000" THEN
IF mask(23 downto 20)="0000" THEN
IF mask(19 downto 16)="0000" THEN
bitnr(4) <= '0';
IF mask(15 downto 12)="0000" THEN
IF mask(11 downto 8)="0000" THEN
bitnr(3) <= '0';
IF mask(7 downto 4)="0000" THEN
bitnr(2) <= '0';
mux <= mask(3 downto 0);
ELSE
mux <= mask(7 downto 4);
END IF;
ELSE
mux <= mask(11 downto 8);
bitnr(2) <= '0';
END IF;
ELSE
mux <= mask(15 downto 12);
END IF;
ELSE
mux <= mask(19 downto 16);
bitnr(3) <= '0';
bitnr(2) <= '0';
END IF;
ELSE
mux <= mask(23 downto 20);
bitnr(3) <= '0';
END IF;
ELSE
mux <= mask(27 downto 24);
bitnr(2) <= '0';
END IF;
ELSE
mux <= mask(31 downto 28);
END IF;
IF mux(3 downto 2)="00" THEN
bitnr(1) <= '0';
IF mux(1)='0' THEN
bitnr(0) <= '0';
END IF;
ELSE
IF mux(3)='0' THEN
bitnr(0) <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Rotation
-----------------------------------------------------------------------------
PROCESS (exe_opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, exec)
BEGIN
CASE exe_opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_rot <= OP1out(7);
WHEN "01"|"11" => --Word
rot_rot <= OP1out(15);
WHEN "10" => --Long
rot_rot <= OP1out(31);
WHEN OTHERS => NULL;
END CASE;
CASE rot_bits IS
WHEN "00" => --ASL, ASR
rot_lsb <= '0';
rot_msb <= rot_rot;
WHEN "01" => --LSL, LSR
rot_lsb <= '0';
rot_msb <= '0';
WHEN "10" => --ROXL, ROXR
rot_lsb <= Flags(4);
rot_msb <= Flags(4);
WHEN "11" => --ROL, ROR
rot_lsb <= rot_rot;
rot_msb <= OP1out(0);
WHEN OTHERS => NULL;
END CASE;
IF exec(rot_nop)='1' THEN
rot_out <= OP1out;
rot_X <= Flags(4);
IF rot_bits="10" THEN --ROXL, ROXR
rot_C <= Flags(4);
ELSE
rot_C <= '0';
END IF;
ELSE
IF exe_opcode(8)='1' THEN --left
rot_out <= OP1out(30 downto 0)&rot_lsb;
rot_X <= rot_rot;
rot_C <= rot_rot;
ELSE --right
rot_X <= OP1out(0);
rot_C <= OP1out(0);
rot_out <= rot_msb&OP1out(31 downto 1);
CASE exe_opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_out(7) <= rot_msb;
WHEN "01"|"11" => --Word
rot_out(15) <= rot_msb;
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
END PROCESS;
------------------------------------------------------------------------------
--CCR op
------------------------------------------------------------------------------
PROCESS (clk, Reset, exe_opcode, exe_datatype, Flags, last_data_read, OP2out, flag_z, OP1IN, c_out, addsub_ofl,
bcd_s, bcd_a, exec)
BEGIN
IF exec(andiSR)='1' THEN
CCRin <= Flags AND last_data_read(7 downto 0);
ELSIF exec(eoriSR)='1' THEN
CCRin <= Flags XOR last_data_read(7 downto 0);
ELSIF exec(oriSR)='1' THEN
CCRin <= Flags OR last_data_read(7 downto 0);
ELSE
CCRin <= OP2out(7 downto 0);
END IF;
------------------------------------------------------------------------------
--Flags
------------------------------------------------------------------------------
flag_z <= "000";
IF exec(use_XZFlag)='1' AND flags(2)='0' THEN
flag_z <= "000";
ELSIF OP1in(7 downto 0)="00000000" THEN
flag_z(0) <= '1';
IF OP1in(15 downto 8)="00000000" THEN
flag_z(1) <= '1';
IF OP1in(31 downto 16)="0000000000000000" THEN
flag_z(2) <= '1';
END IF;
END IF;
END IF;
-- --Flags NZVC
IF exe_datatype="00" THEN --Byte
set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
IF exec(opcABCD)='1' THEN
set_flags(0) <= bcd_a(8);
ELSIF exec(opcSBCD)='1' THEN
set_flags(0) <= bcd_s(8);
END IF;
ELSIF exe_datatype="10" OR exec(opcCPMAW)='1' THEN --Long
set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
ELSE --Word
set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
END IF;
IF rising_edge(clk) THEN
IF clkena_lw = '1' THEN
IF exec(directSR)='1' OR set_stop='1' THEN
Flags(7 downto 0) <= data_read(7 downto 0);
END IF;
IF exec(directCCR)='1' THEN
Flags(7 downto 0) <= data_read(7 downto 0);
END IF;
IF exec(opcROT)='1' THEN
asl_VFlag <= ((set_flags(3) XOR rot_rot) OR asl_VFlag);
ELSE
asl_VFlag <= '0';
END IF;
IF exec(to_CCR)='1' THEN
Flags(7 downto 0) <= CCRin(7 downto 0); --CCR
ELSIF Z_error='1' THEN
IF exe_opcode(8)='0' THEN
Flags(3 downto 0) <= reg_QA(31)&"000";
ELSE
Flags(3 downto 0) <= "0100";
END IF;
ELSIF exec(no_Flags)='0' THEN
IF exec(opcADD)='1' THEN
Flags(4) <= set_flags(0);
ELSIF exec(opcROT)='1' AND rot_bits/="11" AND exec(rot_nop)='0' THEN
Flags(4) <= rot_X;
END IF;
IF (exec(opcADD) OR exec(opcCMP))='1' THEN
Flags(3 downto 0) <= set_flags;
ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
IF V_Flag='1' THEN
Flags(3 downto 0) <= "1010";
ELSE
Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
END IF;
ELSIF exec(write_reminder)='1' AND MUL_Mode/=3 THEN -- z-flag MULU.l
Flags(3) <= set_flags(3);
Flags(2) <= set_flags(2) AND Flags(2);
Flags(1) <= '0';
Flags(0) <= '0';
ELSIF exec(write_lowlong)='1' AND (MUL_Mode=1 OR MUL_Mode=2) THEN -- flag MULU.l
Flags(3) <= set_flags(3);
Flags(2) <= set_flags(2);
Flags(1) <= set_mV_Flag; --V
Flags(0) <= '0';
ELSIF exec(opcOR)='1' OR exec(opcAND)='1' OR exec(opcEOR)='1' OR exec(opcMOVE)='1' OR exec(opcMOVEQ)='1' OR exec(opcSWAP)='1' OR exec(opcBF)='1' OR (exec(opcMULU)='1' AND MUL_Mode/=3) THEN
Flags(1 downto 0) <= "00";
Flags(3 downto 2) <= set_flags(3 downto 2);
IF exec(opcBF)='1' THEN
Flags(3) <= bf_NFlag;
END IF;
ELSIF exec(opcROT)='1' THEN
Flags(3 downto 2) <= set_flags(3 downto 2);
Flags(0) <= rot_C;
IF rot_bits="00" AND ((set_flags(3) XOR rot_rot) OR asl_VFlag)='1' THEN --ASL/ASR
Flags(1) <= '1';
ELSE
Flags(1) <= '0';
END IF;
ELSIF exec(opcBITS)='1' THEN
Flags(2) <= NOT one_bit_in;
ELSIF exec(opcCHK)='1' THEN
IF exe_datatype="01" THEN --Word
Flags(3) <= OP1out(15);
ELSE
Flags(3) <= OP1out(31);
END IF;
IF OP1out(15 downto 0)=X"0000" AND (exe_datatype="01" OR OP1out(31 downto 16)=X"0000") THEN
Flags(2) <='1';
ELSE
Flags(2) <='0';
END IF;
Flags(1 downto 0) <= "00";
END IF;
END IF;
END IF;
Flags(7 downto 5) <= "000";
END IF;
END PROCESS;
-------------------------------------------------------------------------------
---- MULU/MULS
-------------------------------------------------------------------------------
PROCESS (exe_opcode, OP2out, muls_msb, mulu_reg, FAsign, mulu_sign, reg_QA, faktorB, result_mulu, signedOP)
BEGIN
IF (signedOP='1' AND faktorB(31)='1') OR FAsign='1' THEN
muls_msb <= mulu_reg(63);
ELSE
muls_msb <= '0';
END IF;
IF signedOP='1' AND faktorB(31)='1' THEN
mulu_sign <= '1';
ELSE
mulu_sign <= '0';
END IF;
IF MUL_Mode=0 THEN -- 16 Bit
result_mulu(63 downto 32) <= muls_msb&mulu_reg(63 downto 33);
result_mulu(15 downto 0) <= 'X'&mulu_reg(15 downto 1);
IF mulu_reg(0)='1' THEN
IF FAsign='1' THEN
result_mulu(63 downto 47) <= (muls_msb&mulu_reg(63 downto 48)-(mulu_sign&faktorB(31 downto 16)));
ELSE
result_mulu(63 downto 47) <= (muls_msb&mulu_reg(63 downto 48)+(mulu_sign&faktorB(31 downto 16)));
END IF;
END IF;
ELSE -- 32 Bit
result_mulu <= muls_msb&mulu_reg(63 downto 1);
IF mulu_reg(0)='1' THEN
IF FAsign='1' THEN
result_mulu(63 downto 31) <= (muls_msb&mulu_reg(63 downto 32)-(mulu_sign&faktorB));
ELSE
result_mulu(63 downto 31) <= (muls_msb&mulu_reg(63 downto 32)+(mulu_sign&faktorB));
END IF;
END IF;
END IF;
IF exe_opcode(15)='1' OR MUL_Mode=0 THEN
faktorB(31 downto 16) <= OP2out(15 downto 0);
faktorB(15 downto 0) <= (OTHERS=>'0');
ELSE
faktorB <= OP2out;
END IF;
IF (result_mulu(63 downto 32)=X"00000000" AND (signedOP='0' OR result_mulu(31)='0')) OR
(result_mulu(63 downto 32)=X"FFFFFFFF" AND signedOP='1' AND result_mulu(31)='1') THEN
set_mV_Flag <= '0';
ELSE
set_mV_Flag <= '1';
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF clkena_lw='1' THEN
IF micro_state=mul1 THEN
mulu_reg(63 downto 32) <= (OTHERS=>'0');
IF divs='1' AND ((exe_opcode(15)='1' AND reg_QA(15)='1') OR (exe_opcode(15)='0' AND reg_QA(31)='1')) THEN --MULS Neg faktor
FAsign <= '1';
mulu_reg(31 downto 0) <= 0-reg_QA;
ELSE
FAsign <= '0';
mulu_reg(31 downto 0) <= reg_QA;
END IF;
ELSIF exec(opcMULU)='0' THEN
mulu_reg <= result_mulu;
END IF;
END IF;
END IF;
END PROCESS;
-------------------------------------------------------------------------------
---- DIVU/DIVS
-------------------------------------------------------------------------------
PROCESS (execOPC, OP1out, OP2out, div_reg, div_neg, div_bit, div_sub, div_quot, OP1_sign, div_over, result_div, reg_QA, opcode, sndOPC, divs, exe_opcode, reg_QB,
signedOP, nozero, div_qsign, OP2outext)
BEGIN
divs <= (opcode(15) AND opcode(8)) OR (NOT opcode(15) AND sndOPC(11));
divisor(15 downto 0) <= (OTHERS=> '0');
divisor(63 downto 32) <= (OTHERS=> divs AND reg_QA(31));
IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
divisor(47 downto 16) <= reg_QA;
ELSE
divisor(31 downto 0) <= reg_QA;
IF exe_opcode(14)='1' AND sndOPC(10)='1' THEN
divisor(63 downto 32) <= reg_QB;
END IF;
END IF;
IF signedOP='1' OR opcode(15)='0' THEN
OP2outext <= OP2out(31 downto 16);
ELSE
OP2outext <= (OTHERS=> '0');
END IF;
IF signedOP='1' AND OP2out(31) ='1' THEN
div_sub <= (div_reg(63 downto 31))+('1'&OP2out(31 downto 0));
ELSE
div_sub <= (div_reg(63 downto 31))-('0'&OP2outext(15 downto 0)&OP2out(15 downto 0));
END IF;
IF DIV_Mode=0 THEN
div_bit <= div_sub(16);
ELSE
div_bit <= div_sub(32);
END IF;
IF div_bit='1' THEN
div_quot(63 downto 32) <= div_reg(62 downto 31);
ELSE
div_quot(63 downto 32) <= div_sub(31 downto 0);
END IF;
div_quot(31 downto 0) <= div_reg(30 downto 0)&NOT div_bit;
IF ((nozero='1' AND signedOP='1' AND (OP2out(31) XOR OP1_sign XOR div_neg XOR div_qsign)='1' ) --Overflow DIVS
OR (signedOP='0' AND div_over(32)='0')) AND DIV_Mode/=3 THEN --Overflow DIVU
set_V_Flag <= '1';
ELSE
set_V_Flag <= '0';
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF clkena_lw='1' THEN
V_Flag <= set_V_Flag;
signedOP <= divs;
IF micro_state=div1 THEN
nozero <= '0';
IF divs='1' AND divisor(63)='1' THEN -- Neg divisor
OP1_sign <= '1';
div_reg <= 0-divisor;
ELSE
OP1_sign <= '0';
div_reg <= divisor;
END IF;
ELSE
div_reg <= div_quot;
nozero <= NOT div_bit OR nozero;
END IF;
IF micro_state=div2 THEN
div_qsign <= NOT div_bit;
div_neg <= signedOP AND (OP2out(31) XOR OP1_sign);
IF DIV_Mode=0 THEN
div_over(32 downto 16) <= ('0'&div_reg(47 downto 32))-('0'&OP2out(15 downto 0));
ELSE
div_over <= ('0'&div_reg(63 downto 32))-('0'&OP2out);
END IF;
END IF;
IF exec(write_reminder)='0' THEN
-- IF exec_DIVU='0' THEN
IF div_neg='1' THEN
result_div(31 downto 0) <= 0-div_quot(31 downto 0);
ELSE
result_div(31 downto 0) <= div_quot(31 downto 0);
END IF;
IF OP1_sign='1' THEN
result_div(63 downto 32) <= 0-div_quot(63 downto 32);
ELSE
result_div(63 downto 32) <= div_quot(63 downto 32);
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END;

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------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2013 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package TG68K_Pack is
type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_AnXn1, ld_AnXn2, st_dAn1, ld_AnXnbd1, ld_AnXnbd2, ld_AnXnbd3,
ld_229_1, ld_229_2, ld_229_3, ld_229_4, st_229_1, st_229_2, st_229_3, st_229_4,
st_AnXn1, st_AnXn2, bra1, bsr1, bsr2, nopnop, dbcc1, movem1, movem2, movem3,
andi, op_AxAy, cmpm, link1, link2, unlink1, unlink2, int1, int2, int3, int4, rte1, rte2, rte3, trap0, trap1, trap2, trap3,
trap4, trap5, trap6, movec1, movep1, movep2, movep3, movep4, movep5, rota1, bf1,
mul1, mul2, mul_end1, mul_end2, div1, div2, div3, div4, div_end1, div_end2);
constant opcMOVE : integer := 0; --
constant opcMOVEQ : integer := 1; --
constant opcMOVESR : integer := 2; --
constant opcADD : integer := 3; --
constant opcADDQ : integer := 4; --
constant opcOR : integer := 5; --
constant opcAND : integer := 6; --
constant opcEOR : integer := 7; --
constant opcCMP : integer := 8; --
constant opcROT : integer := 9; --
constant opcCPMAW : integer := 10;
constant opcEXT : integer := 11; --
constant opcABCD : integer := 12; --
constant opcSBCD : integer := 13; --
constant opcBITS : integer := 14; --
constant opcSWAP : integer := 15; --
constant opcScc : integer := 16; --
constant andiSR : integer := 17; --
constant eoriSR : integer := 18; --
constant oriSR : integer := 19; --
constant opcMULU : integer := 20; --
constant opcDIVU : integer := 21; --
constant dispouter : integer := 22; --
constant rot_nop : integer := 23; --
constant ld_rot_cnt : integer := 24; --
constant writePC_add : integer := 25; --
constant ea_data_OP1 : integer := 26; --
constant ea_data_OP2 : integer := 27; --
constant use_XZFlag : integer := 28; --
constant get_bfoffset : integer := 29; --
constant save_memaddr : integer := 30; --
constant opcCHK : integer := 31; --
constant movec_rd : integer := 32; --
constant movec_wr : integer := 33; --
constant Regwrena : integer := 34; --
constant update_FC : integer := 35; --
constant linksp : integer := 36; --
constant movepl : integer := 37; --
constant update_ld : integer := 38; --
constant OP1addr : integer := 39; --
constant write_reg : integer := 40; --
constant changeMode : integer := 41; --
constant ea_build : integer := 42; --
constant trap_chk : integer := 43; --
constant store_ea_data : integer := 44; --
constant addrlong : integer := 45; --
constant postadd : integer := 46; --
constant presub : integer := 47; --
constant subidx : integer := 48; --
constant no_Flags : integer := 49; --
constant use_SP : integer := 50; --
constant to_CCR : integer := 51; --
constant to_SR : integer := 52; --
constant OP2out_one : integer := 53; --
constant OP1out_zero : integer := 54; --
constant mem_addsub : integer := 55; --
constant addsub : integer := 56; --
constant directPC : integer := 57; --
constant direct_delta : integer := 58; --
constant directSR : integer := 59; --
constant directCCR : integer := 60; --
constant exg : integer := 61; --
constant get_ea_now : integer := 62; --
constant ea_to_pc : integer := 63; --
constant hold_dwr : integer := 64; --
constant to_USP : integer := 65; --
constant from_USP : integer := 66; --
constant write_lowlong : integer := 67; --
constant write_reminder : integer := 68; --
constant movem_action : integer := 69; --
constant briefext : integer := 70; --
constant get_2ndOPC : integer := 71; --
constant mem_byte : integer := 72; --
constant longaktion : integer := 73; --
constant opcRESET : integer := 74; --
constant opcBF : integer := 75; --
constant opcBFwb : integer := 76; --
constant s2nd_hbits : integer := 77; --
-- constant : integer := 75; --
-- constant : integer := 76; --
-- constant : integer := 7; --
-- constant : integer := 7; --
-- constant : integer := 7; --
constant lastOpcBit : integer := 77;
component TG68K_ALU
generic(
MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode : integer := 0 --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
);
port(
clk : in std_logic;
Reset : in std_logic;
clkena_lw : in std_logic:='1';
execOPC : in bit;
exe_condition : in std_logic;
exec_tas : in std_logic;
long_start : in bit;
movem_presub : in bit;
set_stop : in bit;
Z_error : in bit;
rot_bits : in std_logic_vector(1 downto 0);
exec : in bit_vector(lastOpcBit downto 0);
OP1out : in std_logic_vector(31 downto 0);
OP2out : in std_logic_vector(31 downto 0);
reg_QA : in std_logic_vector(31 downto 0);
reg_QB : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(15 downto 0);
datatype : in std_logic_vector(1 downto 0);
exe_opcode : in std_logic_vector(15 downto 0);
exe_datatype : in std_logic_vector(1 downto 0);
sndOPC : in std_logic_vector(15 downto 0);
last_data_read : in std_logic_vector(15 downto 0);
data_read : in std_logic_vector(15 downto 0);
FlagsSR : in std_logic_vector(7 downto 0);
micro_state : in micro_states;
bf_ext_in : in std_logic_vector(7 downto 0);
bf_ext_out : out std_logic_vector(7 downto 0);
bf_shift : in std_logic_vector(5 downto 0);
bf_width : in std_logic_vector(5 downto 0);
bf_loffset : in std_logic_vector(4 downto 0);
set_V_Flag : buffer bit;
Flags : buffer std_logic_vector(7 downto 0);
c_out : buffer std_logic_vector(2 downto 0);
addsub_q : buffer std_logic_vector(31 downto 0);
ALUout : out std_logic_vector(31 downto 0)
);
end component;
end;

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--
-- A simulation model of YM2149 (AY-3-8910 with bells on)
-- Copyright (c) MikeJ - Jan 2005
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email support@fpgaarcade.com
--
-- Revision list
--
-- version 001 initial release
--
-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
--
-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
-- vol 15 .. 0
-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
-- to produced all the required values.
-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
--
-- NOTE, this component uses a volume table for accurate mixing of the three analogue channels,
-- where the outputs are wired together - like in the Atari ST
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity YM2149 is
port (
-- data bus
I_DA : in std_logic_vector(7 downto 0);
O_DA : out std_logic_vector(7 downto 0);
O_DA_OE_L : out std_logic;
-- control
I_A9_L : in std_logic;
I_A8 : in std_logic;
I_BDIR : in std_logic;
I_BC2 : in std_logic;
I_BC1 : in std_logic;
I_SEL_L : in std_logic;
O_AUDIO : out std_logic_vector(7 downto 0);
-- port a
I_IOA : in std_logic_vector(7 downto 0);
O_IOA : out std_logic_vector(7 downto 0);
O_IOA_OE_L : out std_logic;
-- port b
I_IOB : in std_logic_vector(7 downto 0);
O_IOB : out std_logic_vector(7 downto 0);
O_IOB_OE_L : out std_logic;
--
ENA : in std_logic; -- clock enable for higher speed operation
RESET_L : in std_logic;
CLK : in std_logic -- note 6 Mhz
);
end;
architecture RTL of YM2149 is
component vol_table
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(9 downto 0)
);
end component;
-- signals
type array_16x8 is array (0 to 15) of std_logic_vector(7 downto 0);
type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0);
signal cnt_div : std_logic_vector(3 downto 0) := (others => '0');
signal noise_div : std_logic := '0';
signal ena_div : std_logic;
signal ena_div_noise : std_logic;
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
-- registers
signal addr : std_logic_vector(7 downto 0);
signal busctrl_addr : std_logic;
signal busctrl_we : std_logic;
signal busctrl_re : std_logic;
signal reg : array_16x8;
signal env_reset : std_logic;
signal ioa_inreg : std_logic_vector(7 downto 0);
signal iob_inreg : std_logic_vector(7 downto 0);
signal noise_gen_cnt : std_logic_vector(4 downto 0);
signal noise_gen_op : std_logic;
signal tone_gen_cnt : array_3x12 := (others => (others => '0'));
signal tone_gen_op : std_logic_vector(3 downto 1) := "000";
signal env_gen_cnt : std_logic_vector(15 downto 0);
signal env_ena : std_logic;
signal env_hold : std_logic;
signal env_inc : std_logic;
signal env_vol : std_logic_vector(4 downto 0);
signal vol_table_in : std_logic_vector(11 downto 0);
signal vol_table_out : std_logic_vector(9 downto 0);
begin
-- cpu i/f
p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
variable cs : std_logic;
variable sel : std_logic_vector(2 downto 0);
begin
-- BDIR BC2 BC1 MODE
-- 0 0 0 inactive
-- 0 0 1 address
-- 0 1 0 inactive
-- 0 1 1 read
-- 1 0 0 address
-- 1 0 1 inactive
-- 1 1 0 write
-- 1 1 1 read
busctrl_addr <= '0';
busctrl_we <= '0';
busctrl_re <= '0';
cs := '0';
if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
cs := '1';
end if;
sel := (I_BDIR & I_BC2 & I_BC1);
case sel is
when "000" => null;
when "001" => busctrl_addr <= '1';
when "010" => null;
when "011" => busctrl_re <= cs;
when "100" => busctrl_addr <= '1';
when "101" => null;
when "110" => busctrl_we <= cs;
when "111" => busctrl_addr <= '1';
when others => null;
end case;
end process;
p_oe : process(busctrl_re)
begin
-- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
O_DA_OE_L <= not (busctrl_re);
end process;
-- CLOCKED
--p_waddr : process
--begin
---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
--wait until rising_edge(CLK);
--if (RESET_L = '0') then
--addr <= (others => '0');
--else
--if (busctrl_addr = '1') then
--addr <= I_DA;
--end if;
--end if;
--end process;
--p_wdata : process
--begin
---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
--wait until rising_edge(CLK);
--env_reset <= '0';
--if (RESET_L = '0') then
--reg <= (others => (others => '0'));
--env_reset <= '1';
--else
--env_reset <= '0';
--if (busctrl_we = '1') then
--case addr(3 downto 0) is
--when x"0" => reg(0) <= I_DA;
--when x"1" => reg(1) <= I_DA;
--when x"2" => reg(2) <= I_DA;
--when x"3" => reg(3) <= I_DA;
--when x"4" => reg(4) <= I_DA;
--when x"5" => reg(5) <= I_DA;
--when x"6" => reg(6) <= I_DA;
--when x"7" => reg(7) <= I_DA;
--when x"8" => reg(8) <= I_DA;
--when x"9" => reg(9) <= I_DA;
--when x"A" => reg(10) <= I_DA;
--when x"B" => reg(11) <= I_DA;
--when x"C" => reg(12) <= I_DA;
--when x"D" => reg(13) <= I_DA; env_reset <= '1';
--when x"E" => reg(14) <= I_DA;
--when x"F" => reg(15) <= I_DA;
--when others => null;
--end case;
--end if;
--end if;
--end process;
-- LATCHED, useful when emulating a real chip in circuit. Nasty as gated clock.
p_waddr : process(reset_l, busctrl_addr)
begin
-- looks like registers are latches in real chip, but the address is caught at the end of the address state.
if (RESET_L = '0') then
addr <= (others => '0');
elsif falling_edge(busctrl_addr) then -- yuk
addr <= I_DA;
end if;
end process;
p_wdata : process(reset_l, busctrl_we, addr)
begin
if (RESET_L = '0') then
reg <= (others => (others => '0'));
elsif falling_edge(busctrl_we) then
case addr(3 downto 0) is
when x"0" => reg(0) <= I_DA;
when x"1" => reg(1) <= I_DA;
when x"2" => reg(2) <= I_DA;
when x"3" => reg(3) <= I_DA;
when x"4" => reg(4) <= I_DA;
when x"5" => reg(5) <= I_DA;
when x"6" => reg(6) <= I_DA;
when x"7" => reg(7) <= I_DA;
when x"8" => reg(8) <= I_DA;
when x"9" => reg(9) <= I_DA;
when x"A" => reg(10) <= I_DA;
when x"B" => reg(11) <= I_DA;
when x"C" => reg(12) <= I_DA;
when x"D" => reg(13) <= I_DA;
when x"E" => reg(14) <= I_DA;
when x"F" => reg(15) <= I_DA;
when others => null;
end case;
end if;
env_reset <= '0';
if (busctrl_we = '1') and (addr(3 downto 0) = x"D") then
env_reset <= '1';
end if;
end process;
p_rdata : process(busctrl_re, addr, reg)
begin
O_DA <= (others => '0'); -- 'X'
if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
case addr(3 downto 0) is
when x"0" => O_DA <= reg(0) ;
when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ;
when x"2" => O_DA <= reg(2) ;
when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ;
when x"4" => O_DA <= reg(4) ;
when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ;
when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ;
when x"7" => O_DA <= reg(7) ;
when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ;
when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ;
when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ;
when x"B" => O_DA <= reg(11);
when x"C" => O_DA <= reg(12);
when x"D" => O_DA <= "0000" & reg(13)(3 downto 0);
when x"E" => if (reg(7)(6) = '0') then -- input
O_DA <= ioa_inreg;
else
O_DA <= reg(14); -- read output reg
end if;
when x"F" => if (Reg(7)(7) = '0') then
O_DA <= iob_inreg;
else
O_DA <= reg(15);
end if;
when others => null;
end case;
end if;
end process;
--
p_divider : process
begin
wait until rising_edge(CLK);
-- / 8 when SEL is high and /16 when SEL is low
if (ENA = '1') then
ena_div <= '0';
ena_div_noise <= '0';
if (cnt_div = "0000") then
cnt_div <= (not I_SEL_L) & "111";
ena_div <= '1';
noise_div <= not noise_div;
if (noise_div = '1') then
ena_div_noise <= '1';
end if;
else
cnt_div <= cnt_div - "1";
end if;
end if;
end process;
p_noise_gen : process
variable noise_gen_comp : std_logic_vector(4 downto 0);
variable poly17_zero : std_logic;
begin
wait until rising_edge(CLK);
if (reg(6)(4 downto 0) = "00000") then
noise_gen_comp := "00000";
else
noise_gen_comp := (reg(6)(4 downto 0) - "1");
end if;
poly17_zero := '0';
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
if (ENA = '1') then
if (ena_div_noise = '1') then -- divider ena
if (noise_gen_cnt >= noise_gen_comp) then
noise_gen_cnt <= "00000";
poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
else
noise_gen_cnt <= (noise_gen_cnt + "1");
end if;
end if;
end if;
end process;
noise_gen_op <= poly17(0);
p_tone_gens : process
variable tone_gen_freq : array_3x12;
variable tone_gen_comp : array_3x12;
begin
wait until rising_edge(CLK);
-- looks like real chips count up - we need to get the Exact behaviour ..
tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
-- period 0 = period 1
for i in 1 to 3 loop
if (tone_gen_freq(i) = x"000") then
tone_gen_comp(i) := x"000";
else
tone_gen_comp(i) := (tone_gen_freq(i) - "1");
end if;
end loop;
if (ENA = '1') then
for i in 1 to 3 loop
if (ena_div = '1') then -- divider ena
if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
tone_gen_cnt(i) <= x"000";
tone_gen_op(i) <= not tone_gen_op(i);
else
tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
end if;
end if;
end loop;
end if;
end process;
p_envelope_freq : process
variable env_gen_freq : std_logic_vector(15 downto 0);
variable env_gen_comp : std_logic_vector(15 downto 0);
begin
wait until rising_edge(CLK);
env_gen_freq := reg(12) & reg(11);
-- envelope freqs 1 and 0 are the same.
if (env_gen_freq = x"0000") then
env_gen_comp := x"0000";
else
env_gen_comp := (env_gen_freq - "1");
end if;
if (ENA = '1') then
env_ena <= '0';
if (ena_div = '1') then -- divider ena
if (env_gen_cnt >= env_gen_comp) then
env_gen_cnt <= x"0000";
env_ena <= '1';
else
env_gen_cnt <= (env_gen_cnt + "1");
end if;
end if;
end if;
end process;
p_envelope_shape : process(env_reset, CLK)
variable is_bot : boolean;
variable is_bot_p1 : boolean;
variable is_top_m1 : boolean;
variable is_top : boolean;
begin
-- envelope shapes
-- C AtAlH
-- 0 0 x x \___
--
-- 0 1 x x /___
--
-- 1 0 0 0 \\\\
--
-- 1 0 0 1 \___
--
-- 1 0 1 0 \/\/
-- ___
-- 1 0 1 1 \
--
-- 1 1 0 0 ////
-- ___
-- 1 1 0 1 /
--
-- 1 1 1 0 /\/\
--
-- 1 1 1 1 /___
if (env_reset = '1') then
-- load initial state
if (reg(13)(2) = '0') then -- attack
env_vol <= "11111";
env_inc <= '0'; -- -1
else
env_vol <= "00000";
env_inc <= '1'; -- +1
end if;
env_hold <= '0';
elsif rising_edge(CLK) then
is_bot := (env_vol = "00000");
is_bot_p1 := (env_vol = "00001");
is_top_m1 := (env_vol = "11110");
is_top := (env_vol = "11111");
if (ENA = '1') then
if (env_ena = '1') then
if (env_hold = '0') then
if (env_inc = '1') then
env_vol <= (env_vol + "00001");
else
env_vol <= (env_vol + "11111");
end if;
end if;
-- envelope shape control.
if (reg(13)(3) = '0') then
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
else
if is_top then env_hold <= '1'; end if;
end if;
else
if (reg(13)(0) = '1') then -- hold = 1
if (env_inc = '0') then -- down
if (reg(13)(1) = '1') then -- alt
if is_bot then env_hold <= '1'; end if;
else
if is_bot_p1 then env_hold <= '1'; end if;
end if;
else
if (reg(13)(1) = '1') then -- alt
if is_top then env_hold <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
end if;
end if;
elsif (reg(13)(1) = '1') then -- alternate
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
if is_bot then env_hold <= '0'; env_inc <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
if is_top then env_hold <= '0'; env_inc <= '0'; end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
p_chan_mixer_table : process
variable chan_mixed : std_logic_vector(2 downto 0);
begin
wait until rising_edge(CLK);
if (ENA = '1') then
chan_mixed(0) := (reg(7)(0) or tone_gen_op(1)) and (reg(7)(3) or noise_gen_op);
chan_mixed(1) := (reg(7)(1) or tone_gen_op(2)) and (reg(7)(4) or noise_gen_op);
chan_mixed(2) := (reg(7)(2) or tone_gen_op(3)) and (reg(7)(5) or noise_gen_op);
vol_table_in <= x"000";
if (chan_mixed(0) = '1') then
if (reg(8)(4) = '0') then
vol_table_in(3 downto 0) <= reg(8)(3 downto 0);
else
vol_table_in(3 downto 0) <= env_vol(4 downto 1);
end if;
end if;
if (chan_mixed(1) = '1') then
if (reg(9)(4) = '0') then
vol_table_in(7 downto 4) <= reg(9)(3 downto 0);
else
vol_table_in(7 downto 4) <= env_vol(4 downto 1);
end if;
end if;
if (chan_mixed(2) = '1') then
if (reg(10)(4) = '0') then
vol_table_in(11 downto 8) <= reg(10)(3 downto 0);
else
vol_table_in(11 downto 8) <= env_vol(4 downto 1);
end if;
end if;
end if;
end process;
u_vol_table : vol_table
port map (
CLK => clk,
ADDR => vol_table_in,
DATA => vol_table_out
);
p_op_mixer : process
variable chan_mixed : std_logic;
variable chan_amp : std_logic_vector(4 downto 0);
begin
wait until rising_edge(CLK);
if (RESET_L = '0') then
O_AUDIO(7 downto 0) <= "00000000";
else
O_AUDIO(7 downto 0) <= vol_table_out(9 downto 2);
end if;
end process;
p_io_ports : process(reg)
begin
-- input low
O_IOA <= reg(14);
O_IOA_OE_L <= not reg(7)(6);
O_IOB <= reg(15);
O_IOB_OE_L <= not reg(7)(7);
end process;
p_io_ports_inreg : process
begin
wait until rising_edge(CLK);
ioa_inreg <= I_IOA;
iob_inreg <= I_IOB;
end process;
end architecture RTL;

130
cores/mist/acia.v Normal file
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module acia (
// cpu register interface
input clk,
input reset,
input [7:0] din,
input sel,
input [7:0] addr,
input ds,
input rw,
output reg [7:0] dout,
output dtack,
output irq,
// data from io controller to acia
input ikbd_strobe_in,
input [7:0] ikbd_data_in,
// data from acia to io controller
output ikbd_data_out_available,
input ikbd_strobe_out,
output [7:0] ikbd_data_out
);
localparam FIFO_ADDR_BITS = 4;
localparam FIFO_DEPTH = (1 << FIFO_ADDR_BITS);
reg [7:0] fifoIn [FIFO_DEPTH-1:0];
reg [FIFO_ADDR_BITS-1:0] writePin, readPin;
//
reg [7:0] fifoOut [FIFO_DEPTH-1:0];
reg [FIFO_ADDR_BITS-1:0] writePout, readPout;
// timer to let bytes arrive at a reasonable speed
reg [13:0] readTimer;
reg ikbd_strobe_inD, ikbd_strobe_inD2;
reg data_read;
always @(negedge clk) begin
if(reset)
readTimer <= 14'd0;
else
if(readTimer > 0)
readTimer <= readTimer - 14'd1;
ikbd_strobe_inD <= ikbd_strobe_in;
ikbd_strobe_inD2 <= ikbd_strobe_inD;
// read on kbd data register
if(sel && ~ds && rw && (addr == 8'h02))
data_read <= 1'b1;
else
data_read <= 1'b0;
if(reset) begin
// reset read and write counters
readPin <= 4'd0;
writePin <= 4'd0;
end else if(ikbd_strobe_inD && !ikbd_strobe_inD2) begin
// store data in fifo
fifoIn[writePin] <= ikbd_data_in;
writePin <= writePin + 4'd1;
end else if(data_read && dataInAvail) begin
readPin <= readPin + 4'd1;
// Some programs (e.g. bolo) need a pause between two ikbd bytes.
// The ikbd runs at 7812.5 bit/s 1 start + 8 data + 1 stop bit.
// One bit is 1/718.25 seconds. A pause of ~1ms is thus required
// 8000000/718.25 = 11138.18
readTimer <= 14'd11138;
end
end
// ------------------ cpu interface --------------------
wire [7:0] rxd;
assign rxd = fifoIn[readPin];
wire dataInAvail;
assign dataInAvail = (readPin != writePin) && (readTimer == 0);
assign irq = dataInAvail;
assign ikbd_data_out_available = (readPout != writePout);
assign ikbd_data_out = fifoOut[readPout];
// ---------------- send acia data to io controller ------------
reg ikbd_strobe_outD, ikbd_strobe_outD2;
always @(posedge clk) begin
ikbd_strobe_outD <= ikbd_strobe_out;
ikbd_strobe_outD2 <= ikbd_strobe_outD;
if(reset)
readPout <= 4'd0;
else
if(ikbd_strobe_outD && !ikbd_strobe_outD2)
readPout <= readPout + 4'd1;
end
// dtack
assign dtack = sel;
always @(sel, ds, rw, addr, dataInAvail, rxd) begin
if(sel && ~ds && rw) begin
// keyboard acia read
if(addr == 8'h00) dout = 8'h02 | (dataInAvail?8'h81:8'h00); // status
else if(addr == 8'h02) dout = rxd; // data
// midi acia read
else if(addr == 8'h04) dout = 8'h02; // status
else if(addr == 8'h06) dout = 8'h00; // data
else dout = 8'h00;
end else
dout = 8'h00;
end
always @(negedge clk) begin
if(reset) begin
writePout <= 0;
end else begin
// keyboard acia data register writes into buffer
if(sel && ~ds && ~rw && addr == 8'h02) begin
fifoOut[writePout] <= din;
writePout <= writePout + 4'd1;
end
end
end
endmodule

13
cores/mist/clock.ppf Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="clock" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="areset" direction="input" scope="external" />
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="c2" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>

5
cores/mist/clock.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "12.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clock.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clock_bb.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clock.ppf"]

404
cores/mist/clock.v Normal file
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// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clock.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clock (
areset,
inclk0,
c0,
c1,
c2,
c3,
locked);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output c3;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire3;
wire [0:0] sub_wire8 = 1'h0;
wire [2:2] sub_wire5 = sub_wire0[2:2];
wire [0:0] sub_wire4 = sub_wire0[0:0];
wire [3:3] sub_wire2 = sub_wire0[3:3];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c3 = sub_wire2;
wire locked = sub_wire3;
wire c0 = sub_wire4;
wire c2 = sub_wire5;
wire sub_wire6 = inclk0;
wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire7),
.clk (sub_wire0),
.locked (sub_wire3),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 18,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 85,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 72,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 85,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 18,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 85,
altpll_component.clk2_phase_shift = "-2000",
altpll_component.clk3_divide_by = 27000000,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 2457599,
altpll_component.clk3_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clock",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "18"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "72"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "18"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "127.500000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "31.875000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "127.500000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "2.457600"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "85"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "85"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "85"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "32.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "2.45760000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-2000.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "amigaclk.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "18"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "85"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "72"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "85"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "18"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "85"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2000"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "27000000"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2457599"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

254
cores/mist/clock_bb.v Normal file
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@@ -0,0 +1,254 @@
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clock.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module clock (
areset,
inclk0,
c0,
c1,
c2,
locked);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "18"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "72"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "18"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "127.500000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "31.875000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "127.500000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "85"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "85"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "85"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "32.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-2500.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "amigaclk.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "18"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "85"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "72"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "85"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "18"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "85"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2500"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

158
cores/mist/data_io.v Normal file
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// SPI data client (rom, floppy, harddisk io)
module data_io (
// clocks
input clk_8,
input reset,
input [1:0] bus_cycle,
output reg [15:0] ctrl_out,
// spi interface
input sdi,
input sck,
input ss,
output sdo,
// dma interface
output [4:0] dma_idx,
input [7:0] dma_data,
output reg dma_ack,
// ram interface
output reg [2:0] state, // state bits required to drive the sdram host
output [22:0] addr,
output reg [15:0] data_out, // write data register
input [15:0] data_in,
input ack
);
assign dma_idx = bcnt;
reg [4:0] cnt; // bit counter (counting spi bits, rolling from 23 to 8)
reg [4:0] bcnt; // payload byte counter
reg [14:0] sbuf; // receive buffer (buffer used to assemble spi bytes/words)
reg [7:0] cmd; // command byte (first byte of spi transmission)
reg [30:0] addrR;// address register (word address for memory transfers)
reg write; // write request received via SPI
reg writeD; // write synchonized to 8Mhz clock
reg writeD2; // synchronized write delayed by one 8Mhz clock
reg read; // read request received via SPI
reg readD; // read synchonized to 8Mhz clock
reg readD2; // synchronized read delayed by one 8Mhz clock
// during write the address needs to be decremented by one as the
// address auto increment takes place at the beginning of each transfer
assign addr = addrR[22:0] - ((cmd == 2)?23'b1:23'b0);
// generate state signals required to control the sdram host interface
always @(posedge clk_8) begin
// start io transfers after! bus_cycle 3 and 0 (after the video cycle)
writeD <= write && ((bus_cycle == 3) || writeD);
writeD2 <= writeD;
readD <= read && ((bus_cycle == 3) || readD);
readD2 <= readD;
if(reset)
state <= 3'b101;
else begin
if(writeD && ~writeD2)
state <= 3'b011; // write data
else if(readD && ~readD2)
state <= 3'b010; // read data
else
state <= 3'b001; // decode (idle)
end
end
reg [15:0] txData;
assign sdo = txData[15];
always@(negedge sck) begin
// memory read
if(cmd == 3) begin
if(cnt == 8)
txData <= data_in;
else
txData[15:1] <= txData[14:0];
end
// dma status read
if(cmd == 5) begin
if((cnt == 8) || (cnt == 16))
txData[15:8] <= dma_data;
else
txData[15:1] <= txData[14:0];
end
end
always@(posedge sck, posedge ss) begin
if(ss == 1'b1) begin
cnt <= 5'd0;
bcnt <= 4'd0;
write <= 1'b0;
read <= 1'b0;
dma_ack <= 1'b0;
end else begin
dma_ack <= 1'b0;
sbuf <= { sbuf[13:0], sdi};
// 0:7 is command, 8:15 and 16:23 is payload bytes
if(cnt < 5'd23)
cnt <= cnt + 5'd1;
else
cnt <= 5'd8;
// count payload bytes
if((cnt == 15) || (cnt == 23))
bcnt <= bcnt + 4'd1;
if(cnt == 5'd7) begin
cmd <= {sbuf[6:0], sdi};
// send ack
if({sbuf[6:0], sdi } == 8'd6)
dma_ack <= 1'b1;
// if we can see a read coming initiate sdram read transfer asap
if({sbuf[6:0], sdi } == 8'd3)
read <= 1;
end
// handle "payload"
if(cnt >= 8) begin
// set address
if(cmd == 1)
addrR <= { addrR[29:0], sdi};
// write ram
if(cmd == 2) begin
if(cnt == 5'd16)
write <= 1'b0;
if(cnt == 5'd23) begin
data_out <= { sbuf, sdi };
addrR <= addrR + 31'b1;
write <= 1'b1;
end
end
// read ram
if(cmd == 3) begin
if(cnt == 16)
read <= 0;
if(cnt == 23) begin
addrR <= addrR + 31'b1;
read <= 1;
end
end
// set control register
if((cmd == 4) && (cnt == 5'd23))
ctrl_out <= { sbuf, sdi };
end
end
end
endmodule

241
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module dma (
// cpu register interface
input clk,
input reset,
input [15:0] din,
input sel,
input [7:0] addr,
input uds,
input lds,
input rw,
output reg [15:0] dout,
output dtack,
// output to mfp
output irq,
// input from system config
input fdc_wr_prot,
// connection to data_io (arm controller spi interface)
input [4:0] dio_idx,
output reg [7:0] dio_data,
input dio_ack,
// input from psg
input drv_side,
input [1:0] drv_sel
);
// ------------- data_io (arm controller) interface ------
always @(dio_idx, base, scnt, fdc_cmd, fdc_track, fdc_sector,
fdc_data, drv_sel, drv_side, fdc_busy) begin
dio_data = 8'h00;
case (dio_idx)
0: dio_data = base[23:16];
1: dio_data = base[15:8];
2: dio_data = base[7:0];
3: dio_data = scnt;
4: dio_data = fdc_cmd;
5: dio_data = fdc_track;
6: dio_data = fdc_sector;
7: dio_data = fdc_data;
8: dio_data = { 4'b0000, drv_sel, drv_side, fdc_busy };
default: dio_data = 8'h00;
endcase
end
// ------------------ cpu interface --------------------
reg fdc_busy;
assign irq = !fdc_busy;
reg [15:0] mode;
// fdc registers
reg [7:0] fdc_cmd;
reg [7:0] fdc_track;
reg [7:0] fdc_sector;
reg [7:0] fdc_data;
// dma base address register and sector counter
reg [23:0] base;
reg [7:0] scnt;
// dtack
assign dtack = sel;
// virtual head is over track 0
wire track0;
assign track0 = (fdc_track == 8'd0);
reg step_dir;
// status byte returned by the fdc when reading register 0
wire [7:0] fdc_status;
assign fdc_status = {
!(motor_on == 0), fdc_wr_prot, 3'b000,
(fdc_cmd[7]==1'b0)?track0:1'b0, 1'b0, fdc_busy };
wire [15:0] dma_status;
assign dma_status = { 14'd0, !(scnt == 0), 1'b1 }; // bit 0 = 1: DMA_OK
// timer to simulate motor-on
reg [15:0] motor_on;
always @(sel, rw, addr, mode, base, fdc_data, fdc_sector, fdc_status, fdc_track,
dma_status, scnt) begin
dout = 16'h0000;
if(sel && rw) begin
if((addr == 8'h04) && (mode[4] == 1'b0)) begin
// controller access register
if(mode[3] == 1'b0) begin
// fdc
if(mode[2:1] == 2'b00) // status register
dout = { 8'h00, fdc_status };
if(mode[2:1] == 2'b01) // track register
dout = { 8'h00, fdc_track };
if(mode[2:1] == 2'b10) // sector register
dout = { 8'h00, fdc_sector };
if(mode[2:1] == 2'b11) // data register
dout = { 8'h00, fdc_data };
end
end
if(addr == 8'h06)
dout = dma_status;
// sector count register
if((addr == 8'h04) && (mode[4] == 1'b1))
dout = { 8'h00, scnt };
// dma base address read back
if(addr == 8'h09)
dout = { 8'h00, base[23:16] };
if(addr == 8'h0b)
dout = { 8'h00, base[15:8] };
if(addr == 8'h0d)
dout = { 8'h00, base[7:0] };
end
end
reg dio_ackD, dio_ackD2;
always @(posedge clk)
dio_ackD <= dio_ack;
always @(negedge clk) begin
if(reset) begin
mode <= 16'd0;
fdc_cmd <= 8'd0;
fdc_track <= 8'd0;
fdc_sector <= 8'd0;
fdc_data <= 8'd0;
base <= 24'h000000;
scnt <= 8'h00;
fdc_busy <= 1'b0;
motor_on <= 16'd0;
end else begin
// rising edge on ack -> clear busy flag
dio_ackD2 <= dio_ackD;
if(dio_ackD && !dio_ackD2) begin
scnt <= 8'h00; // all sectors transmitted
fdc_busy <= 1'b0;
end
// let "motor" run for some time
if(motor_on != 0)
motor_on <= motor_on - 16'd1;
// dma control and mode register
if(sel && ~rw) begin
if(~lds && (addr == 8'h04) && (mode[4] == 1'b0)) begin
// controller access register
if(mode[3] == 1'b0) begin
// fdc register write
if(mode[2:1] == 2'b00) begin // command register
fdc_cmd <= din[7:0];
// all TYPE I and TYPE II commands start the motor
if((din[7] == 1'b0) || (din[7:6] == 2'b10))
motor_on <= 16'hffff;
// ------------- TYPE I commands -------------
if(din[7:4] == 4'b0000) // RESTORE
fdc_track <= 8'd0;
if(din[7:4] == 4'b0001) // SEEK
fdc_track <= fdc_data;
if(din[7:4] == 4'b0011) begin // STEP with update flag
if(step_dir == 1'b1)
fdc_track <= fdc_track + 8'd1;
else
fdc_track <= fdc_track - 8'd1;
end
if(din[7:4] == 4'b0101) begin // STEP-IN with update flag
step_dir <= 1'b1;
fdc_track <= fdc_track + 8'd1;
end
if(din[7:4] == 4'b0111) begin // STEP-OUT with update flag
step_dir <= 1'b0;
fdc_track <= fdc_track - 8'd1;
end
// ------------- TYPE II commands -------------
if(din[7:5] == 3'b100) // read sector
fdc_busy <= 1'b1;
if(din[7:5] == 3'b101) // write sector
if(!fdc_wr_prot)
fdc_busy <= 1'b1;
// ------------- TYPE III commands ------------
// these aren't supported yet
// if(din[7:4] == 4'b1100) // read address
// fdc_busy <= 1'b1;
// if(din[7:4] == 4'b1110) // read track
// fdc_busy <= 1'b1;
// if(din[7:4] == 4'b1111) // write track
// if(!fdc_wr_prot)
// fdc_busy <= 1'b1;
// ------------- TYPE IV commands -------------
if(din[7:4] == 4'b1101) // force intrerupt
fdc_busy <= 1'b0;
end if(mode[2:1] == 2'b01) // track register
fdc_track <= din[7:0];
if(mode[2:1] == 2'b10) // sector register
fdc_sector <= din[7:0];
if(mode[2:1] == 2'b11) // data register
fdc_data <= din[7:0];
end
end
// sector count register
if(~lds && (addr == 8'h04) && (mode[4] == 1'b1))
scnt <= din[7:0];
if(addr == 8'h06)
mode <= din;
if(~lds && (addr == 8'h09))
base[23:16] <= din[7:0];
if(~lds && (addr == 8'h0b))
base[15:8] <= din[7:0];
if(~lds && (addr == 8'h0d))
base[7:0] <= din[7:0];
end
end
end
endmodule

343
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//
module mfp (
// cpu register interface
input clk,
input reset,
input [7:0] din,
input sel,
input [7:0] addr,
input ds,
input rw,
output reg [7:0] dout,
output dtack,
output irq,
input iack,
// serial rs232 connection to io controller
output serial_data_out_available,
input serial_strobe_out,
output [7:0] serial_data_out,
input clk_ext, // external 2.457MHz
input de,
input dma_irq,
input acia_irq,
input mono_detect
);
localparam FIFO_ADDR_BITS = 4;
localparam FIFO_DEPTH = (1 << FIFO_ADDR_BITS);
//
reg [7:0] fifoOut [FIFO_DEPTH-1:0];
reg [FIFO_ADDR_BITS-1:0] writePout, readPout;
assign serial_data_out_available = (readPout != writePout);
assign serial_data_out = fifoOut[readPout];
// signal "fifo is full" via uart config bit
wire serial_data_out_fifo_full = (readPout === (writePout + 4'd1));
// ---------------- send mfp uart data to io controller ------------
reg serial_strobe_outD, serial_strobe_outD2;
always @(posedge clk) begin
serial_strobe_outD <= serial_strobe_out;
serial_strobe_outD2 <= serial_strobe_outD;
if(reset)
readPout <= 4'd0;
else
if(serial_strobe_outD && !serial_strobe_outD2)
readPout <= readPout + 4'd1;
end
// timer to let bytes arrive at a reasonable speed
reg [13:0] readTimer;
wire write = sel && ~ds && ~rw;
wire timera_done;
wire [7:0] timera_dat_o;
wire [4:0] timera_ctrl_o;
mfp_timer timer_a (
.CLK (clk),
.XCLK_I (clk_ext),
.RST (reset),
.CTRL_I (din[4:0]),
.CTRL_O (timera_ctrl_o),
.CTRL_WE ((addr == 8'h19) && write),
.DAT_I (din),
.DAT_O (timera_dat_o),
.DAT_WE ((addr == 8'h1f) && write),
.T_O_PULSE (timera_done)
);
wire timerb_done;
wire [7:0] timerb_dat_o;
wire [4:0] timerb_ctrl_o;
mfp_timer timer_b (
.CLK (clk),
.XCLK_I (clk_ext),
.RST (reset),
.CTRL_I (din[4:0]),
.CTRL_O (timerb_ctrl_o),
.CTRL_WE ((addr == 8'h1b) && write),
.DAT_I (din),
.DAT_O (timerb_dat_o),
.DAT_WE ((addr == 8'h21) && write),
.T_I (de),
.T_O_PULSE (timerb_done)
);
wire timerc_done;
wire [7:0] timerc_dat_o;
wire [4:0] timerc_ctrl_o;
mfp_timer timer_c (
.CLK (clk),
.XCLK_I (clk_ext),
.RST (reset),
.CTRL_I ({2'b00, din[6:4]}),
.CTRL_O (timerc_ctrl_o),
.CTRL_WE ((addr == 8'h1d) && write),
.DAT_I (din),
.DAT_O (timerc_dat_o),
.DAT_WE ((addr == 8'h23) && write),
.T_O_PULSE (timerc_done)
);
wire timerd_done;
wire [7:0] timerd_dat_o;
wire [4:0] timerd_ctrl_o;
mfp_timer timer_d (
.CLK (clk),
.XCLK_I (clk_ext),
.RST (reset),
.CTRL_I ({2'b00, din[2:0]}),
.CTRL_O (timerd_ctrl_o),
.CTRL_WE ((addr == 8'h1d) && write),
.DAT_I (din),
.DAT_O (timerd_dat_o),
.DAT_WE ((addr == 8'h25) && write),
.T_O_PULSE (timerd_done)
);
// dtack
assign dtack = sel || iack;
reg [7:0] aer, ddr, gpip;
// the mfp can handle 16 irqs, 8 internal and 8 external
reg [15:0] ipr, ier, imr, isr; // interrupt registers
reg [7:0] vr;
// any pending and not masked interrupt causes the irq line to go high
// if highest_irq_pending != higest_irq_active then there's a high prio
// irq in service and no irq is generated until this one is finished
assign irq = ((ipr & imr) != 16'h0000) && (highest_irq_active == highest_irq_pending);
// handle pending and in service irqs
wire [15:0] irq_active_map;
assign irq_active_map = (ipr | isr) & imr;
// (i am pretty sure this can be done much more elegant ...)
// check the number of the highest active irq
wire [3:0] highest_irq_active;
assign highest_irq_active=
( irq_active_map[15] == 1'b1)?4'd15:
((irq_active_map[15:14] == 2'b01)?4'd14:
((irq_active_map[15:13] == 3'b001)?4'd13:
((irq_active_map[15:12] == 4'b0001)?4'd12:
((irq_active_map[15:11] == 5'b00001)?4'd11:
((irq_active_map[15:10] == 6'b000001)?4'd10:
((irq_active_map[15:9] == 7'b0000001)?4'd9:
((irq_active_map[15:8] == 8'b00000001)?4'd8:
((irq_active_map[15:7] == 9'b000000001)?4'd7:
((irq_active_map[15:6] == 10'b000000001)?4'd6:
((irq_active_map[15:5] == 11'b0000000001)?4'd5:
((irq_active_map[15:4] == 12'b00000000001)?4'd4:
((irq_active_map[15:3] == 13'b000000000001)?4'd3:
((irq_active_map[15:2] == 14'b0000000000001)?4'd2:
((irq_active_map[15:1] == 15'b00000000000001)?4'd1:
((irq_active_map[15:0] == 16'b000000000000001)?4'd0:
4'd0)))))))))))))));
wire [15:0] irq_pending_map;
assign irq_pending_map = ipr & imr;
// check the number of the highest pending irq
wire [3:0] highest_irq_pending;
assign highest_irq_pending =
( irq_pending_map[15] == 1'b1)?4'd15:
((irq_pending_map[15:14] == 2'b01)?4'd14:
((irq_pending_map[15:13] == 3'b001)?4'd13:
((irq_pending_map[15:12] == 4'b0001)?4'd12:
((irq_pending_map[15:11] == 5'b00001)?4'd11:
((irq_pending_map[15:10] == 6'b000001)?4'd10:
((irq_pending_map[15:9] == 7'b0000001)?4'd9:
((irq_pending_map[15:8] == 8'b00000001)?4'd8:
((irq_pending_map[15:7] == 9'b000000001)?4'd7:
((irq_pending_map[15:6] == 10'b000000001)?4'd6:
((irq_pending_map[15:5] == 11'b0000000001)?4'd5:
((irq_pending_map[15:4] == 12'b00000000001)?4'd4:
((irq_pending_map[15:3] == 13'b000000000001)?4'd3:
((irq_pending_map[15:2] == 14'b0000000000001)?4'd2:
((irq_pending_map[15:1] == 15'b00000000000001)?4'd1:
((irq_pending_map[15:0] == 16'b000000000000001)?4'd0:
4'd0)))))))))))))));
// wire inputs to external gpip in
// acia/dma irq is active low in st, but active high in this config, we thus invert
// it to make sure tos sees what it expects to see when it looks at the registers
wire [7:0] gpip_in;
assign gpip_in = { mono_detect, 1'b0, !dma_irq, !acia_irq, 4'b0000 };
// gpip as output to the cpu
wire [7:0] gpip_cpu_out;
assign gpip_cpu_out = (gpip_in & ~ddr) | (gpip & ddr);
// cpu read interface
always @(iack, sel, ds, rw, addr, gpip_cpu_out, aer, ddr, ier, ipr, isr, imr,
vr, irq_vec) begin
dout = 8'd0;
if(sel && ~ds && rw) begin
if(addr == 8'h01) dout = gpip_cpu_out;
if(addr == 8'h03) dout = aer;
if(addr == 8'h05) dout = ddr;
if(addr == 8'h07) dout = ier[15:8];
if(addr == 8'h0b) dout = ipr[15:8];
if(addr == 8'h0f) dout = isr[15:8];
if(addr == 8'h13) dout = imr[15:8];
if(addr == 8'h09) dout = ier[7:0];
if(addr == 8'h0d) dout = ipr[7:0];
if(addr == 8'h11) dout = isr[7:0];
if(addr == 8'h15) dout = imr[7:0];
if(addr == 8'h17) dout = vr;
// timers
if(addr == 8'h19) dout = { 3'b000, timera_ctrl_o};
if(addr == 8'h1b) dout = { 3'b000, timerb_ctrl_o};
if(addr == 8'h1d) dout = { timerc_ctrl_o[3:0], timerd_ctrl_o[3:0]};
if(addr == 8'h1f) dout = timera_dat_o;
if(addr == 8'h21) dout = timerb_dat_o;
if(addr == 8'h23) dout = timerc_dat_o;
if(addr == 8'h25) dout = timerd_dat_o;
// uart: report "tx buffer empty" if fifo is not full
if(addr == 8'h2d) dout = serial_data_out_fifo_full?8'h00:8'h80;
end else if(iack) begin
dout = irq_vec;
end
end
// delay de and timer to detect changes
reg acia_irqD, acia_irqD2, dma_irqD, dma_irqD2;
reg [7:0] irq_vec;
always @(posedge clk) begin
acia_irqD <= acia_irq;
dma_irqD <= dma_irq;
iackD <= iack;
// the pending irq changes in the middle of an iack
// phase, so we latch the current vector to keep is stable
// during the entire cpu read
irq_vec <= { vr[7:4], highest_irq_pending };
end
reg iackD;
always @(negedge clk) begin
dma_irqD2 <= dma_irqD;
acia_irqD2 <= acia_irqD;
if(reset) begin
ipr <= 16'h0000; ier <= 16'h0000;
imr <= 16'h0000; isr <= 16'h0000;
writePout <= 0;
end else begin
// ack pending irqs and set isr if enabled
if(iackD) begin
// remove active bit from ipr
ipr[highest_irq_pending] <= 1'b0;
// move bit into isr if s-bit in vr is set
if(vr[3])
isr[highest_irq_pending] <= 1'b1;
end
// map timer interrupts
if(timera_done && ier[13]) ipr[13] <= 1'b1; // timer_a
if(timerb_done && ier[ 8]) ipr[ 8] <= 1'b1; // timer_b
if(timerc_done && ier[ 5]) ipr[ 5] <= 1'b1; // timer_c
if(timerd_done && ier[ 4]) ipr[ 4] <= 1'b1; // timer_d
// irq by acia ...
if(acia_irqD && !acia_irqD2) begin
if(ier[6]) ipr[6] <= 1'b1;
end
// ... and dma
if(dma_irqD && !dma_irqD2) begin
if(ier[7]) ipr[7] <= 1'b1;
end
if(sel && ~ds && ~rw) begin
if(addr == 8'h01)
gpip <= din;
if(addr == 8'h03)
aer <= din;
if(addr == 8'h05)
ddr <= din;
if(addr == 8'h07) begin
ier[15:8] <= din;
ipr[15:8]<= ipr[15:8] & din; // clear pending interrupts
end
if(addr == 8'h0b)
ipr[15:8] <= ipr[15:8] & din;
if(addr == 8'h0f)
isr[15:8] <= isr[15:8] & din; // zero bits are cleared
if(addr == 8'h13)
imr[15:8] <= din;
if(addr == 8'h09) begin
ier[7:0] <= din;
ipr[7:0] <= ipr[7:0] & din; // clear pending interrupts
end
if(addr == 8'h0d)
ipr[7:0] <= ipr[7:0] & din;
if(addr == 8'h11)
isr[7:0] <= isr[7:0] & din; // zero bits are cleared
if(addr == 8'h15)
imr[7:0] <= din;
if(addr == 8'h17)
vr <= din;
if(addr == 8'h2f) begin
fifoOut[writePout] <= din;
writePout <= writePout + 4'd1;
end
end
end
end
endmodule

139
cores/mist/mfp_timer.v Normal file
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module mfp_timer(
input CLK,
input RST,
input DAT_WE,
input [7:0] DAT_I,
output [7:0] DAT_O,
input CTRL_WE,
input [4:0] CTRL_I,
output [4:0] CTRL_O,
inout XCLK_I,
input T_I, // ext. trigger in
output reg T_O,
output reg T_O_PULSE
);
reg [7:0] data, down_counter, cur_counter;
reg [3:0] control;
wire[7:0] prescaler; // prescaler value
reg [7:0] prescaler_counter; // prescaler counter
reg count;
wire started;
wire delay_mode;
wire event_mode;
wire pulse_mode;
// trigger edge detect registers
reg trigger_r, trigger_r2;
// async clock edge detect
reg xclk_r, xclk_r2;
// counters work on the negative clock edge. we latch them
// on the positive edge for stable cpu read
always @(posedge CLK)
cur_counter <= down_counter;
// generate clock from async clock input
always @(posedge XCLK_I) begin
if(RST === 1'b1)
prescaler_counter <= 8'd0;
else begin
if(prescaler_counter >= prescaler)
prescaler_counter <= 8'd0;
else
prescaler_counter <= prescaler_counter + 8'd1;
end
end
always @(negedge CLK) begin
if (RST === 1'b1) begin
T_O_PULSE <= 1'b0;
T_O <= 1'b0;
control <= 4'd0;
data <= 8'd0;
down_counter <= 8'd0;
count <= 1'b0;
end else begin
// bring trigger/xclk edges into our clock domain.
trigger_r <= T_I;
trigger_r2 <= trigger_r;
xclk_r <= (prescaler_counter === 8'd0);
xclk_r2 <= xclk_r;
T_O_PULSE <= 1'b0;
// if a write request comes from the main unit
// then write the data to the appropriate register.
if(DAT_WE) begin
data <= DAT_I;
down_counter <= DAT_I;
end
if(CTRL_WE) begin
control <= CTRL_I[3:0];
if (CTRL_I[4] == 1'b1)
T_O <= 1'b0;
end
if (started) begin
count <= 1'b0;
// handle event mode
if (event_mode === 1'b1)
if ((~trigger_r2 & trigger_r) === 1'b1)
count <= 1'b1;
// handle delay mode
if (delay_mode === 1'b1)
if ((~xclk_r2 & xclk_r) === 1'b1)
count <= 1'b1;
if (count) begin
// timeout pulse
if (down_counter === 8'd1) begin
// pulse the timer out
T_O <= ~T_O;
down_counter <= data;
T_O_PULSE <= 1'b1;
end else begin
down_counter <= down_counter - 8'd1;
end
end
end
end
end
assign prescaler = control[2:0] === 3'd1 ? 8'd04 :
control[2:0] === 3'd2 ? 8'd10 :
control[2:0] === 3'd3 ? 8'd16 :
control[2:0] === 3'd4 ? 8'd50 :
control[2:0] === 3'd5 ? 8'd64 :
control[2:0] === 3'd6 ? 8'd100 :
control[2:0] === 3'd7 ? 8'd200 : 8'd1;
assign delay_mode = control[3] === 1'b0;
assign pulse_mode = control[3] === 1'b1 & !event_mode;
assign event_mode = control[3:0] === 4'b1000;
assign started = control[3:0] != 4'd0;
assign DAT_O = cur_counter;
assign CTRL_O = {T_O, control};
endmodule // mfp_timer

62
cores/mist/mist.jdi Normal file
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@@ -0,0 +1,62 @@
<sld_project_info>
<project>
<hash md5_digest_80b="f8d5b5a7688270eb3596"/>
</project>
<file_info/>
<hub_info ir_width="8" node_count="1"/>
<node_info>
<node hpath="sld_signaltap:auto_signaltap_0" instance_id="0" mfg_id="110" node_id="0" sld_node_info="0x30006E00" version="6">
<parameters>
<parameter name="lpm_type" type="string" value="sld_signaltap"/>
<parameter name="sld_node_info" type="unknown" value="805334528"/>
<parameter name="SLD_IP_VERSION" type="dec" value="6"/>
<parameter name="SLD_IP_MINOR_VERSION" type="dec" value="0"/>
<parameter name="SLD_COMMON_IP_VERSION" type="dec" value="0"/>
<parameter name="sld_data_bits" type="unknown" value="175"/>
<parameter name="sld_trigger_bits" type="unknown" value="175"/>
<parameter name="SLD_NODE_CRC_BITS" type="dec" value="32"/>
<parameter name="sld_node_crc_hiword" type="unknown" value="22929"/>
<parameter name="sld_node_crc_loword" type="unknown" value="471"/>
<parameter name="SLD_INCREMENTAL_ROUTING" type="dec" value="0"/>
<parameter name="sld_sample_depth" type="unknown" value="1024"/>
<parameter name="sld_segment_size" type="unknown" value="1024"/>
<parameter name="SLD_RAM_BLOCK_TYPE" type="string" value="AUTO"/>
<parameter name="sld_state_bits" type="unknown" value="11"/>
<parameter name="sld_buffer_full_stop" type="unknown" value="1"/>
<parameter name="SLD_MEM_ADDRESS_BITS" type="dec" value="7"/>
<parameter name="SLD_DATA_BIT_CNTR_BITS" type="dec" value="4"/>
<parameter name="sld_trigger_level" type="unknown" value="1"/>
<parameter name="sld_trigger_in_enabled" type="unknown" value="0"/>
<parameter name="sld_advanced_trigger_entity" type="unknown" value="basic,1,"/>
<parameter name="sld_trigger_level_pipeline" type="unknown" value="1"/>
<parameter name="sld_enable_advanced_trigger" type="unknown" value="0"/>
<parameter name="SLD_ADVANCED_TRIGGER_1" type="string" value="NONE"/>
<parameter name="SLD_ADVANCED_TRIGGER_2" type="string" value="NONE"/>
<parameter name="SLD_ADVANCED_TRIGGER_3" type="string" value="NONE"/>
<parameter name="SLD_ADVANCED_TRIGGER_4" type="string" value="NONE"/>
<parameter name="SLD_ADVANCED_TRIGGER_5" type="string" value="NONE"/>
<parameter name="SLD_ADVANCED_TRIGGER_6" type="string" value="NONE"/>
<parameter name="SLD_ADVANCED_TRIGGER_7" type="string" value="NONE"/>
<parameter name="SLD_ADVANCED_TRIGGER_8" type="string" value="NONE"/>
<parameter name="SLD_ADVANCED_TRIGGER_9" type="string" value="NONE"/>
<parameter name="SLD_ADVANCED_TRIGGER_10" type="string" value="NONE"/>
<parameter name="sld_inversion_mask_length" type="unknown" value="549"/>
<parameter name="sld_inversion_mask" type="unknown" value="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
<parameter name="sld_power_up_trigger" type="unknown" value="0"/>
<parameter name="SLD_STATE_FLOW_MGR_ENTITY" type="string" value="state_flow_mgr_entity.vhd"/>
<parameter name="sld_state_flow_use_generated" type="unknown" value="0"/>
<parameter name="sld_current_resource_width" type="unknown" value="1"/>
<parameter name="sld_attribute_mem_mode" type="unknown" value="OFF"/>
<parameter name="SLD_STORAGE_QUALIFIER_BITS" type="dec" value="1"/>
<parameter name="SLD_STORAGE_QUALIFIER_GAP_RECORD" type="dec" value="0"/>
<parameter name="SLD_STORAGE_QUALIFIER_MODE" type="string" value="OFF"/>
<parameter name="SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION" type="dec" value="0"/>
<parameter name="sld_storage_qualifier_inversion_mask_length" type="unknown" value="0"/>
<parameter name="SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY" type="string" value="basic"/>
<parameter name="SLD_STORAGE_QUALIFIER_PIPELINE" type="dec" value="0"/>
</parameters>
<inputs/>
<outputs/>
</node>
</node_info>
</sld_project_info>

23
cores/mist/mist.qpf Normal file
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@@ -0,0 +1,23 @@
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
QUARTUS_VERSION = "7.2"
DATE = "22:27:29 October 30, 2007"
# Revisions
PROJECT_REVISION = "mist"

700
cores/mist/mist.qsf Normal file
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@@ -0,0 +1,700 @@
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name TOP_LEVEL_ENTITY mist_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:27:29 OCTOBER 30, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 12.1
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_22 -to CLOCK_50[0]
set_location_assignment PIN_23 -to CLOCK_50[1]
set_location_assignment PIN_128 -to CLOCK_32[0]
set_location_assignment PIN_129 -to CLOCK_32[1]
set_location_assignment PIN_54 -to CLOCK_27[0]
set_location_assignment PIN_55 -to CLOCK_27[1]
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_46 -to UART_TX
set_location_assignment PIN_31 -to UART_RX
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_90 -to SPI_SS4
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_global_assignment -name FMAX_REQUIREMENT "114 MHz"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name TPD_REQUIREMENT "2 ns"
set_global_assignment -name TSU_REQUIREMENT "2 ns"
set_global_assignment -name TCO_REQUIREMENT "2 ns"
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION OFF
set_global_assignment -name AUTO_RAM_RECOGNITION ON
set_global_assignment -name AUTO_ROM_RECOGNITION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_8
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_128
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SDRAM_CLK
set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=1024" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=1024" -section_id auto_signaltap_0
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SPI_SCK
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_32
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "clock:clock|altpll:altpll_component|clk[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "TG68K:tg68k|IPL[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "TG68K:tg68k|IPL[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "TG68K:tg68k|IPL[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|state[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|state[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "TG68K:tg68k|IPL[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "TG68K:tg68k|IPL[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "TG68K:tg68k|IPL[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|TG68_PC[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|data_write[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|exe_opcode[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|state[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|state[1]" -section_id auto_signaltap_0
set_global_assignment -name VERILOG_FILE mfp_timer.v
set_global_assignment -name VHDL_FILE vol_table_array.vhd
set_global_assignment -name VHDL_FILE YM2149_volmix.vhd
set_global_assignment -name VERILOG_FILE acia.v
set_global_assignment -name VHDL_FILE TG68K.vhd
set_global_assignment -name VHDL_FILE TG68K_ALU.vhd
set_global_assignment -name VHDL_FILE TG68K_Pack.vhd
set_global_assignment -name VHDL_FILE TG68KdotC_Kernel.vhd
set_global_assignment -name SDC_FILE mist.sdc
set_global_assignment -name VHDL_FILE sdram.vhd
set_global_assignment -name VERILOG_FILE clock.v
set_global_assignment -name VERILOG_FILE mist_top.v
set_global_assignment -name VERILOG_FILE user_io.v
set_global_assignment -name VERILOG_FILE video.v
set_global_assignment -name VERILOG_FILE data_io.v
set_global_assignment -name VERILOG_FILE mfp.v
set_global_assignment -name VERILOG_FILE dma.v
set_global_assignment -name VERILOG_FILE sigma_delta_dac.v
set_global_assignment -name VERILOG_FILE mmu.v
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|trap_vector[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|trap_vector[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|trap_vector[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|trap_vector[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|trap_vector[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|trap_vector[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|trap_vector[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|trap_vector[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|trap_vector[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "TG68K:tg68k|addr[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "TG68K:tg68k|addr[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "TG68K:tg68k|addr[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "TG68K:tg68k|addr[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "TG68K:tg68k|addr[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "TG68K:tg68k|addr[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "TG68K:tg68k|addr[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "TG68K:tg68k|addr[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "TG68K:tg68k|addr[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "TG68K:tg68k|addr[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "TG68K:tg68k|addr[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "TG68K:tg68k|addr[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "TG68K:tg68k|addr[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "TG68K:tg68k|addr[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "TG68K:tg68k|addr[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "TG68K:tg68k|addr[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "TG68K:tg68k|addr[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "TG68K:tg68k|addr[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "TG68K:tg68k|addr[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "TG68K:tg68k|addr[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "TG68K:tg68k|addr[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "TG68K:tg68k|addr[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "TG68K:tg68k|addr[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "TG68K:tg68k|addr[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "TG68K:tg68k|addr[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "TG68K:tg68k|addr[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "TG68K:tg68k|addr[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "TG68K:tg68k|addr[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "TG68K:tg68k|addr[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "TG68K:tg68k|addr[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "TG68K:tg68k|addr[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "TG68K:tg68k|addr[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "TG68K:tg68k|as" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "TG68K:tg68k|data_read[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "TG68K:tg68k|data_read[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "TG68K:tg68k|data_read[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "TG68K:tg68k|data_read[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "TG68K:tg68k|data_read[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "TG68K:tg68k|data_read[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "TG68K:tg68k|data_read[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "TG68K:tg68k|data_read[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "TG68K:tg68k|data_read[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "TG68K:tg68k|data_read[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "TG68K:tg68k|data_read[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "TG68K:tg68k|data_read[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "TG68K:tg68k|data_read[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "TG68K:tg68k|data_read[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "TG68K:tg68k|data_read[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "TG68K:tg68k|data_read[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "TG68K:tg68k|dtack" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "TG68K:tg68k|lds" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "TG68K:tg68k|rw" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "TG68K:tg68k|uds" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to VGA_HS -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to "data_io:data_io|bus_cycle[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "data_io:data_io|bus_cycle[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to "mfp:mfp|clk" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to "mfp:mfp|dtack" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to "mfp:mfp|ipr[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[136] -to "mfp:mfp|ipr[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[137] -to "mfp:mfp|ipr[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[138] -to "mfp:mfp|ipr[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[139] -to "mfp:mfp|ipr[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[140] -to "mfp:mfp|ipr[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[141] -to "mfp:mfp|ipr[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[142] -to "mfp:mfp|ipr[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[143] -to "mfp:mfp|ipr[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[144] -to "mfp:mfp|ipr[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[145] -to "mfp:mfp|ipr[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[146] -to "mfp:mfp|ipr[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[147] -to "mfp:mfp|ipr[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[148] -to "mfp:mfp|ipr[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[149] -to "mfp:mfp|ipr[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[150] -to "mfp:mfp|ipr[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[151] -to "mfp:mfp|isr[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[152] -to "mfp:mfp|isr[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[153] -to "mfp:mfp|isr[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[154] -to "mfp:mfp|isr[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[155] -to "mfp:mfp|isr[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[156] -to "mfp:mfp|isr[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[157] -to "mfp:mfp|isr[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[158] -to "mfp:mfp|isr[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[159] -to "mfp:mfp|isr[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[160] -to "mfp:mfp|isr[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[161] -to "mfp:mfp|isr[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[162] -to "mfp:mfp|isr[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[163] -to "mfp:mfp|isr[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[164] -to "mfp:mfp|isr[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[165] -to "mfp:mfp|isr[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[166] -to "mfp:mfp|isr[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[167] -to "mfp:mfp|sel" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[168] -to "mmu:mmu|reset" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[169] -to "sdram:sdram|chipCycle" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[170] -to tg68_berr -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[171] -to "TG68K:tg68k|berr_in" -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[172] -to hsD -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[173] -to hsD2 -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[174] -to hsI -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|trap_vector[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|trap_vector[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|trap_vector[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|trap_vector[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|trap_vector[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|trap_vector[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "TG68K:tg68k|TG68KdotC_Kernel:pf68K_Kernel_inst|trap_vector[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "TG68K:tg68k|addr[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "TG68K:tg68k|addr[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "TG68K:tg68k|addr[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "TG68K:tg68k|addr[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "TG68K:tg68k|addr[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "TG68K:tg68k|addr[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "TG68K:tg68k|addr[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "TG68K:tg68k|addr[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "TG68K:tg68k|addr[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "TG68K:tg68k|addr[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "TG68K:tg68k|addr[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "TG68K:tg68k|addr[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "TG68K:tg68k|addr[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "TG68K:tg68k|addr[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "TG68K:tg68k|addr[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "TG68K:tg68k|addr[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "TG68K:tg68k|addr[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "TG68K:tg68k|addr[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "TG68K:tg68k|addr[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "TG68K:tg68k|addr[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "TG68K:tg68k|addr[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "TG68K:tg68k|addr[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "TG68K:tg68k|addr[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "TG68K:tg68k|addr[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "TG68K:tg68k|addr[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "TG68K:tg68k|addr[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "TG68K:tg68k|addr[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "TG68K:tg68k|addr[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "TG68K:tg68k|addr[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "TG68K:tg68k|addr[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "TG68K:tg68k|addr[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "TG68K:tg68k|addr[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "TG68K:tg68k|as" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "TG68K:tg68k|data_read[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "TG68K:tg68k|data_read[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "TG68K:tg68k|data_read[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "TG68K:tg68k|data_read[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "TG68K:tg68k|data_read[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "TG68K:tg68k|data_read[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "TG68K:tg68k|data_read[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "TG68K:tg68k|data_read[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "TG68K:tg68k|data_read[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "TG68K:tg68k|data_read[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "TG68K:tg68k|data_read[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "TG68K:tg68k|data_read[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "TG68K:tg68k|data_read[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "TG68K:tg68k|data_read[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "TG68K:tg68k|data_read[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "TG68K:tg68k|data_read[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "TG68K:tg68k|dtack" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "TG68K:tg68k|lds" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "TG68K:tg68k|rw" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "TG68K:tg68k|uds" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to VGA_HS -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "data_io:data_io|bus_cycle[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "data_io:data_io|bus_cycle[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "mfp:mfp|clk" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "mfp:mfp|dtack" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "mfp:mfp|ipr[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "mfp:mfp|ipr[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "mfp:mfp|ipr[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "mfp:mfp|ipr[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "mfp:mfp|ipr[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "mfp:mfp|ipr[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "mfp:mfp|ipr[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "mfp:mfp|ipr[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "mfp:mfp|ipr[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "mfp:mfp|ipr[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "mfp:mfp|ipr[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "mfp:mfp|ipr[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "mfp:mfp|ipr[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[148] -to "mfp:mfp|ipr[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[149] -to "mfp:mfp|ipr[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[150] -to "mfp:mfp|ipr[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[151] -to "mfp:mfp|isr[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[152] -to "mfp:mfp|isr[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[153] -to "mfp:mfp|isr[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[154] -to "mfp:mfp|isr[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[155] -to "mfp:mfp|isr[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[156] -to "mfp:mfp|isr[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[157] -to "mfp:mfp|isr[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[158] -to "mfp:mfp|isr[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[159] -to "mfp:mfp|isr[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[160] -to "mfp:mfp|isr[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[161] -to "mfp:mfp|isr[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[162] -to "mfp:mfp|isr[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[163] -to "mfp:mfp|isr[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[164] -to "mfp:mfp|isr[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[165] -to "mfp:mfp|isr[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[166] -to "mfp:mfp|isr[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[167] -to "mfp:mfp|sel" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[168] -to "mmu:mmu|reset" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[169] -to "sdram:sdram|chipCycle" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[170] -to tg68_berr -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[171] -to "TG68K:tg68k|berr_in" -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[172] -to hsD -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[173] -to hsD2 -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[174] -to hsI -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=175" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=175" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=549" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=471" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=22929" -section_id auto_signaltap_0
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
cores/mist/mist.qws Normal file
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108
cores/mist/mist.sdc Normal file
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## Generated SDC file "constraints.sdc"
## Copyright (C) 1991-2011 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition"
## DATE "Fri Jul 06 23:05:47 2012"
##
## DEVICE "EP3C25E144C8"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {clk_27} -period 37.037 -waveform { 0.000 18.500 } [get_ports {CLOCK_27[0]}]
#**************************************************************
# Create Generated Clock
#**************************************************************
derive_pll_clocks
create_generated_clock -name sdclk_pin -source [get_pins {clock|altpll_component|auto_generated|pll1|clk[2]}] [get_ports {SDRAM_CLK}]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty;
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -clock sdclk_pin -max 6.4 [get_ports SDRAM_DQ*]
set_input_delay -clock sdclk_pin -min 3.2 [get_ports SDRAM_DQ*]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -clock sdclk_pin -max 1.5 [get_ports SDRAM_*]
set_output_delay -clock sdclk_pin -min -0.8 [get_ports SDRAM_*]
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -from [get_clocks {sdclk_pin}] -to [get_clocks {clock|altpll_component|auto_generated|pll1|clk[2]}] -setup -end 2
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

711
cores/mist/mist_top.v Normal file
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/********************************************/
/* */
/********************************************/
module mist_top (
// clock inputs
input wire [ 2-1:0] CLOCK_32, // 32 MHz
input wire [ 2-1:0] CLOCK_27, // 27 MHz
input wire [ 2-1:0] CLOCK_50, // 50 MHz
// LED outputs
output wire LED, // LED Yellow
// UART
output wire UART_TX, // UART Transmitter
input wire UART_RX, // UART Receiver
// VGA
output wire VGA_HS, // VGA H_SYNC
output wire VGA_VS, // VGA V_SYNC
output wire [ 6-1:0] VGA_R, // VGA Red[5:0]
output wire [ 6-1:0] VGA_G, // VGA Green[5:0]
output wire [ 6-1:0] VGA_B, // VGA Blue[5:0]
// SDRAM
inout wire [ 16-1:0] SDRAM_DQ, // SDRAM Data bus 16 Bits
output wire [ 13-1:0] SDRAM_A, // SDRAM Address bus 13 Bits
output wire SDRAM_DQML, // SDRAM Low-byte Data Mask
output wire SDRAM_DQMH, // SDRAM High-byte Data Mask
output wire SDRAM_nWE, // SDRAM Write Enable
output wire SDRAM_nCAS, // SDRAM Column Address Strobe
output wire SDRAM_nRAS, // SDRAM Row Address Strobe
output wire SDRAM_nCS, // SDRAM Chip Select
output wire [ 2-1:0] SDRAM_BA, // SDRAM Bank Address
output wire SDRAM_CLK, // SDRAM Clock
output wire SDRAM_CKE, // SDRAM Clock Enable
// MINIMIG specific
output wire AUDIO_L, // sigma-delta DAC output left
output wire AUDIO_R, // sigma-delta DAC output right
// SPI
inout wire SPI_DO, // inout
input wire SPI_DI,
input wire SPI_SCK,
input wire SPI_SS2, // fpga
input wire SPI_SS3, // OSD
input wire SPI_SS4, // "sniff" mode
input wire CONF_DATA0 // SPI_SS for user_io
);
wire [15:0] video_data;
wire video_read;
wire [22:0] video_address;
wire video_de, video_hs;
// on-board io
wire [1:0] buttons;
// TODO: Clean this up as all dtacks are directly generated from their sel's
wire io_dtack;
assign io_dtack =
vreg_sel?vreg_dtack:
(mmu_sel?mmu_dtack:
((mfp_sel||mfp_iack)?mfp_dtack:
(acia_sel?acia_dtack:
(psg_sel?psg_dtack:
(dma_sel?dma_dtack:
(auto_iack?auto_iack:
1'b0))))));
// the original tg68k did not contain working support for bus fault exceptions. While earlier
// TOS versions cope with that, TOS versions with blitter support need this to work as this is
// required to properly detect that a blitter is not present.
// a bus error is now generated once no dtack is seen for 63 clock cycles. The tg68k requires
// a dtack to be generated with the bus error to continue operation
wire tg68_berr = (dtack_timeout == 6'd63); // || cpu_write_illegal;
wire cpu_write = cpu_cycle && cpu2io && data_strobe && !tg68_rw;
// it's illegal to write to certain memory areas
// TODO: Still the write itself would succeed. That must not happen
wire cpu_write_illegal = cpu_write &&
(tg68_adr[23:3] === 21'd0); // the first two long words $0 and $4
reg [5:0] dtack_timeout;
always @(posedge clk_8) begin
if(reset) begin
dtack_timeout <= 6'd0;
end else begin
if(!tg68_dtack)
dtack_timeout <= 6'd0;
else if(dtack_timeout != 6'd63)
dtack_timeout <= dtack_timeout + 6'd1;
end
end
// request interrupt ack from mfp for IPL == 6
wire mfp_iack;
assign mfp_iack = cpu_cycle && cpu2iack && data_strobe && (tg68_adr[3:1] == 3'b110);
// the tg68k core with the wrapper of the minimig doesn't support non-autovector
// interrupts. Also the existing support for them inside the tg68 kernel is/was broken.
// For the atari i've fixed the non-autovector support inside the kernel and switched
// entirely to non-autovector interrupts. This means that i now have to provide
// the vectors for those interrupts that oin the ST are autovector ones. This needs
// to be done for IPL2 (hbi) and IPL4 (vbi)
wire auto_iack;
assign auto_iack = cpu_cycle && cpu2iack && data_strobe &&
((tg68_adr[3:1] == 3'b100) || (tg68_adr[3:1] == 3'b010));
wire [7:0] auto_vector;
assign auto_vector = (tg68_adr[3:1] == 3'b100)?8'h1c:8'h1a;
// mmu cpu interface at $ff8001
wire mmu_sel;
wire mmu_dtack;
wire [7:0] mmu_data_out;
assign mmu_sel = cpu_cycle && cpu2io && data_strobe && ({tg68_adr[15:1], 1'b0} == 16'h8000);
// video controller cpu interface at $ff8200
wire vreg_sel;
wire vreg_dtack;
wire [15:0] vreg_data_out;
assign vreg_sel = cpu_cycle && cpu2io && data_strobe && (tg68_adr[15:8] == 8'h82);
// mfp cpu interface at $fffa00 - $fffa3f
wire mfp_sel;
wire mfp_dtack;
wire [7:0] mfp_data_out;
assign mfp_sel = cpu_cycle && cpu2io && data_strobe && (tg68_adr[15:8] == 8'hfa) &&
(tg68_adr[7:6] == 2'b00);
// acia cpu interface at $fffc00
wire acia_sel;
wire acia_dtack;
wire [7:0] acia_data_out;
assign acia_sel = cpu_cycle && cpu2io && data_strobe && (tg68_adr[15:8] == 8'hfc);
// psg interface at $ff8800
wire psg_sel;
wire psg_dtack;
wire [7:0] psg_data_out;
assign psg_sel = cpu_cycle && cpu2io && data_strobe && (tg68_adr[15:8] == 8'h88);
// dma interface at $ff8600
wire dma_sel;
wire dma_dtack;
wire [15:0] dma_data_out;
assign dma_sel = cpu_cycle && cpu2io && data_strobe && (tg68_adr[15:8] == 8'h86);
// de-multiplex the various io data output ports into one
wire [15:0] io_data_out;
assign io_data_out =
vreg_sel?vreg_data_out:
(mmu_sel?{8'h00, mmu_data_out}:
((mfp_sel||mfp_iack)?{8'h00, mfp_data_out}:
(auto_iack?{8'h00, auto_vector}:
(acia_sel?{acia_data_out, 8'h00}:
(psg_sel?{psg_data_out, 8'h00}:
(dma_sel?dma_data_out:
16'h0000))))));
wire init;
assign init = ~pll_locked;
video video (
.reset (init ), // reset input
.clk (clk_32 ),
.bus_cycle (bus_cycle ),
// spi for OSD
.sdi (SPI_DI ),
.sck (SPI_SCK ),
.ss (SPI_SS3 ),
// cpu register interface
.reg_clk (clk_8 ),
.reg_reset (reset ),
.reg_din (tg68_dat_out),
.reg_sel (vreg_sel ),
.reg_addr (tg68_adr[7:0]),
.reg_uds (tg68_uds ),
.reg_lds (tg68_lds ),
.reg_rw (tg68_rw ),
.reg_dout (vreg_data_out),
.reg_dtack (vreg_dtack ),
.vaddr (video_address ),
.data (video_data ),
.read (video_read ),
.hs (VGA_HS ),
.vs (VGA_VS ),
.video_r (VGA_R ),
.video_g (VGA_G ),
.video_b (VGA_B ),
.pal56 (~system_ctrl[9]),
.hsO (video_hs ),
.deO (video_de )
);
mmu mmu (
// cpu register interface
.clk (clk_8 ),
.reset (reset ),
.din (tg68_dat_out[7:0]),
.sel (mmu_sel ),
.ds (tg68_lds ),
.rw (tg68_rw ),
.dout (mmu_data_out),
.dtack (mmu_dtack )
);
wire acia_irq, dma_irq;
mfp mfp (
// cpu register interface
.clk (clk_8 ),
.reset (reset ),
.din (tg68_dat_out[7:0]),
.sel (mfp_sel ),
.addr (tg68_adr[7:0]),
.ds (tg68_lds ),
.rw (tg68_rw ),
.dout (mfp_data_out),
.dtack (mfp_dtack ),
.irq (mfp_irq ),
.iack (mfp_iack ),
// serial/rs232 interface
.serial_data_out_available (serial_data_from_mfp_available),
.serial_strobe_out (serial_strobe_from_mfp),
.serial_data_out (serial_data_from_mfp),
// input signals
.clk_ext (clk_mfp ),
.de (video_de ),
.dma_irq (dma_irq ),
.acia_irq (acia_irq ),
.mono_detect (system_ctrl[8])
);
acia acia (
// cpu interface
.clk (clk_8 ),
.reset (reset ),
.din (tg68_dat_out[15:8]),
.sel (acia_sel ),
.addr (tg68_adr[7:0]),
.ds (tg68_uds ),
.rw (tg68_rw ),
.dout (acia_data_out),
.dtack (acia_dtack ),
.irq (acia_irq ),
// ikbd interface
.ikbd_data_out_available (ikbd_data_from_acia_available),
.ikbd_strobe_out (ikbd_strobe_from_acia),
.ikbd_data_out (ikbd_data_from_acia),
.ikbd_strobe_in (ikbd_strobe_to_acia),
.ikbd_data_in (ikbd_data_to_acia)
);
//// ym2149 sound chip ////
reg [1:0] sclk;
always @ (posedge clk_8)
sclk <= sclk + 2'd1;
wire [7:0] port_a_out;
assign floppy_side = port_a_out[0];
assign floppy_sel = port_a_out[2:1];
wire [7:0] audio_out;
assign AUDIO_R = AUDIO_L;
assign psg_dtack = psg_sel;
sigma_delta_dac sigma_delta_dac (
.DACout (AUDIO_L),
.DACin (audio_out),
.CLK (clk_32),
.RESET (reset)
);
YM2149 ym2149 (
.I_DA ( tg68_dat_out[15:8] ),
.O_DA ( psg_data_out ),
.O_DA_OE_L ( ),
// control
.I_A9_L ( 1'b0 ),
.I_A8 ( 1'b1 ),
.I_BDIR ( psg_sel && !tg68_rw ),
.I_BC2 ( 1'b1 ),
.I_BC1 ( psg_sel && !tg68_adr[1]),
.I_SEL_L ( 1'b1 ),
.O_AUDIO ( audio_out ),
// port a
.I_IOA ( 8'd0 ),
.O_IOA ( port_a_out ),
.O_IOA_OE_L ( ),
// port b
.I_IOB ( 8'd0 ),
.O_IOB ( ),
.O_IOB_OE_L ( ),
//
.ENA ( 1'b1 ),
.RESET_L ( !reset ),
.CLK ( sclk[1] ) // 2 MHz
);
wire dma_dio_ack;
wire [4:0] dma_dio_idx;
wire [7:0 ]dma_dio_data;
// floppy_sel is active low
wire wr_prot = (floppy_sel == 2'b01)?system_ctrl[7]:system_ctrl[6];
dma dma (
// cpu interface
.clk (clk_8 ),
.reset (reset ),
.din (tg68_dat_out[15:0]),
.sel (dma_sel ),
.addr (tg68_adr[7:0]),
.uds (tg68_uds ),
.lds (tg68_lds ),
.rw (tg68_rw ),
.dout (dma_data_out),
.dtack (dma_dtack ),
.irq (dma_irq ),
// system control interface
.fdc_wr_prot (wr_prot),
// data_io (arm controller imterface)
.dio_idx (dma_dio_idx ),
.dio_data (dma_dio_data),
.dio_ack (dma_dio_ack ),
// floppy interface
.drv_sel (floppy_sel ),
.drv_side (floppy_side )
);
wire [1:0] floppy_sel;
wire floppy_side;
assign LED = (floppy_sel == 2'b11);
// clock generation
wire pll_locked;
wire clk_8;
wire clk_32;
wire clk_128;
wire clk_mfp;
// use pll
clock clock (
.areset (1'b0 ), // async reset input
.inclk0 (CLOCK_27[0] ), // input clock (27MHz)
.c0 (clk_128 ), // output clock c0 (128MHz)
.c1 (clk_32 ), // output clock c1 (32MHz)
.c2 (SDRAM_CLK ), // output clock c2 (128MHz)
.c3 (clk_mfp ), // output clock c3 (2.4576MHz)
.locked (pll_locked ) // pll locked output
);
//// 8MHz clock ////
wire [3:0] bus_cycle;
reg [3:0] clk_cnt;
always @ (posedge clk_32, negedge pll_locked) begin
if (!pll_locked)
clk_cnt <= #1 4'b0010;
else
clk_cnt <= #1 clk_cnt + 4'd1;
end
assign clk_8 = clk_cnt[1];
assign bus_cycle = clk_cnt-4'd2;
// SDRAM
assign SDRAM_CKE = 1'b1;
assign SDRAM_nCS = sdram_cs[0];
assign SDRAM_DQML = sdram_dqm[0];
assign SDRAM_DQMH = sdram_dqm[1];
wire [ 4-1:0] sdram_cs;
wire [ 2-1:0] sdram_dqm;
// host sdram interface used for io data up/download
wire [2:0] host_state;
wire [22:0] host_addr;
wire [15:0] host_dataWR;
wire [15:0] host_dataRD;
// tg68
wire [ 16-1:0] tg68_dat_in;
wire [ 16-1:0] tg68_dat_out;
wire [ 32-1:0] tg68_adr;
wire [ 3-1:0] tg68_IPL;
wire tg68_dtack;
wire tg68_as;
wire tg68_uds;
wire tg68_lds;
wire tg68_rw;
wire tg68_ena7RD;
wire tg68_ena7WR;
wire tg68_enaWR;
wire [ 16-1:0] tg68_cout;
wire tg68_cpuena;
// wire [ 2-1:0] cpu_config;
// wire [ 6-1:0] memcfg;
wire [ 32-1:0] tg68_cad;
wire [ 6-1:0] tg68_cpustate;
wire tg68_cdma;
wire tg68_clds;
wire tg68_cuds;
wire reset;
assign reset = system_ctrl[0];
// ------------- generate VBI (IPL = 4) --------------
wire vbi_ack;
assign vbi_ack = cpu2iack && data_strobe && (tg68_adr[3:1] == 3'b100);
reg vsD, vsD2, vsI, vbi;
always @(negedge clk_8)
vsD <= VGA_VS;
always @(posedge clk_8) begin
vsD2 <= vsD; // delay by one
vsI <= vsD && !vsD2; // create single event
if(reset || vbi_ack)
vbi <= 1'b0;
else if(vsI)
vbi <= 1'b1;
end
// ------------- generate HBI (IPL = 2) --------------
wire hbi_ack;
assign hbi_ack = cpu2iack && data_strobe && (tg68_adr[3:1] == 3'b010);
reg hsD, hsD2, hsI, hbi;
always @(negedge clk_8)
hsD <= video_hs;
always @(posedge clk_8) begin
hsD2 <= hsD; // delay by one
hsI <= hsD && !hsD2; // create single event
if(reset || hbi_ack)
hbi <= 1'b0;
else if(hsI)
hbi <= 1'b1;
end
wire mfp_irq;
reg [2:0] ipl;
always @(posedge clk_8) begin
if(reset) begin
ipl <= 3'b111;
end else begin
// ipl[0] is tied high on the atari
if(mfp_irq) ipl <= 3'b001; // mfp has IPL 6
else if(vbi) ipl <= 3'b011; // vbi has IPL 4
else if(hbi) ipl <= 3'b101; // hbi has IPL 2
else ipl <= 3'b111;
end
end
//// TG68K main CPU ////
TG68K tg68k (
.clk (clk_128 ),
.reset (~reset ),
.clkena_in (1'b1 ),
.IPL (ipl ), // 3'b111
.dtack (tg68_dtack ),
.vpa (1'b1 ),
.ein (1'b1 ),
.addr (tg68_adr ),
.data_read (cpu_data_in ),
.data_write (tg68_dat_out ),
.as (tg68_as ),
.uds (tg68_uds ),
.lds (tg68_lds ),
.rw (tg68_rw ),
.berr (tg68_berr ),
.e ( ),
.vma ( ),
.wrd ( ),
.ena7RDreg (tg68_ena7RD ),
.ena7WRreg (tg68_ena7WR ),
.enaWRreg (tg68_enaWR ),
.fromram (tg68_cout ),
.ramready (tg68_cpuena ),
.cpu (system_ctrl[5:4] ), // 00=68000
.memcfg (6'b000000 ), // 00XXXX = no fastmem
.ramaddr (tg68_cad ),
.cpustate (tg68_cpustate ),
.nResetOut ( ),
.skipFetch ( ),
.cpuDMA (tg68_cdma ),
.ramlds (tg68_clds ),
.ramuds (tg68_cuds )
);
//
wire [15:0] cpu_data_in;
assign cpu_data_in = cpu2mem?ram_data:io_data_out;
// cpu/video stram multiplexing
wire video_cycle;
wire cpu_cycle;
wire [22:0] ram_address;
wire [15:0] ram_data;
assign video_cycle = (bus_cycle[3:2] == 0); // 1 is host/spi cycle
assign cpu_cycle = (bus_cycle[3:2] == 2);
assign ram_address = video_cycle?video_address:tg68_adr[23:1];
assign video_data = ram_data;
// TODO: put 0x000000 to 0x000007 into tos section so it's write protected
wire MEM512K = (system_ctrl[3:1] == 3'd0);
wire MEM1M = (system_ctrl[3:1] == 3'd1);
wire MEM2M = (system_ctrl[3:1] == 3'd2);
wire MEM4M = (system_ctrl[3:1] == 3'd3);
wire MEM8M = (system_ctrl[3:1] == 3'd4);
wire MEM14M = (system_ctrl[3:1] == 3'd5);
// ram from 0x000000 to 0x400000
wire cpu2ram;
assign cpu2ram = (tg68_adr[23:22] == 2'b00) || // ordinary 4MB
((MEM14M || MEM8M) && (tg68_adr[23:22] == 2'b01)) || // MiST special 8MB
(MEM14M && ((tg68_adr[23:22] == 2'b10) |
(tg68_adr[23:21] == 3'b110))); // MiST special 14MB
// 256k tos from 0xe00000 to 0xe40000
wire cpu2tos256k;
assign cpu2tos256k = (tg68_adr[23:18] == 6'b111000);
// 192k tos from 0xfc0000 to 0xff0000
wire cpu2tos192k;
assign cpu2tos192k = (tg68_adr[23:17] == 7'b1111110) ||
(tg68_adr[23:16] == 8'b11111110);
// 128k cartridge from 0xfa0000 to 0xfc0000
wire cpu2cart;
assign cpu2cart = (tg68_adr[23:17] == 7'b1111101);
// cpu to any type of mem (rw on ram, read on rom)
wire cpu2mem;
assign cpu2mem = cpu2ram || (tg68_rw && (cpu2tos192k || cpu2tos256k || cpu2cart));
// io from 0xff0000
wire cpu2io;
assign cpu2io = (tg68_adr[23:16] == 8'b11111111);
// irq ack happens on 0xfffffX
wire cpu2iack;
assign cpu2iack = (tg68_adr[23:4] == 20'hfffff);
wire data_strobe;
assign data_strobe = ~tg68_uds || ~tg68_lds;
// generate dtack (for st ram only and rom), TODO: no dtack for rom write
assign tg68_dtack = ~((cpu2mem && data_strobe && cpu_cycle) || io_dtack );
wire ram_oe;
assign ram_oe = video_cycle?~video_read:
(cpu_cycle?~(data_strobe && tg68_rw && cpu2mem):1'b1);
wire ram_wr;
assign ram_wr = cpu_cycle?~(data_strobe && ~tg68_rw && cpu2ram):1'b1;
// data strobe
wire ram_uds;
assign ram_uds = video_cycle?1'b0:tg68_uds;
wire ram_lds;
assign ram_lds = video_cycle?1'b0:tg68_lds;
//// sdram ////
sdram sdram (
.sdata (SDRAM_DQ ),
.sdaddr (SDRAM_A ),
.dqm (sdram_dqm ),
.sd_cs (sdram_cs ),
.ba (SDRAM_BA ),
.sd_we (SDRAM_nWE ),
.sd_ras (SDRAM_nRAS ),
.sd_cas (SDRAM_nCAS ),
.sysclk (clk_128 ),
.reset_in (~init ),
.hostWR (host_dataWR ),
.hostAddr ({host_addr,1'b0} ),
.hostState (host_state ),
.hostL (1'b0 ),
.hostU (1'b0 ),
.hostRD (host_dataRD ),
.hostena ( ),
// fast ram interface
.cpuWR (tg68_dat_out ),
.cpuAddr (tg68_cad[24:1] ),
.cpuU (tg68_cuds ),
.cpuL (tg68_clds ),
.cpustate (tg68_cpustate ), // 6'b100101
.cpu_dma (tg68_cdma ),
.cpuRD (tg68_cout ),
.cpuena (tg68_cpuena ),
.enaRDreg ( ),
.enaWRreg (tg68_enaWR ),
.ena7RDreg (tg68_ena7RD ),
.ena7WRreg (tg68_ena7WR ),
// chip/slow ram interface
.chipWR (tg68_dat_out ),
.chipAddr (ram_address ),
.chipU (ram_uds ),
.chipL (ram_lds ),
.chipRW (ram_wr ),
.chip_dma (ram_oe ),
.c_7m (clk_8 ),
.chipRD (ram_data ),
.reset_out ( )
);
// multiplex spi_do, drive it from user_io if that's selected, drive
// it from minimig if it's selected and leave it open else (also
// to be able to monitor sd card data directly)
wire data_io_sdo;
wire user_io_sdo;
assign SPI_DO = (CONF_DATA0 == 1'b0)?user_io_sdo:
((SPI_SS2 == 1'b0)?data_io_sdo:1'bZ);
wire [15:0] system_ctrl;
// connection to transfer ikbd data from io controller to acia
wire [7:0] ikbd_data_to_acia;
wire ikbd_strobe_to_acia;
// connection to transfer ikbd data from acia to io controller
wire [7:0] ikbd_data_from_acia;
wire ikbd_strobe_from_acia;
wire ikbd_data_from_acia_available;
// connection to transfer serial/rs232 data from mfp to io controller
wire [7:0] serial_data_from_mfp;
wire serial_strobe_from_mfp;
wire serial_data_from_mfp_available;
//// user io has an extra spi channel outside minimig core ////
user_io user_io(
.SPI_CLK(SPI_SCK),
.SPI_SS_IO(CONF_DATA0),
.SPI_MISO(user_io_sdo),
.SPI_MOSI(SPI_DI),
.BUTTONS(buttons),
// ikbd interface
.ikbd_strobe_out(ikbd_strobe_from_acia),
.ikbd_data_out(ikbd_data_from_acia),
.ikbd_data_out_available(ikbd_data_from_acia_available),
.ikbd_strobe_in(ikbd_strobe_to_acia),
.ikbd_data_in(ikbd_data_to_acia),
// serial/rs232 interface
.serial_strobe_out(serial_strobe_from_mfp),
.serial_data_out(serial_data_from_mfp),
.serial_data_out_available(serial_data_from_mfp_available),
.CORE_TYPE(8'ha3) // mist core id
);
data_io data_io (
// system control
.clk_8 (clk_8 ),
.reset (init ),
.bus_cycle (bus_cycle[3:2]),
.ctrl_out (system_ctrl ),
// spi
.sdi (SPI_DI ),
.sck (SPI_SCK ),
.ss (SPI_SS2 ),
.sdo (data_io_sdo ),
// dma interface
.dma_idx (dma_dio_idx ),
.dma_data (dma_dio_data ),
.dma_ack (dma_dio_ack ),
// ram interface
.state (host_state ),
.addr (host_addr ),
.data_out (host_dataWR ),
.data_in (host_dataRD )
);
endmodule

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module mmu (
// cpu register interface
input clk,
input reset,
input [7:0] din,
input sel,
input ds,
input rw,
output reg [7:0] dout,
output dtack
);
// dtack
assign dtack = sel;
reg [7:0] memconfig;
always @(sel, ds, rw) begin
dout = 8'd0;
if(sel && ~ds && rw)
dout = memconfig;
end
always @(negedge clk) begin
if(reset)
memconfig <= 8'h00;
else begin
if(sel && ~ds && ~rw)
memconfig <= din;
end
end
endmodule

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module psg (
// cpu register interface
input clk,
input reset,
input [7:0] din,
input sel,
input [7:0] addr,
input ds,
input rw,
output reg [7:0] dout,
output dtack,
output drv_side,
output [1:0] drv_sel
);
// port a is partly used to select the floppy
assign drv_side = port_a[0];
assign drv_sel = { port_a[2], port_a[1] };
// ------------------ cpu interface --------------------
reg [7:0] port_a;
reg [3:0] reg_sel;
// dtack
assign dtack = sel;
always @(sel, ds, rw, addr) begin
dout = 8'h00;
if(sel && ~ds && rw) begin
// read from selected register
if(addr == 8'h00 && reg_sel == 4'd14)
dout = port_a;
end
end
always @(negedge clk) begin
if(reset) begin
reg_sel <= 4'd0;
port_a <= 8'd0;
end else begin
// keyboard acia data register writes into buffer
if(sel && ~ds && ~rw) begin
// register select
if(addr == 8'h00)
reg_sel <= din[3:0];
// write to selected register
if(addr == 8'h02 && reg_sel == 4'd14)
port_a <= din;
end
end
end
endmodule

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------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2011 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sdram is
port
(
sdata : inout std_logic_vector(15 downto 0);
sdaddr : out std_logic_vector(12 downto 0);
dqm : out std_logic_vector(1 downto 0);
sd_cs : out std_logic_vector(3 downto 0);
ba : buffer std_logic_vector(1 downto 0);
sd_we : out std_logic;
sd_ras : out std_logic;
sd_cas : out std_logic;
sysclk : in std_logic;
reset_in : in std_logic;
hostWR : in std_logic_vector(15 downto 0);
hostAddr : in std_logic_vector(23 downto 0);
hostState : in std_logic_vector(2 downto 0);
hostL : in std_logic;
hostU : in std_logic;
cpuWR : in std_logic_vector(15 downto 0);
cpuAddr : in std_logic_vector(24 downto 1);
cpuU : in std_logic;
cpuL : in std_logic;
cpustate : in std_logic_vector(5 downto 0);
cpu_dma : in std_logic;
chipWR : in std_logic_vector(15 downto 0);
chipAddr : in std_logic_vector(23 downto 1);
chipU : in std_logic;
chipL : in std_logic;
chipRW : in std_logic;
chip_dma : in std_logic;
c_7m : in std_logic;
hostRD : out std_logic_vector(15 downto 0);
hostena : buffer std_logic;
cpuRD : out std_logic_vector(15 downto 0);
cpuena : out std_logic;
chipRD : out std_logic_vector(15 downto 0);
reset_out : out std_logic;
enaRDreg : out std_logic;
enaWRreg : buffer std_logic;
ena7RDreg : out std_logic;
ena7WRreg : out std_logic
-- c_7m : out std_logic
);
end;
architecture rtl of sdram is
signal initstate :std_logic_vector(3 downto 0);
signal cas_sd_cs :std_logic_vector(3 downto 0);
signal cas_sd_ras :std_logic;
signal cas_sd_cas :std_logic;
signal cas_sd_we :std_logic;
signal cas_dqm :std_logic_vector(1 downto 0);
signal init_done :std_logic;
signal datain :std_logic_vector(15 downto 0);
signal datawr :std_logic_vector(15 downto 0);
signal casaddr :std_logic_vector(24 downto 0);
signal sdwrite :std_logic;
signal sdata_reg :std_logic_vector(15 downto 0);
signal hostCycle :std_logic;
signal zmAddr :std_logic_vector(24 downto 0);
signal zena :std_logic;
signal zcache :std_logic_vector(63 downto 0);
signal zcache_addr :std_logic_vector(23 downto 0);
signal zcache_fill :std_logic;
signal zcachehit :std_logic;
signal zvalid :std_logic_vector(3 downto 0);
signal zequal :std_logic;
signal hostStated :std_logic_vector(1 downto 0);
signal hostRDd :std_logic_vector(15 downto 0);
signal cena :std_logic;
signal ccache :std_logic_vector(63 downto 0);
signal ccache_addr :std_logic_vector(24 downto 0);
signal ccache_fill :std_logic;
signal ccachehit :std_logic;
signal cvalid :std_logic_vector(3 downto 0);
signal cequal :std_logic;
signal cpuStated :std_logic_vector(1 downto 0);
signal cpuRDd :std_logic_vector(15 downto 0);
signal hostSlot_cnt :std_logic_vector(7 downto 0);
signal reset_cnt :std_logic_vector(7 downto 0);
signal reset :std_logic;
signal reset_sdstate :std_logic;
signal c_7md :std_logic;
signal c_7mdd :std_logic;
signal c_7mdr :std_logic;
signal cpuCycle :std_logic;
signal chipCycle :std_logic;
signal slow :std_logic_vector(7 downto 0);
type sdram_states is (ph0,ph1,ph2,ph3,ph4,ph5,ph6,ph7,ph8,ph9,ph10,ph11,ph12,ph13,ph14,ph15);
signal sdram_state : sdram_states;
type pass_states is (nop,ras,cas);
signal pass : pass_states;
begin
process (sysclk, reset_in) begin
if reset_in = '0' THEN
reset_cnt <= "00000000";
reset <= '0';
reset_sdstate <= '0';
elsif (sysclk'event and sysclk='1') THEN
IF reset_cnt="00101010"THEN
reset_sdstate <= '1';
END IF;
IF reset_cnt="10101010"THEN
if sdram_state=ph15 then
reset <= '1';
end if;
ELSE
reset_cnt <= reset_cnt+1;
reset <= '0';
END IF;
end if;
end process;
-------------------------------------------------------------------------
-- SPIHOST cache
-------------------------------------------------------------------------
hostena <= '1' when zena='1' or hostState(1 downto 0)="01" OR zcachehit='1' else '0';
-- TH zmAddr <= '0'& NOT hostAddr(23) & hostAddr(22) & NOT hostAddr(21) & hostAddr(20 downto 0);
zmAddr <= '0'& hostAddr(23 downto 0);
process (sysclk, zmAddr, hostAddr, zcache_addr, zcache, zequal, zvalid, hostRDd)
begin
if zmAddr(23 downto 3)=zcache_addr(23 downto 3) THEN
zequal <='1';
else
zequal <='0';
end if;
zcachehit <= '0';
if zequal='1' and zvalid(0)='1' and hostStated(1)='0' THEN
-- case (hostAddr(2 downto 1)-zcache_addr(2 downto 1)) is
-- when "00"=>
-- zcachehit <= zvalid(0);
-- hostRD <= zcache(63 downto 48);
-- when "01"=>
-- zcachehit <= zvalid(1);
-- hostRD <= zcache(47 downto 32);
-- when "10"=>
-- zcachehit <= zvalid(2);
-- hostRD <= zcache(31 downto 16);
-- when "11"=>
-- zcachehit <= zvalid(3);
-- hostRD <= zcache(15 downto 0);
-- when others=> null;
-- end case;
case (hostAddr(2 downto 1)&zcache_addr(2 downto 1)) is
when "0000"|"0101"|"1010"|"1111"=>
zcachehit <= zvalid(0);
hostRD <= zcache(63 downto 48);
when "0100"|"1001"|"1110"|"0011"=>
zcachehit <= zvalid(1);
hostRD <= zcache(47 downto 32);
when "1000"|"1101"|"0010"|"0111"=>
zcachehit <= zvalid(2);
hostRD <= zcache(31 downto 16);
when "1100"|"0001"|"0110"|"1011"=>
zcachehit <= zvalid(3);
hostRD <= zcache(15 downto 0);
when others=> null;
end case;
else
hostRD <= hostRDd;
end if;
end process;
--Daten<65>bernahme
process (sysclk, reset) begin
if reset = '0' THEN
zcache_fill <= '0';
zena <= '0';
zvalid <= "0000";
elsif (sysclk'event and sysclk='1') THEN
if enaWRreg='1' THEN
zena <= '0';
end if;
if sdram_state=ph9 AND hostCycle='1' THEN
hostRDd <= sdata_reg;
-- if zmAddr=casaddr and cas_sd_cas='0' then
-- zena <= '1';
-- end if;
end if;
if sdram_state=ph11 AND hostCycle='1' THEN
-- hostRDd <= sdata_reg;
if zmAddr=casaddr and cas_sd_cas='0' then
zena <= '1';
end if;
end if;
hostStated <= hostState(1 downto 0);
if zequal='1' and hostState(1 downto 0)="11" THEN
zvalid <= "0000";
end if;
case sdram_state is
when ph7 =>
if hostStated(1)='0' AND hostCycle='1' THEN --only instruction cache
-- if cas_sd_we='1' AND hostStated(1)='0' AND hostCycle='1' THEN --only instruction cache
-- if cas_sd_we='1' AND hostCycle='1' THEN
zcache_addr <= casaddr(23 downto 0);
zcache_fill <= '1';
zvalid <= "0000";
end if;
when ph9 =>
if zcache_fill='1' THEN
zcache(63 downto 48) <= sdata_reg;
-- zvalid(0) <= '1';
end if;
when ph10 =>
if zcache_fill='1' THEN
zcache(47 downto 32) <= sdata_reg;
-- zvalid(1) <= '1';
end if;
when ph11 =>
if zcache_fill='1' THEN
zcache(31 downto 16) <= sdata_reg;
-- zvalid(2) <= '1';
end if;
-- zena <= '0';
when ph12 =>
if zcache_fill='1' THEN
zcache(15 downto 0) <= sdata_reg;
-- zvalid(3) <= '1';
zvalid <= "1111";
end if;
zcache_fill <= '0';
when others => null;
end case;
end if;
end process;
-------------------------------------------------------------------------
-- cpu cache
-------------------------------------------------------------------------
cpuena <= '1' when cena='1' or ccachehit='1' else '0';
process (sysclk, cpuAddr, ccache_addr, ccache, cequal, cvalid, cpuRDd)
begin
if cpuAddr(24 downto 3)=ccache_addr(24 downto 3) THEN
cequal <='1';
else
cequal <='0';
end if;
ccachehit <= '0';
if cequal='1' and cvalid(0)='1' and cpuStated(1)='0' THEN
-- case (cpuAddr(2 downto 1)-ccache_addr(2 downto 1)) is
-- when "00"=>
-- ccachehit <= cvalid(0);
-- cpuRD <= ccache(63 downto 48);
-- when "01"=>
-- ccachehit <= cvalid(1);
-- cpuRD <= ccache(47 downto 32);
-- when "10"=>
-- ccachehit <= cvalid(2);
-- cpuRD <= ccache(31 downto 16);
-- when "11"=>
-- ccachehit <= cvalid(3);
-- cpuRD <= ccache(15 downto 0);
-- when others=> null;
-- end case;
case (cpuAddr(2 downto 1)&ccache_addr(2 downto 1)) is
when "0000"|"0101"|"1010"|"1111"=>
ccachehit <= cvalid(0);
cpuRD <= ccache(63 downto 48);
when "0100"|"1001"|"1110"|"0011"=>
ccachehit <= cvalid(1);
cpuRD <= ccache(47 downto 32);
when "1000"|"1101"|"0010"|"0111"=>
ccachehit <= cvalid(2);
cpuRD <= ccache(31 downto 16);
when "1100"|"0001"|"0110"|"1011"=>
ccachehit <= cvalid(3);
cpuRD <= ccache(15 downto 0);
when others=> null;
end case;
else
cpuRD <= cpuRDd;
end if;
end process;
--Daten<65>bernahme
process (sysclk, reset) begin
if reset = '0' THEN
ccache_fill <= '0';
cena <= '0';
cvalid <= "0000";
elsif (sysclk'event and sysclk='1') THEN
if cpuState(5)='1' THEN
cena <= '0';
end if;
if sdram_state=ph9 AND cpuCycle='1' THEN
cpuRDd <= sdata_reg;
-- if cpuAddr=casaddr(24 downto 1) and cas_sd_cas='0' then
-- cena <= '1';
-- end if;
end if;
if sdram_state=ph11 AND cpuCycle='1' THEN
-- cpuRDd <= sdata_reg;
if cpuAddr=casaddr(24 downto 1) and cas_sd_cas='0' then
cena <= '1';
end if;
end if;
cpuStated <= cpuState(1 downto 0);
if cequal='1' and cpuState(1 downto 0)="11" THEN
cvalid <= "0000";
end if;
case sdram_state is
when ph7 =>
if cpuStated(1)='0' AND cpuCycle='1' THEN --only instruction cache
-- if cas_sd_we='1' AND hostStated(1)='0' AND hostCycle='1' THEN --only instruction cache
-- if cas_sd_we='1' AND hostCycle='1' THEN
ccache_addr <= casaddr;
ccache_fill <= '1';
cvalid <= "0000";
end if;
when ph9 =>
if ccache_fill='1' THEN
ccache(63 downto 48) <= sdata_reg;
-- cvalid(0) <= '1';
end if;
when ph10 =>
if ccache_fill='1' THEN
ccache(47 downto 32) <= sdata_reg;
-- cvalid(1) <= '1';
end if;
when ph11 =>
if ccache_fill='1' THEN
ccache(31 downto 16) <= sdata_reg;
-- cvalid(2) <= '1';
end if;
when ph12 =>
if ccache_fill='1' THEN
ccache(15 downto 0) <= sdata_reg;
-- cvalid(3) <= '1';
cvalid <= "1111";
end if;
ccache_fill <= '0';
when others => null;
end case;
end if;
end process;
-------------------------------------------------------------------------
-- chip cache
-------------------------------------------------------------------------
process (sysclk, sdata_reg)
begin
if (sysclk'event and sysclk='1') THEN
if sdram_state=ph9 AND chipCycle='1' THEN
chipRD <= sdata_reg;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- SDRAM Basic
-------------------------------------------------------------------------
reset_out <= init_done;
process (sysclk, reset, sdwrite, datain) begin
IF sdwrite='1' THEN
sdata <= datawr;
ELSE
sdata <= "ZZZZZZZZZZZZZZZZ";
END IF;
if (sysclk'event and sysclk='0') THEN
c_7md <= c_7m;
END IF;
if (sysclk'event and sysclk='1') THEN
if sdram_state=ph2 THEN
IF chipCycle='1' THEN
datawr <= chipWR;
ELSIF cpuCycle='1' THEN
datawr <= cpuWR;
ELSE
datawr <= hostWR;
END IF;
END IF;
sdata_reg <= sdata;
c_7mdd <= c_7md;
c_7mdr <= c_7md AND NOT c_7mdd;
if reset_sdstate = '0' then
sdwrite <= '0';
enaRDreg <= '0';
enaWRreg <= '0';
ena7RDreg <= '0';
ena7WRreg <= '0';
ELSE
sdwrite <= '0';
enaRDreg <= '0';
enaWRreg <= '0';
ena7RDreg <= '0';
ena7WRreg <= '0';
case sdram_state is --LATENCY=3
when ph2 => sdwrite <= '1';
enaWRreg <= '1';
when ph3 => sdwrite <= '1';
when ph4 => sdwrite <= '1';
when ph5 => sdwrite <= '1';
when ph6 => enaWRreg <= '1';
ena7RDreg <= '1';
-- when ph7 => c_7m <= '0';
when ph10 => enaWRreg <= '1';
when ph14 => enaWRreg <= '1';
ena7WRreg <= '1';
-- when ph15 => c_7m <= '1';
when others => null;
end case;
END IF;
if reset = '0' then
initstate <= (others => '0');
init_done <= '0';
ELSE
case sdram_state is --LATENCY=3
when ph15 => if initstate /= "1111" THEN
initstate <= initstate+1;
else
init_done <='1';
end if;
when others => null;
end case;
END IF;
IF c_7mdr='1' THEN
sdram_state <= ph2;
-- if reset_sdstate = '0' then
-- sdram_state <= ph0;
ELSE
case sdram_state is --LATENCY=3
when ph0 => sdram_state <= ph1;
when ph1 => sdram_state <= ph2;
-- when ph1 =>
-- IF c_28md='1' THEN
-- sdram_state <= ph2;
-- ELSE
-- sdram_state <= ph1;
-- END IF;
when ph2 => sdram_state <= ph3;
-- when ph2 => --sdram_state <= ph3;
-- IF c_28md='0' THEN
-- sdram_state <= ph3;
-- ELSE
-- sdram_state <= ph2;
-- END IF;
when ph3 => sdram_state <= ph4;
when ph4 => sdram_state <= ph5;
when ph5 => sdram_state <= ph6;
when ph6 => sdram_state <= ph7;
when ph7 => sdram_state <= ph8;
when ph8 => sdram_state <= ph9;
when ph9 => sdram_state <= ph10;
when ph10 => sdram_state <= ph11;
when ph11 => sdram_state <= ph12;
when ph12 => sdram_state <= ph13;
when ph13 => sdram_state <= ph14;
when ph14 => sdram_state <= ph15;
-- when ph15 => sdram_state <= ph0;
when others => sdram_state <= ph0;
end case;
END IF;
END IF;
end process;
process (sysclk, initstate, pass, hostAddr, datain, init_done, casaddr, cpuU, cpuL, hostCycle) begin
if (sysclk'event and sysclk='1') THEN
sd_cs <="1111";
sd_ras <= '1';
sd_cas <= '1';
sd_we <= '1';
sdaddr <= "XXXXXXXXXXXXX";
ba <= "00";
dqm <= "00";
if init_done='0' then
if sdram_state =ph1 then
case initstate is
when "0010" => --PRECHARGE
sdaddr(10) <= '1'; --all banks
sd_cs <="0000";
sd_ras <= '0';
sd_cas <= '1';
sd_we <= '0';
when "0011"|"0100"|"0101"|"0110"|"0111"|"1000"|"1001"|"1010"|"1011"|"1100" => --AUTOREFRESH
sd_cs <="0000";
sd_ras <= '0';
sd_cas <= '0';
sd_we <= '1';
when "1101" => --LOAD MODE REGISTER
sd_cs <="0000";
sd_ras <= '0';
sd_cas <= '0';
sd_we <= '0';
-- ba <= "00";
-- sdaddr <= "0001000100010"; --BURST=4 LATENCY=2
sdaddr <= "0001000110010"; --BURST=4 LATENCY=3
when others => null; --NOP
end case;
END IF;
else
-- Time slot control
if sdram_state=ph1 THEN
cpuCycle <= '0';
chipCycle <= '0';
hostCycle <= '0';
cas_sd_cs <= "1110";
cas_sd_ras <= '1';
cas_sd_cas <= '1';
cas_sd_we <= '1';
IF slow(2 downto 0)=5 THEN
slow <= slow+3;
ELSE
slow <= slow+1;
END IF;
-- IF dma='0' OR cpu_dma='0' THEN
IF hostSlot_cnt /= "00000000" THEN
hostSlot_cnt <= hostSlot_cnt-1;
END IF;
-- IF chip_dma='1' THEN
IF chip_dma='0' OR chipRW='0' THEN
chipCycle <= '1';
sdaddr <= '0'&chipAddr(20 downto 9);
-- ba <= "00";
ba <= chipAddr(22 downto 21);
-- cas_dqm <= "00"; --only word access
cas_dqm <= chipU& chipL;
sd_cs <= "1110"; --ACTIVE
sd_ras <= '0';
casaddr <= '0'&chipAddr&'0';
datain <= chipWR;
cas_sd_cas <= '0';
cas_sd_we <= chipRW;
-- ELSIF cpu_dma='1' AND hostSlot_cnt /= "00000000" THEN
-- ELSIF cpu_dma='0' OR cpuRW='0' THEN
ELSIF cpuState(2)='0' AND cpuState(5)='0' THEN
cpuCycle <= '1';
sdaddr <= cpuAddr(24)&cpuAddr(20 downto 9);
ba <= cpuAddr(22 downto 21);
cas_dqm <= cpuU& cpuL;
sd_cs <= "1110"; --ACTIVE
sd_ras <= '0';
casaddr <= cpuAddr(24 downto 1)&'0';
datain <= cpuWR;
cas_sd_cas <= '0';
cas_sd_we <= NOT cpuState(1) OR NOT cpuState(0);
ELSE
hostSlot_cnt <= "00001111";
-- ELSIF hostState(2)='1' OR hostena='1' OR slow(3 downto 0)="0001" THEN --refresh cycle
IF hostState(2)='1' OR hostena='1' THEN --refresh cycle
-- ELSIF slow(3 downto 0)="0001" THEN --refresh cycle
sd_cs <="0000"; --AUTOREFRESH
sd_ras <= '0';
sd_cas <= '0';
ELSE
hostCycle <= '1';
sdaddr <= '0'&zmAddr(20 downto 9);
ba <= zmAddr(22 downto 21);
cas_dqm <= hostU& hostL;
sd_cs <= "1110"; --ACTIVE
sd_ras <= '0';
casaddr <= zmAddr;
datain <= hostWR;
cas_sd_cas <= '0';
IF hostState="011" THEN
cas_sd_we <= '0';
-- dqm <= hostU& hostL;
END IF;
END IF;
END IF;
END IF;
if sdram_state=ph4 then
sdaddr <= '0'&'0' & '1' & '0' & casaddr(23)&casaddr(8 downto 1);--auto precharge
ba <= casaddr(22 downto 21);
sd_cs <= cas_sd_cs;
IF cas_sd_we='0' THEN
dqm <= cas_dqm;
END IF;
sd_ras <= cas_sd_ras;
sd_cas <= cas_sd_cas;
sd_we <= cas_sd_we;
END IF;
END IF;
END IF;
END process;
END;

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module sigma_delta_dac(
output reg DACout, //Average Output feeding analog lowpass
input [MSBI:0] DACin, //DAC input (excess 2**MSBI)
input CLK,
input RESET
);
parameter MSBI = 7;
reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder
reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder
reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder
reg [MSBI+2:0] DeltaB; //B input of Delta Adder
always @ (*)
DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
always @(*)
DeltaAdder = DACin + DeltaB;
always @(*)
SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge CLK or posedge RESET)
if(RESET) begin
SigmaLatch <= 1'b1 << (MSBI+1);
DACout <= 1'b0;
end else begin
SigmaLatch <= SigmaAdder;
DACout <= SigmaLatch[MSBI+2];
end
endmodule

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module user_io(
input SPI_CLK,
input SPI_SS_IO,
output reg SPI_MISO,
input SPI_MOSI,
input [7:0] CORE_TYPE,
// ikbd tdata from io controller to acia
output reg ikbd_strobe_in,
output reg [7:0] ikbd_data_in,
// ikbd data from acia to io controller
output reg ikbd_strobe_out,
input ikbd_data_out_available,
input [7:0] ikbd_data_out,
// serial data from mfp to io controller
output reg serial_strobe_out,
input serial_data_out_available,
input [7:0] serial_data_out,
output [1:0] BUTTONS,
output [1:0] SWITCHES
);
reg toggle;
reg [6:0] sbuf;
reg [7:0] cmd;
reg [5:0] cnt;
reg [3:0] but_sw;
assign BUTTONS = but_sw[1:0];
assign SWITCHES = but_sw[3:2];
always@(negedge SPI_CLK) begin
if(cnt <= 7)
SPI_MISO <= CORE_TYPE[7-cnt];
else begin
// ikbd acia->io controller
if(cmd == 3) begin
if(!toggle)
SPI_MISO <= ikbd_data_out_available;
else
SPI_MISO <= ikbd_data_out[15-cnt];
end
// serial mfp->io controller
if(cmd == 5) begin
if(!toggle)
SPI_MISO <= serial_data_out_available;
else
SPI_MISO <= serial_data_out[15-cnt];
end
end
end
always@(posedge SPI_CLK, posedge SPI_SS_IO) begin
if(SPI_SS_IO == 1) begin
cnt <= 0;
toggle <= 1'b0;
ikbd_strobe_in <= 1'b0;
ikbd_strobe_out <= 1'b0;
serial_strobe_out <= 1'b0;
end else begin
sbuf[6:1] <= sbuf[5:0];
sbuf[0] <= SPI_MOSI;
// count 0-7 8-15 8-15 8-15
if(cnt != 6'd15)
cnt <= cnt + 6'd1;
else begin
cnt <= 6'd8;
toggle <= !toggle;
end
// assemble command
if(cnt == 7) begin
cmd[7:1] <= sbuf;
cmd[0] <= SPI_MOSI;
end
if(cnt == 9) begin
ikbd_strobe_in <= 1'b0;
ikbd_strobe_out <= 1'b0;
serial_strobe_out <= 1'b0;
end
// payload byte
if(cnt == 15) begin
if(cmd == 1) begin
but_sw[3:1] <= sbuf[2:0];
but_sw[0] <= SPI_MOSI;
end
if(cmd == 2) begin
ikbd_data_in[7:1] <= sbuf;
ikbd_data_in[0] <= SPI_MOSI;
ikbd_strobe_in <= 1'b1;
end
// give strobe after second ikbd byte (toggle ==1)
if((cmd == 3) && toggle)
ikbd_strobe_out <= 1'b1;
// give strobe after second serial byte (toggle ==1)
if((cmd == 5) && toggle)
serial_strobe_out <= 1'b1;
end
end
end
endmodule

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// http://martin.hinner.info/vga/timing.html
// http://www.epanorama.net/faq/vga2rgb/calc.html
// original atari video timing
// mono color
// pclk 32MHz 16/8MHz
// hfreq 35.7kHz 15.75kHz
// vfreq 71.2Hz 50/60Hz
//
// avg. values derived from frequencies:
// hdisp 640 640/320
// htot 896 1015/507
// vdisp 400 200
// vtot 501 315/262
module video (
// system interface
input clk, // 31.875 MHz
input reset, // reset
input [3:0] bus_cycle,
// SPI interface for OSD
input sck,
input ss,
input sdi,
// memory interface
output reg [22:0] vaddr, // video word address counter
output read, // video read cycle
input [15:0] data,
// cpu register interface
input reg_clk,
input reg_reset,
input [15:0] reg_din,
input reg_sel,
input [7:0] reg_addr,
input reg_uds,
input reg_lds,
input reg_rw,
output reg [15:0] reg_dout,
output reg_dtack,
// screen interface
output hs, // H_SYNC
output vs, // V_SYNC
output [5:0] video_r, // Red[5:0]
output [5:0] video_g, // Green[5:0]
output [5:0] video_b, // Blue[5:0]
// system config
input pal56, // use VGA compatible 56hz for PAL
// for internal use
output deO,
output hsO
);
// basic video parameters
localparam H_PRE = 10'd16; // 16 clocks read prefetch
localparam H_ACT = 10'd640;
localparam V_ACT = 10'd400;
// default video mode is
parameter DEFAULT_MODE = 2'd2;
// output a de/hs signal with half the hsyncs in color mode
assign deO = ~(mono?de:deC);
assign hsO = mono?hs:hsC;
// line buffer for scan doubler for color video modes
// the color modes have 80 words per line (320*4/16 or 640*2/16) and
// we need space for two lines -> 160 words
reg [15:0] sd_buffer [255:0];
reg [6:0] sd_wptr, sd_rptr;
reg [15:0] dataR;
// instance of video timing module for monochrome (72hz)
wire [9:0] vcnt_mono, hcnt_mono;
wire hs_mono, vs_mono, hmax_mono, vmax_mono;
timing timing_mono (
.clk (clk ),
.reset (reset ),
.vcnt (vcnt_mono ),
.hcnt (hcnt_mono ),
.vs (vs_mono ),
.hs (hs_mono ),
.vmax (vmax_mono ),
.hmax (hmax_mono )
);
// instance of video timing module for pal@56Hz, 32kHz
wire [9:0] vcnt_pal56, hcnt_pal56;
wire hs_pal56, vs_pal56, hmax_pal56, vmax_pal56, bd_pal56;
timing #(10'd120, 10'd40, 10'd200, 10'd100, 10'd3, 10'd66) timing_pal56 (
.clk (clk ),
.reset (reset ),
.border (bd_pal56 ),
.vcnt (vcnt_pal56 ),
.hcnt (hcnt_pal56 ),
.vs (vs_pal56 ),
.hs (hs_pal56 ),
.vmax (vmax_pal56 ),
.hmax (hmax_pal56 )
);
// instance of video timing module for pal@50Hz, 32kHz
wire [9:0] vcnt_pal50, hcnt_pal50;
wire hs_pal50, vs_pal50, hmax_pal50, vmax_pal50, bd_pal50;
timing #(10'd128, 10'd40, 10'd192, 10'd117, 10'd3, 10'd117) timing_pal50 (
.clk (clk ),
.reset (reset ),
.border (bd_pal50 ),
.vcnt (vcnt_pal50 ),
.hcnt (hcnt_pal50 ),
.vs (vs_pal50 ),
.hs (hs_pal50 ),
.vmax (vmax_pal50 ),
.hmax (hmax_pal50 )
);
// instance of video timing module for ntsc@60Hz, 32kHz
wire [9:0] vcnt_ntsc, hcnt_ntsc;
wire hs_ntsc, vs_ntsc, hmax_ntsc, vmax_ntsc, bd_ntsc;
timing #(10'd160, 10'd40, 10'd160, 10'd64, 10'd3, 10'd64) timing_ntsc (
.clk (clk ),
.reset (reset ),
.border (bd_ntsc ),
.vcnt (vcnt_ntsc ),
.hcnt (hcnt_ntsc ),
.vs (vs_ntsc ),
.hs (hs_ntsc ),
.vmax (vmax_ntsc ),
.hmax (hmax_ntsc )
);
// ----------- de-multiplex video timing signals ------------
// de-multiplex pal50(50hz)/pal56(56hz) timing
wire [9:0] hcnt_pal = pal56?hcnt_pal56:hcnt_pal50;
wire [9:0] vcnt_pal = pal56?vcnt_pal56:vcnt_pal50;
wire bd_pal = pal56?bd_pal56:bd_pal50;
wire hs_pal = pal56?hs_pal56:hs_pal50;
wire vs_pal = pal56?vs_pal56:vs_pal50;
wire hmax_pal = pal56?hmax_pal56:hmax_pal50;
wire vmax_pal = pal56?vmax_pal56:vmax_pal50;
// de-multiplex pal(50hz/56hz)/ntsc(60hz) timing
wire [9:0] hcnt_color = pal?hcnt_pal:hcnt_ntsc;
wire [9:0] vcnt_color = pal?vcnt_pal:vcnt_ntsc;
wire bd_color = pal?bd_pal:bd_ntsc;
wire hs_color = pal?hs_pal:hs_ntsc;
wire vs_color = pal?vs_pal:vs_ntsc;
wire hmax_color = pal?hmax_pal:hmax_ntsc;
wire vmax_color = pal?vmax_pal:vmax_ntsc;
// de-multiplex mono(72hz)/color(50hz/56hz/60hz) timing
wire [9:0] hcnt = mono?hcnt_mono:hcnt_color;
wire [9:0] vcnt = mono?vcnt_mono:vcnt_color;
wire bd = mono?1'b0:bd_color;
// monochome is 640x480 (hs & vs neg)
// color is 800x600 (hs & vs pos)
assign hs = mono?~hs_mono:hs_color;
assign vs = mono?~vs_mono:vs_color;
wire hmax = mono?hmax_mono:hmax_color;
wire vmax = mono?vmax_mono:vmax_color;
reg [15:0] tx, tx0, tx1, tx2, tx3; // output shift registers
localparam BASE_ADDR = 23'h8000; // default video base address 0x010000
reg [22:0] _v_bas_ad; // video base address register
reg [1:0] shmode;
wire mono = (shmode == 2'd2);
wire low = (shmode == 2'd0);
reg [1:0] syncmode;
wire pal = (syncmode[1] == 1'b1);
// dtack
assign reg_dtack = reg_sel;
// 16 colors with 3*3 bits each
reg [2:0] palette_r[15:0];
reg [2:0] palette_g[15:0];
reg [2:0] palette_b[15:0];
always @(reg_sel, reg_rw, reg_uds, reg_lds, reg_addr, _v_bas_ad, shmode, vaddr) begin
reg_dout = { 16'h0000 };
// read registers
if(reg_sel && reg_rw) begin
if(reg_addr == 8'h01 && ~reg_lds)
reg_dout = { 8'h00, _v_bas_ad[22:15]};
if(reg_addr == 8'h03 && ~reg_lds)
reg_dout = { 8'h00, _v_bas_ad[14:7]};
if(reg_addr == 8'h05 && ~reg_lds)
reg_dout = { 8'h00, vaddr[22:15]};
if(reg_addr == 8'h07 && ~reg_lds)
reg_dout = { 8'h00, vaddr[14:7]};
if(reg_addr == 8'h09 && ~reg_lds)
reg_dout = { 8'h00, vaddr[6:0], 1'b0 };
if(reg_addr == 8'h0a && ~reg_uds)
reg_dout = { 6'h00, syncmode, 8'h00};
// the color palette registers
if(reg_addr >= 8'h40 && reg_addr < 8'h60 ) begin
reg_dout[2:0] = palette_b[reg_addr[4:1]];
reg_dout[6:4] = palette_g[reg_addr[4:1]];
reg_dout[10:8] = palette_r[reg_addr[4:1]];
end
if(reg_addr == 8'h60 && ~reg_uds)
reg_dout = { 6'h00, shmode, 8'h00};
end
end
always @(negedge reg_clk) begin
if(reg_reset) begin
_v_bas_ad <= BASE_ADDR;
shmode <= DEFAULT_MODE; // default video mode 2 => mono
syncmode <= 2'b00; // 60hz
if(DEFAULT_MODE == 0) begin
// TOS default palette, can be disabled after tests
palette_r[ 0] <= 3'b111; palette_g[ 0] <= 3'b111; palette_b[ 0] <= 3'b111;
palette_r[ 1] <= 3'b111; palette_g[ 1] <= 3'b000; palette_b[ 1] <= 3'b000;
palette_r[ 2] <= 3'b000; palette_g[ 2] <= 3'b111; palette_b[ 2] <= 3'b000;
palette_r[ 3] <= 3'b111; palette_g[ 3] <= 3'b111; palette_b[ 3] <= 3'b000;
palette_r[ 4] <= 3'b000; palette_g[ 4] <= 3'b000; palette_b[ 4] <= 3'b111;
palette_r[ 5] <= 3'b111; palette_g[ 5] <= 3'b000; palette_b[ 5] <= 3'b111;
palette_r[ 6] <= 3'b000; palette_g[ 6] <= 3'b111; palette_b[ 6] <= 3'b111;
palette_r[ 7] <= 3'b101; palette_g[ 7] <= 3'b101; palette_b[ 7] <= 3'b101;
palette_r[ 8] <= 3'b011; palette_g[ 8] <= 3'b011; palette_b[ 8] <= 3'b011;
palette_r[ 9] <= 3'b111; palette_g[ 9] <= 3'b011; palette_b[ 9] <= 3'b011;
palette_r[10] <= 3'b011; palette_g[10] <= 3'b111; palette_b[10] <= 3'b011;
palette_r[11] <= 3'b111; palette_g[11] <= 3'b111; palette_b[11] <= 3'b011;
palette_r[12] <= 3'b011; palette_g[12] <= 3'b011; palette_b[12] <= 3'b111;
palette_r[13] <= 3'b111; palette_g[13] <= 3'b011; palette_b[13] <= 3'b111;
palette_r[14] <= 3'b011; palette_g[14] <= 3'b111; palette_b[14] <= 3'b111;
palette_r[15] <= 3'b000; palette_g[15] <= 3'b000; palette_b[15] <= 3'b000;
end else
palette_b[ 0] <= 3'b111;
end else begin
// write registers
if(reg_sel && ~reg_rw) begin
if(reg_addr == 8'h01 && ~reg_lds)
_v_bas_ad[22:15] <= reg_din[7:0];
if(reg_addr == 8'h03 && ~reg_lds)
_v_bas_ad[14:7] <= reg_din[7:0];
if(reg_addr == 8'h0a && ~reg_uds)
syncmode <= reg_din[9:8];
// the color palette registers
if(reg_addr >= 8'h40 && reg_addr < 8'h60 ) begin
if(~reg_uds) begin
palette_r[reg_addr[4:1]] <= reg_din[10:8];
end
if(~reg_lds) begin
palette_g[reg_addr[4:1]] <= reg_din[6:4];
palette_b[reg_addr[4:1]] <= reg_din[2:0];
end
end
if(reg_addr == 8'h60 && ~reg_uds)
shmode <= reg_din[9:8];
end
end
end
// ------------ monochrome video signal ----------------
wire [2:0] blue0 = palette_b[0];
wire mono_bit = blue0[0]?~tx[15]:tx[15];
wire [2:0] mono_rgb = de?{mono_bit, mono_bit, mono_bit}:3'b000;
// --------------- colour video signal ------------------
// border color is taken from palette[0]
wire [3:0] index16 = { tx3[15], tx2[15], tx1[15], tx0[15] };
wire [2:0] color_r = de?palette_r[index16]:(bd?palette_r[0]:3'b000);
wire [2:0] color_g = de?palette_g[index16]:(bd?palette_g[0]:3'b000);
wire [2:0] color_b = de?palette_b[index16]:(bd?palette_b[0]:3'b000);
// de-multiplex color and mono into one vga signal ...
wire [2:0] stvid_r = mono?mono_rgb:color_r;
wire [2:0] stvid_g = mono?mono_rgb:color_g;
wire [2:0] stvid_b = mono?mono_rgb:color_b;
// ... add OSD overlay and feed into VGA outputs
assign video_r = !osd_oe?{stvid_r,stvid_r}:{osd_pixel, osd_pixel, osd_pixel, stvid_r};
assign video_g = !osd_oe?{stvid_g,stvid_g}:{osd_pixel, osd_pixel, 1'b1, stvid_g};
assign video_b = !osd_oe?{stvid_b,stvid_b}:{osd_pixel, osd_pixel, osd_pixel, stvid_b};
// display enable signal
// the color modes use a scan doubler and output the data with 2 lines delay
wire [9:0] v_offset = mono?10'd0:10'd2;
wire de = (hcnt >= H_PRE) && (hcnt < H_ACT+H_PRE) && (vcnt >= v_offset && vcnt < V_ACT+v_offset);
// a fake de signal for timer a for color modes with half the hsync frequency
wire deC = (((hcnt >= H_PRE) && !vcnt[0]) || ((hcnt < H_ACT+H_PRE) && vcnt[0])) &&
(vcnt >= (v_offset-10'd0) && vcnt < (V_ACT+v_offset-10'd0));
// a fake hsync pulse for the scan doubled color modes
wire hsC = vcnt[0] && hs;
// create a read signal that's 16 clocks ahead of oe
assign read = (bus_cycle[3:2] == 0) && (hcnt < H_ACT) && (vcnt < V_ACT);
always @(posedge clk) begin
if(reset) begin
vaddr <= _v_bas_ad;
end else begin
// ---- scan doubler pointer handling -----
if(hmax) begin
// reset counters at and of each line
sd_rptr <= 7'd0;
if(vcnt[0])
sd_wptr <= 7'd0;
end
// ------------ memory fetch --------------
if(read) begin
if(bus_cycle == 3) begin
// 16bit buffer for direct mono generation
dataR <= data;
// two line buffer for scan doubling
sd_buffer[{!vcnt[1], sd_wptr}] <= data;
// increase scan doubler address
sd_wptr <= sd_wptr + 7'd1;
// increase video address to next word
vaddr <= vaddr + 23'd1;
end
end else begin
// reached last possible pixel pos
if(hmax && vmax) begin
// reset video address counter
vaddr <= _v_bas_ad;
end
end
// ------------ screen output ----------------
// hires mode: reload shift register every 16 clocks
if(hcnt[3:0] == 4'b1111)
tx <= dataR;
else
tx[15:1] <= tx[14:0];
// double buffered color mode: reload every 32 clocks
// low rez 320x200
if(low) begin
if((hcnt < H_ACT) && (hcnt[4:0] == 5'b01110)) begin
// read words for all four planes
tx0 <= sd_buffer[{vcnt[1], sd_rptr+7'd0}];
tx1 <= sd_buffer[{vcnt[1], sd_rptr+7'd1}];
tx2 <= sd_buffer[{vcnt[1], sd_rptr+7'd2}];
tx3 <= sd_buffer[{vcnt[1], sd_rptr+7'd3}];
sd_rptr <= sd_rptr + 7'd4;
end else if(hcnt[0] == 1'b0) begin
// shift every second pixel
tx0[15:1] <= tx0[14:0];
tx1[15:1] <= tx1[14:0];
tx2[15:1] <= tx2[14:0];
tx3[15:1] <= tx3[14:0];
end
end else begin
// med rez 640x200
if((hcnt < H_ACT) && (hcnt[3:0] == 4'b1111)) begin
// read words for all four planes
tx0 <= sd_buffer[{vcnt[1], sd_rptr+7'd0}];
tx1 <= sd_buffer[{vcnt[1], sd_rptr+7'd1}];
sd_rptr <= sd_rptr + 7'd2;
end else begin
// shift every pixel
tx0[15:1] <= tx0[14:0];
tx1[15:1] <= tx1[14:0];
tx2[15:1] <= 15'h0000;
tx3[15:1] <= 15'h0000;
end
end
end
end
// ----------------------------------- OSD -----------------------------------
// this core supports only the display related OSD commands
// of the minimig
reg [7:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [10:0] bcnt;
// the OSD has its own SPI interface to the io controller
always@(posedge sck, posedge ss) begin
if(ss == 1'b1) begin
cnt <= 5'd0;
bcnt <= 11'd0;
end else begin
sbuf <= { sbuf[6:0], sdi};
// 0:7 is command, rest payload
if(cnt < 15)
cnt <= cnt + 4'd1;
else
cnt <= 4'd8;
if(cnt == 7) begin
cmd <= {sbuf[6:0], sdi};
// lower three command bits are line address
bcnt <= { sbuf[1:0], sdi, 8'h00};
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(sbuf[6:3] == 4'b0100)
osd_enable <= sdi;
end
// command 0x20: OSDCMDWRITE
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
osd_buffer[bcnt] <= {sbuf[6:0], sdi};
bcnt <= bcnt + 11'd1;
end
end
end
// output to video controller
wire osd_oe; // the current pixel overwritten by the OSD
// input from video controller
// vcnt (0..399) / hcnt (0..639)
reg osd_enable;
reg [7:0] osd_buffer [2047:0]; // the OSD buffer itself
localparam OSD_WIDTH = 10'd256;
localparam OSD_HEIGHT = 10'd128; // pixels are doubled vertically
localparam OSD_POS_X = (H_ACT-OSD_WIDTH)>>1;
localparam OSD_POS_Y = (V_ACT-OSD_HEIGHT)>>1;
assign osd_oe = osd_enable && (
(hcnt >= OSD_POS_X) &&
(hcnt < (OSD_POS_X + OSD_WIDTH)) &&
(vcnt >= OSD_POS_Y) &&
(vcnt < (OSD_POS_Y + OSD_HEIGHT)));
wire [7:0] osd_hcnt = hcnt - OSD_POS_X + 7'd1; // one pixel offset for osd_byte register
wire [6:0] osd_vcnt = vcnt - OSD_POS_Y;
wire osd_pixel = osd_byte[osd_vcnt[3:1]];
reg [7:0] osd_byte;
always @(posedge clk)
osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt}];
endmodule
// generic video timing generator
module timing (
input clk, // 31.875 MHz pixel clock
input reset,
output border, // border (incl active area)
output reg [9:0] vcnt, // vertical pixel counter
output reg [9:0] hcnt, // horizontal pixel counter
output vs, // vertical sync signal
output hs, // horizontal sync signal
output vmax, // max vertical pixel position reached
output hmax // max horizontal pixel position reached
);
localparam H_PRE = 10'd16;
localparam H_ACT = 10'd640;
localparam V_ACT = 10'd400;
// default: VESA 640x480x72 timing (2*40 blank lines added)
// VESA == 31.5 MHz, Atari ST == 32 Mhz, MIST == 31.875MHz
parameter H_FP = 10'd24;
parameter H_S = 10'd40;
parameter H_BP = 10'd128;
localparam H_TOT = H_ACT + H_FP + H_S + H_BP;
parameter V_FP = 10'd55;
parameter V_S = 10'd3;
parameter V_BP = 10'd73;
localparam V_TOT = V_ACT + V_FP + V_S + V_BP;
// generate sync pulses
assign hs = (hcnt >= (H_ACT+H_FP+H_PRE)) && (hcnt < (H_ACT+H_FP+H_S+H_PRE));
assign vs = (vcnt >= (V_ACT+V_FP)) && (vcnt < (V_ACT+V_FP+V_S));
// max is not really the max possible position but something "far" behind the
// visible area to allow for counter resets etc
assign hmax = (hcnt == H_ACT + H_FP + H_PRE);
assign vmax = (vcnt == V_ACT + V_FP);
localparam H_BORDER = 10'd40;
localparam V_BORDER = 10'd40;
// the following only works if H_BORDER > H_PRE
wire rborder = (hcnt < H_ACT+H_PRE+H_BORDER) && ((vcnt < V_ACT+V_BORDER) || (vcnt >= V_TOT-V_BORDER));
wire lborder = (hcnt >= H_TOT-H_BORDER+H_PRE) && ((vcnt < V_ACT+V_BORDER-1) || (vcnt >= V_TOT-V_BORDER-1));
assign border = lborder || rborder;
always @(posedge clk) begin
// ------------ video counters --------------
if(reset) begin
// using reset here is important to make sure video counters
// run synchronous to bus state machine
hcnt <= 10'd0;
vcnt <= 10'd0;
end else begin
// horizontal video counter
if(hcnt < H_TOT - 10'd1)
hcnt <= hcnt + 10'd1;
else begin
hcnt <= 10'd0;
// vertical video counter
if(vcnt < V_TOT - 10'd1)
vcnt <= vcnt + 10'd1;
else begin
vcnt <= 10'd0;
end
end
end
end
endmodule

540
cores/mist/vol_table_array.vhd Normal file
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@@ -0,0 +1,540 @@
-- generated with tablegen by MikeJ
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vol_table is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(9 downto 0)
);
end;
architecture RTL of vol_table is
type ROM_ARRAY is array(0 to 4095) of std_logic_vector(11 downto 0);
constant ROM : ROM_ARRAY := (
x"000",x"002",x"004",x"006",x"009",x"00D",x"014",x"01B", -- 0x0000
x"027",x"036",x"050",x"06D",x"0A5",x"0EB",x"17D",x"24D", -- 0x0008
x"002",x"005",x"007",x"009",x"00D",x"010",x"016",x"01D", -- 0x0010
x"02A",x"038",x"051",x"06F",x"0A7",x"0ED",x"17E",x"24D", -- 0x0018
x"004",x"007",x"009",x"00B",x"00E",x"012",x"018",x"020", -- 0x0020
x"02B",x"03A",x"054",x"071",x"0A9",x"0EF",x"17E",x"24D", -- 0x0028
x"006",x"009",x"00B",x"00D",x"011",x"014",x"01A",x"021", -- 0x0030
x"02E",x"03C",x"055",x"073",x"0AB",x"0F0",x"17F",x"24D", -- 0x0038
x"009",x"00D",x"00E",x"011",x"014",x"018",x"01D",x"024", -- 0x0040
x"031",x"03F",x"058",x"076",x"0AD",x"0F3",x"180",x"24D", -- 0x0048
x"00D",x"010",x"012",x"014",x"018",x"01B",x"021",x"028", -- 0x0050
x"035",x"042",x"05C",x"079",x"0B0",x"0F5",x"182",x"24D", -- 0x0058
x"014",x"016",x"018",x"01A",x"01D",x"021",x"027",x"02F", -- 0x0060
x"03A",x"049",x"062",x"07E",x"0B5",x"0FA",x"184",x"24D", -- 0x0068
x"01B",x"01D",x"020",x"021",x"024",x"028",x"02F",x"035", -- 0x0070
x"042",x"050",x"068",x"085",x"0BB",x"0FE",x"188",x"24D", -- 0x0078
x"027",x"02A",x"02B",x"02E",x"031",x"035",x"03A",x"042", -- 0x0080
x"04D",x"05C",x"073",x"091",x"0C5",x"108",x"18E",x"24D", -- 0x0088
x"036",x"038",x"03A",x"03C",x"03F",x"042",x"049",x"050", -- 0x0090
x"05C",x"06A",x"082",x"09D",x"0D2",x"114",x"19A",x"24D", -- 0x0098
x"050",x"051",x"054",x"055",x"058",x"05C",x"062",x"068", -- 0x00A0
x"073",x"082",x"098",x"0B4",x"0E7",x"128",x"1AB",x"254", -- 0x00A8
x"06D",x"06F",x"071",x"073",x"076",x"079",x"07E",x"085", -- 0x00B0
x"091",x"09D",x"0B4",x"0D0",x"102",x"142",x"1C1",x"264", -- 0x00B8
x"0A5",x"0A7",x"0A9",x"0AB",x"0AD",x"0B0",x"0B5",x"0BB", -- 0x00C0
x"0C5",x"0D2",x"0E7",x"102",x"133",x"172",x"1ED",x"27C", -- 0x00C8
x"0EB",x"0ED",x"0EF",x"0F0",x"0F3",x"0F5",x"0FA",x"0FE", -- 0x00D0
x"108",x"114",x"128",x"142",x"172",x"1AF",x"21D",x"2AB", -- 0x00D8
x"17D",x"17E",x"17E",x"17F",x"180",x"182",x"184",x"188", -- 0x00E0
x"18E",x"19A",x"1AB",x"1C1",x"1ED",x"21D",x"284",x"30A", -- 0x00E8
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x00F0
x"24D",x"24D",x"254",x"264",x"27C",x"2AB",x"30A",x"379", -- 0x00F8
x"002",x"005",x"006",x"009",x"00C",x"010",x"016",x"01D", -- 0x0100
x"02A",x"038",x"052",x"06F",x"0A7",x"0ED",x"17E",x"24E", -- 0x0108
x"005",x"007",x"009",x"00B",x"00F",x"012",x"018",x"01F", -- 0x0110
x"02C",x"03A",x"053",x"071",x"0A9",x"0EF",x"17F",x"24E", -- 0x0118
x"006",x"009",x"00B",x"00D",x"011",x"014",x"01B",x"022", -- 0x0120
x"02E",x"03D",x"056",x"073",x"0AB",x"0F0",x"180",x"24E", -- 0x0128
x"009",x"00B",x"00D",x"010",x"013",x"016",x"01C",x"023", -- 0x0130
x"030",x"03E",x"057",x"075",x"0AD",x"0F2",x"181",x"24E", -- 0x0138
x"00C",x"00F",x"011",x"013",x"016",x"01A",x"01F",x"027", -- 0x0140
x"033",x"041",x"05B",x"078",x"0AF",x"0F4",x"181",x"24E", -- 0x0148
x"010",x"012",x"014",x"016",x"01A",x"01D",x"023",x"02A", -- 0x0150
x"037",x"044",x"05E",x"07B",x"0B2",x"0F7",x"183",x"24E", -- 0x0158
x"016",x"018",x"01B",x"01C",x"01F",x"023",x"02A",x"031", -- 0x0160
x"03D",x"04B",x"064",x"080",x"0B7",x"0FB",x"185",x"24E", -- 0x0168
x"01D",x"01F",x"022",x"023",x"027",x"02A",x"031",x"037", -- 0x0170
x"044",x"052",x"06A",x"087",x"0BD",x"100",x"189",x"24E", -- 0x0178
x"02A",x"02C",x"02E",x"030",x"033",x"037",x"03D",x"044", -- 0x0180
x"04F",x"05E",x"075",x"092",x"0C7",x"10A",x"190",x"24E", -- 0x0188
x"038",x"03A",x"03D",x"03E",x"041",x"044",x"04B",x"052", -- 0x0190
x"05E",x"06C",x"083",x"09F",x"0D4",x"115",x"19B",x"24E", -- 0x0198
x"052",x"053",x"056",x"057",x"05B",x"05E",x"064",x"06A", -- 0x01A0
x"075",x"083",x"09A",x"0B6",x"0E9",x"12A",x"1AD",x"256", -- 0x01A8
x"06F",x"071",x"073",x"075",x"078",x"07B",x"080",x"087", -- 0x01B0
x"092",x"09F",x"0B6",x"0D1",x"104",x"143",x"1C2",x"265", -- 0x01B8
x"0A7",x"0A9",x"0AB",x"0AD",x"0AF",x"0B2",x"0B7",x"0BD", -- 0x01C0
x"0C7",x"0D4",x"0E9",x"104",x"135",x"174",x"1EE",x"27D", -- 0x01C8
x"0ED",x"0EF",x"0F0",x"0F2",x"0F4",x"0F7",x"0FB",x"100", -- 0x01D0
x"10A",x"115",x"12A",x"143",x"174",x"1B0",x"21E",x"2AC", -- 0x01D8
x"17E",x"17F",x"180",x"181",x"181",x"183",x"185",x"189", -- 0x01E0
x"190",x"19B",x"1AD",x"1C2",x"1EE",x"21E",x"285",x"30B", -- 0x01E8
x"24E",x"24E",x"24E",x"24E",x"24E",x"24E",x"24E",x"24E", -- 0x01F0
x"24E",x"24E",x"256",x"265",x"27D",x"2AC",x"30B",x"379", -- 0x01F8
x"004",x"006",x"008",x"00A",x"00D",x"011",x"018",x"01F", -- 0x0200
x"02B",x"039",x"053",x"070",x"0A8",x"0EE",x"17F",x"24F", -- 0x0208
x"006",x"009",x"00B",x"00D",x"011",x"014",x"01A",x"021", -- 0x0210
x"02E",x"03C",x"055",x"073",x"0AB",x"0F0",x"180",x"24F", -- 0x0218
x"008",x"00B",x"00D",x"00F",x"012",x"016",x"01C",x"023", -- 0x0220
x"02F",x"03E",x"057",x"074",x"0AC",x"0F2",x"181",x"24F", -- 0x0228
x"00A",x"00D",x"00F",x"011",x"014",x"018",x"01E",x"025", -- 0x0230
x"031",x"040",x"059",x"077",x"0AE",x"0F3",x"182",x"24F", -- 0x0238
x"00D",x"011",x"012",x"014",x"018",x"01B",x"021",x"028", -- 0x0240
x"035",x"043",x"05C",x"079",x"0B0",x"0F5",x"183",x"24F", -- 0x0248
x"011",x"014",x"016",x"018",x"01B",x"01F",x"025",x"02C", -- 0x0250
x"039",x"046",x"05F",x"07C",x"0B3",x"0F8",x"184",x"24F", -- 0x0258
x"018",x"01A",x"01C",x"01E",x"021",x"025",x"02B",x"032", -- 0x0260
x"03E",x"04C",x"065",x"082",x"0B8",x"0FD",x"186",x"24F", -- 0x0268
x"01F",x"021",x"023",x"025",x"028",x"02C",x"032",x"039", -- 0x0270
x"045",x"053",x"06C",x"088",x"0BE",x"101",x"18A",x"24F", -- 0x0278
x"02B",x"02E",x"02F",x"031",x"035",x"039",x"03E",x"045", -- 0x0280
x"051",x"05F",x"077",x"094",x"0C8",x"10B",x"191",x"24F", -- 0x0288
x"039",x"03C",x"03E",x"040",x"043",x"046",x"04C",x"053", -- 0x0290
x"05F",x"06D",x"085",x"0A0",x"0D5",x"116",x"19C",x"24F", -- 0x0298
x"053",x"055",x"057",x"059",x"05C",x"05F",x"065",x"06C", -- 0x02A0
x"077",x"085",x"09B",x"0B7",x"0EA",x"12B",x"1AE",x"256", -- 0x02A8
x"070",x"073",x"074",x"077",x"079",x"07C",x"082",x"088", -- 0x02B0
x"094",x"0A0",x"0B7",x"0D3",x"105",x"144",x"1C3",x"266", -- 0x02B8
x"0A8",x"0AB",x"0AC",x"0AE",x"0B0",x"0B3",x"0B8",x"0BE", -- 0x02C0
x"0C8",x"0D5",x"0EA",x"105",x"136",x"175",x"1EF",x"27E", -- 0x02C8
x"0EE",x"0F0",x"0F2",x"0F3",x"0F5",x"0F8",x"0FC",x"101", -- 0x02D0
x"10B",x"116",x"12B",x"144",x"175",x"1B1",x"21F",x"2AD", -- 0x02D8
x"17F",x"180",x"181",x"182",x"183",x"184",x"186",x"18A", -- 0x02E0
x"191",x"19C",x"1AE",x"1C3",x"1EF",x"21F",x"285",x"30B", -- 0x02E8
x"24E",x"24E",x"24E",x"24E",x"24E",x"24E",x"24E",x"24E", -- 0x02F0
x"24E",x"24E",x"256",x"266",x"27E",x"2AD",x"30B",x"37A", -- 0x02F8
x"006",x"009",x"00A",x"00D",x"010",x"014",x"01A",x"021", -- 0x0300
x"02D",x"03B",x"055",x"072",x"0AA",x"0F0",x"181",x"250", -- 0x0308
x"009",x"00B",x"00D",x"00F",x"013",x"016",x"01C",x"023", -- 0x0310
x"030",x"03E",x"057",x"075",x"0AD",x"0F2",x"182",x"250", -- 0x0318
x"00A",x"00D",x"00F",x"011",x"014",x"018",x"01F",x"026", -- 0x0320
x"031",x"040",x"059",x"076",x"0AE",x"0F3",x"183",x"250", -- 0x0328
x"00D",x"00F",x"011",x"014",x"017",x"01A",x"020",x"027", -- 0x0330
x"034",x"042",x"05B",x"079",x"0B0",x"0F5",x"183",x"250", -- 0x0338
x"010",x"013",x"014",x"017",x"01A",x"01E",x"023",x"02A", -- 0x0340
x"037",x"045",x"05E",x"07B",x"0B2",x"0F7",x"184",x"250", -- 0x0348
x"014",x"016",x"018",x"01A",x"01E",x"021",x"027",x"02E", -- 0x0350
x"03B",x"048",x"061",x"07E",x"0B5",x"0FA",x"186",x"250", -- 0x0358
x"01A",x"01C",x"01F",x"020",x"023",x"027",x"02D",x"034", -- 0x0360
x"040",x"04E",x"067",x"084",x"0BA",x"0FE",x"188",x"250", -- 0x0368
x"021",x"023",x"026",x"027",x"02A",x"02E",x"034",x"03B", -- 0x0370
x"047",x"055",x"06E",x"08A",x"0C0",x"103",x"18C",x"250", -- 0x0378
x"02D",x"030",x"031",x"034",x"037",x"03B",x"040",x"047", -- 0x0380
x"053",x"061",x"079",x"096",x"0CA",x"10C",x"192",x"250", -- 0x0388
x"03B",x"03E",x"040",x"042",x"045",x"048",x"04E",x"055", -- 0x0390
x"061",x"06F",x"087",x"0A2",x"0D7",x"118",x"19E",x"250", -- 0x0398
x"055",x"057",x"059",x"05B",x"05E",x"061",x"067",x"06E", -- 0x03A0
x"079",x"087",x"09D",x"0B9",x"0EC",x"12C",x"1AF",x"258", -- 0x03A8
x"072",x"075",x"076",x"079",x"07B",x"07E",x"084",x"08A", -- 0x03B0
x"096",x"0A2",x"0B9",x"0D4",x"106",x"145",x"1C4",x"267", -- 0x03B8
x"0AA",x"0AD",x"0AE",x"0B0",x"0B2",x"0B5",x"0BA",x"0C0", -- 0x03C0
x"0CA",x"0D7",x"0EC",x"106",x"137",x"176",x"1F0",x"27F", -- 0x03C8
x"0F0",x"0F2",x"0F3",x"0F5",x"0F7",x"0FA",x"0FE",x"103", -- 0x03D0
x"10C",x"118",x"12C",x"145",x"176",x"1B2",x"220",x"2AE", -- 0x03D8
x"181",x"182",x"183",x"183",x"184",x"186",x"188",x"18C", -- 0x03E0
x"192",x"19E",x"1AF",x"1C4",x"1F0",x"220",x"286",x"30C", -- 0x03E8
x"250",x"250",x"250",x"250",x"250",x"250",x"250",x"250", -- 0x03F0
x"250",x"250",x"257",x"267",x"27F",x"2AE",x"30C",x"37A", -- 0x03F8
x"009",x"00C",x"00D",x"010",x"013",x"017",x"01D",x"024", -- 0x0400
x"030",x"03E",x"058",x"075",x"0AD",x"0F3",x"183",x"251", -- 0x0408
x"00C",x"00E",x"010",x"012",x"016",x"019",x"01F",x"026", -- 0x0410
x"033",x"041",x"05A",x"077",x"0AF",x"0F4",x"184",x"251", -- 0x0418
x"00D",x"010",x"012",x"014",x"017",x"01B",x"022",x"029", -- 0x0420
x"034",x"043",x"05C",x"079",x"0B1",x"0F6",x"185",x"251", -- 0x0428
x"010",x"012",x"014",x"017",x"01A",x"01D",x"023",x"02A", -- 0x0430
x"037",x"045",x"05E",x"07B",x"0B2",x"0F7",x"185",x"251", -- 0x0438
x"013",x"016",x"017",x"01A",x"01D",x"021",x"026",x"02D", -- 0x0440
x"03A",x"048",x"061",x"07E",x"0B4",x"0FA",x"186",x"251", -- 0x0448
x"017",x"019",x"01B",x"01D",x"021",x"024",x"02A",x"031", -- 0x0450
x"03E",x"04B",x"064",x"081",x"0B8",x"0FC",x"188",x"251", -- 0x0458
x"01D",x"01F",x"022",x"023",x"026",x"02A",x"030",x"037", -- 0x0460
x"043",x"051",x"06A",x"086",x"0BC",x"101",x"18A",x"251", -- 0x0468
x"024",x"026",x"029",x"02A",x"02D",x"031",x"037",x"03E", -- 0x0470
x"04A",x"058",x"070",x"08C",x"0C2",x"105",x"18E",x"251", -- 0x0478
x"030",x"033",x"034",x"037",x"03A",x"03E",x"043",x"04A", -- 0x0480
x"056",x"064",x"07B",x"098",x"0CD",x"10F",x"194",x"251", -- 0x0488
x"03E",x"041",x"043",x"045",x"048",x"04B",x"051",x"058", -- 0x0490
x"064",x"072",x"089",x"0A4",x"0D9",x"11A",x"1A0",x"251", -- 0x0498
x"058",x"05A",x"05C",x"05E",x"061",x"064",x"06A",x"070", -- 0x04A0
x"07B",x"089",x"0A0",x"0BB",x"0EE",x"12E",x"1B1",x"259", -- 0x04A8
x"075",x"077",x"079",x"07B",x"07E",x"081",x"086",x"08C", -- 0x04B0
x"098",x"0A4",x"0BB",x"0D6",x"109",x"147",x"1C6",x"269", -- 0x04B8
x"0AD",x"0AF",x"0B1",x"0B2",x"0B4",x"0B8",x"0BC",x"0C2", -- 0x04C0
x"0CD",x"0D9",x"0EE",x"109",x"139",x"178",x"1F2",x"280", -- 0x04C8
x"0F3",x"0F4",x"0F6",x"0F7",x"0FA",x"0FC",x"101",x"105", -- 0x04D0
x"10E",x"11A",x"12E",x"147",x"178",x"1B3",x"221",x"2AF", -- 0x04D8
x"183",x"184",x"185",x"185",x"186",x"188",x"18A",x"18E", -- 0x04E0
x"194",x"1A0",x"1B1",x"1C6",x"1F1",x"221",x"287",x"30D", -- 0x04E8
x"251",x"251",x"251",x"251",x"251",x"251",x"251",x"251", -- 0x04F0
x"251",x"251",x"259",x"269",x"280",x"2AF",x"30D",x"37B", -- 0x04F8
x"00D",x"010",x"011",x"014",x"017",x"01B",x"021",x"028", -- 0x0500
x"034",x"042",x"05C",x"078",x"0B0",x"0F6",x"186",x"254", -- 0x0508
x"010",x"012",x"014",x"016",x"01A",x"01D",x"023",x"02A", -- 0x0510
x"036",x"044",x"05D",x"07B",x"0B2",x"0F7",x"187",x"254", -- 0x0518
x"011",x"014",x"016",x"018",x"01B",x"01F",x"025",x"02C", -- 0x0520
x"038",x"047",x"05F",x"07C",x"0B4",x"0F9",x"187",x"254", -- 0x0528
x"014",x"016",x"018",x"01B",x"01E",x"021",x"027",x"02E", -- 0x0530
x"03A",x"048",x"061",x"07F",x"0B5",x"0FA",x"188",x"254", -- 0x0538
x"017",x"01A",x"01B",x"01E",x"021",x"025",x"02A",x"031", -- 0x0540
x"03D",x"04B",x"064",x"081",x"0B8",x"0FD",x"189",x"254", -- 0x0548
x"01B",x"01D",x"01F",x"021",x"025",x"028",x"02E",x"035", -- 0x0550
x"041",x"04E",x"067",x"084",x"0BB",x"0FF",x"18A",x"254", -- 0x0558
x"021",x"023",x"025",x"027",x"02A",x"02E",x"034",x"03B", -- 0x0560
x"047",x"055",x"06D",x"089",x"0BF",x"104",x"18D",x"254", -- 0x0568
x"028",x"02A",x"02C",x"02E",x"031",x"035",x"03B",x"041", -- 0x0570
x"04E",x"05B",x"074",x"090",x"0C6",x"108",x"191",x"254", -- 0x0578
x"034",x"036",x"038",x"03A",x"03D",x"041",x"047",x"04E", -- 0x0580
x"059",x"067",x"07E",x"09B",x"0D0",x"112",x"197",x"254", -- 0x0588
x"042",x"044",x"047",x"048",x"04B",x"04E",x"055",x"05B", -- 0x0590
x"067",x"075",x"08C",x"0A8",x"0DC",x"11D",x"1A2",x"254", -- 0x0598
x"05C",x"05D",x"05F",x"061",x"064",x"067",x"06D",x"074", -- 0x05A0
x"07E",x"08C",x"0A3",x"0BE",x"0F1",x"131",x"1B3",x"25B", -- 0x05A8
x"078",x"07B",x"07C",x"07F",x"081",x"084",x"089",x"090", -- 0x05B0
x"09B",x"0A8",x"0BE",x"0D9",x"10B",x"14A",x"1C8",x"26B", -- 0x05B8
x"0B0",x"0B2",x"0B4",x"0B5",x"0B8",x"0BB",x"0BF",x"0C6", -- 0x05C0
x"0D0",x"0DC",x"0F1",x"10B",x"13C",x"17A",x"1F4",x"282", -- 0x05C8
x"0F6",x"0F7",x"0F9",x"0FA",x"0FD",x"0FF",x"103",x"108", -- 0x05D0
x"111",x"11D",x"131",x"14A",x"17A",x"1B6",x"223",x"2B0", -- 0x05D8
x"186",x"187",x"187",x"188",x"189",x"18A",x"18D",x"191", -- 0x05E0
x"197",x"1A2",x"1B3",x"1C8",x"1F4",x"223",x"289",x"30E", -- 0x05E8
x"253",x"253",x"253",x"253",x"253",x"253",x"253",x"253", -- 0x05F0
x"253",x"253",x"25B",x"26B",x"282",x"2B0",x"30E",x"37C", -- 0x05F8
x"014",x"016",x"018",x"01A",x"01D",x"021",x"027",x"02E", -- 0x0600
x"03A",x"048",x"061",x"07E",x"0B5",x"0FA",x"18A",x"256", -- 0x0608
x"016",x"018",x"01B",x"01C",x"020",x"023",x"029",x"030", -- 0x0610
x"03C",x"04A",x"063",x"080",x"0B7",x"0FC",x"18B",x"256", -- 0x0618
x"018",x"01B",x"01C",x"01E",x"021",x"025",x"02B",x"032", -- 0x0620
x"03E",x"04C",x"065",x"081",x"0B9",x"0FD",x"18B",x"256", -- 0x0628
x"01A",x"01C",x"01E",x"021",x"024",x"027",x"02D",x"034", -- 0x0630
x"040",x"04E",x"066",x"084",x"0BA",x"0FF",x"18C",x"256", -- 0x0638
x"01D",x"020",x"021",x"024",x"027",x"02B",x"030",x"037", -- 0x0640
x"043",x"051",x"069",x"086",x"0BC",x"101",x"18D",x"256", -- 0x0648
x"021",x"023",x"025",x"027",x"02B",x"02E",x"034",x"03B", -- 0x0650
x"047",x"054",x"06D",x"089",x"0C0",x"104",x"18E",x"256", -- 0x0658
x"027",x"029",x"02B",x"02D",x"030",x"034",x"03A",x"041", -- 0x0660
x"04C",x"05A",x"073",x"08E",x"0C4",x"108",x"191",x"256", -- 0x0668
x"02E",x"030",x"032",x"034",x"037",x"03B",x"041",x"047", -- 0x0670
x"053",x"061",x"079",x"094",x"0CA",x"10D",x"194",x"256", -- 0x0678
x"03A",x"03C",x"03E",x"040",x"043",x"047",x"04C",x"053", -- 0x0680
x"05F",x"06C",x"083",x"0A0",x"0D4",x"116",x"19B",x"256", -- 0x0688
x"048",x"04A",x"04C",x"04E",x"051",x"054",x"05A",x"061", -- 0x0690
x"06C",x"07A",x"091",x"0AC",x"0E0",x"121",x"1A6",x"256", -- 0x0698
x"061",x"063",x"065",x"066",x"069",x"06D",x"073",x"079", -- 0x06A0
x"083",x"091",x"0A7",x"0C3",x"0F5",x"135",x"1B7",x"25E", -- 0x06A8
x"07E",x"080",x"081",x"084",x"086",x"089",x"08E",x"094", -- 0x06B0
x"0A0",x"0AC",x"0C3",x"0DE",x"10F",x"14E",x"1CB",x"26D", -- 0x06B8
x"0B5",x"0B7",x"0B9",x"0BA",x"0BC",x"0C0",x"0C4",x"0CA", -- 0x06C0
x"0D4",x"0E0",x"0F5",x"10F",x"13F",x"17E",x"1F6",x"284", -- 0x06C8
x"0FA",x"0FC",x"0FD",x"0FF",x"101",x"103",x"108",x"10C", -- 0x06D0
x"116",x"121",x"135",x"14E",x"17D",x"1B8",x"226",x"2B2", -- 0x06D8
x"18A",x"18B",x"18B",x"18C",x"18D",x"18E",x"191",x"194", -- 0x06E0
x"19B",x"1A6",x"1B7",x"1CB",x"1F6",x"226",x"28B",x"30F", -- 0x06E8
x"256",x"256",x"256",x"256",x"256",x"256",x"256",x"256", -- 0x06F0
x"256",x"256",x"25E",x"26D",x"284",x"2B2",x"30F",x"37D", -- 0x06F8
x"01B",x"01D",x"01F",x"021",x"024",x"028",x"02E",x"034", -- 0x0700
x"041",x"04E",x"067",x"084",x"0BB",x"100",x"18E",x"25A", -- 0x0708
x"01D",x"01F",x"022",x"023",x"027",x"02A",x"030",x"037", -- 0x0710
x"043",x"050",x"069",x"086",x"0BD",x"101",x"18F",x"25A", -- 0x0718
x"01F",x"022",x"023",x"025",x"028",x"02C",x"032",x"039", -- 0x0720
x"044",x"053",x"06B",x"087",x"0BE",x"103",x"190",x"25A", -- 0x0728
x"021",x"023",x"025",x"028",x"02B",x"02E",x"034",x"03B", -- 0x0730
x"047",x"054",x"06D",x"08A",x"0C0",x"104",x"191",x"25A", -- 0x0738
x"024",x"027",x"028",x"02B",x"02E",x"031",x"037",x"03E", -- 0x0740
x"04A",x"057",x"070",x"08C",x"0C2",x"107",x"191",x"25A", -- 0x0748
x"028",x"02A",x"02C",x"02E",x"031",x"034",x"03B",x"041", -- 0x0750
x"04D",x"05A",x"073",x"08F",x"0C5",x"109",x"193",x"25A", -- 0x0758
x"02E",x"030",x"032",x"034",x"037",x"03B",x"041",x"047", -- 0x0760
x"053",x"060",x"079",x"094",x"0CA",x"10D",x"195",x"25A", -- 0x0768
x"034",x"037",x"039",x"03B",x"03E",x"041",x"047",x"04D", -- 0x0770
x"059",x"067",x"07F",x"09A",x"0D0",x"112",x"199",x"25A", -- 0x0778
x"041",x"043",x"044",x"047",x"04A",x"04D",x"053",x"059", -- 0x0780
x"065",x"072",x"089",x"0A5",x"0D9",x"11B",x"19F",x"25A", -- 0x0788
x"04E",x"050",x"053",x"054",x"057",x"05A",x"060",x"067", -- 0x0790
x"072",x"080",x"097",x"0B2",x"0E6",x"126",x"1AA",x"25A", -- 0x0798
x"067",x"069",x"06B",x"06D",x"070",x"073",x"079",x"07F", -- 0x07A0
x"089",x"097",x"0AD",x"0C8",x"0FA",x"13A",x"1BB",x"262", -- 0x07A8
x"084",x"086",x"087",x"08A",x"08C",x"08F",x"094",x"09A", -- 0x07B0
x"0A5",x"0B2",x"0C8",x"0E3",x"114",x"152",x"1CF",x"271", -- 0x07B8
x"0BB",x"0BD",x"0BE",x"0C0",x"0C2",x"0C5",x"0CA",x"0D0", -- 0x07C0
x"0D9",x"0E6",x"0FA",x"114",x"144",x"182",x"1FA",x"287", -- 0x07C8
x"0FF",x"101",x"102",x"104",x"106",x"108",x"10D",x"112", -- 0x07D0
x"11B",x"126",x"13A",x"152",x"181",x"1BC",x"229",x"2B5", -- 0x07D8
x"18E",x"18F",x"190",x"191",x"191",x"193",x"195",x"199", -- 0x07E0
x"19F",x"1AA",x"1BB",x"1CF",x"1F9",x"229",x"28D",x"312", -- 0x07E8
x"25A",x"25A",x"25A",x"25A",x"25A",x"25A",x"25A",x"25A", -- 0x07F0
x"25A",x"25A",x"261",x"270",x"287",x"2B5",x"312",x"37F", -- 0x07F8
x"027",x"02A",x"02B",x"02D",x"030",x"034",x"03A",x"041", -- 0x0800
x"04C",x"05A",x"072",x"08E",x"0C5",x"109",x"197",x"261", -- 0x0808
x"02A",x"02C",x"02E",x"030",x"033",x"036",x"03C",x"043", -- 0x0810
x"04F",x"05C",x"074",x"090",x"0C7",x"10B",x"198",x"261", -- 0x0818
x"02B",x"02E",x"030",x"032",x"035",x"038",x"03E",x"045", -- 0x0820
x"050",x"05E",x"076",x"092",x"0C8",x"10C",x"198",x"261", -- 0x0828
x"02D",x"030",x"032",x"034",x"037",x"03A",x"040",x"046", -- 0x0830
x"052",x"060",x"078",x"094",x"0CA",x"10E",x"199",x"261", -- 0x0838
x"030",x"033",x"035",x"037",x"03A",x"03E",x"043",x"049", -- 0x0840
x"055",x"062",x"07B",x"096",x"0CC",x"110",x"19A",x"261", -- 0x0848
x"034",x"036",x"038",x"03A",x"03E",x"041",x"046",x"04D", -- 0x0850
x"059",x"065",x"07E",x"099",x"0CF",x"112",x"19B",x"261", -- 0x0858
x"03A",x"03C",x"03E",x"040",x"043",x"046",x"04C",x"053", -- 0x0860
x"05E",x"06B",x"083",x"09E",x"0D3",x"117",x"19E",x"261", -- 0x0868
x"041",x"043",x"045",x"046",x"049",x"04D",x"053",x"059", -- 0x0870
x"065",x"072",x"089",x"0A4",x"0D9",x"11B",x"1A1",x"261", -- 0x0878
x"04C",x"04F",x"050",x"052",x"055",x"059",x"05E",x"065", -- 0x0880
x"070",x"07D",x"094",x"0AF",x"0E3",x"124",x"1A7",x"261", -- 0x0888
x"05A",x"05C",x"05E",x"060",x"062",x"065",x"06B",x"072", -- 0x0890
x"07D",x"08A",x"0A1",x"0BB",x"0EF",x"12F",x"1B2",x"261", -- 0x0898
x"072",x"074",x"076",x"078",x"07B",x"07E",x"083",x"089", -- 0x08A0
x"094",x"0A1",x"0B6",x"0D1",x"103",x"142",x"1C2",x"268", -- 0x08A8
x"08E",x"090",x"092",x"094",x"096",x"099",x"09E",x"0A4", -- 0x08B0
x"0AF",x"0BB",x"0D1",x"0EB",x"11C",x"15A",x"1D6",x"277", -- 0x08B8
x"0C5",x"0C7",x"0C8",x"0CA",x"0CC",x"0CF",x"0D3",x"0D9", -- 0x08C0
x"0E3",x"0EF",x"103",x"11C",x"14B",x"189",x"200",x"28D", -- 0x08C8
x"109",x"10A",x"10C",x"10D",x"110",x"112",x"116",x"11B", -- 0x08D0
x"123",x"12F",x"142",x"15A",x"189",x"1C3",x"22F",x"2BA", -- 0x08D8
x"197",x"198",x"198",x"199",x"19A",x"19B",x"19E",x"1A1", -- 0x08E0
x"1A7",x"1B2",x"1C2",x"1D6",x"200",x"22F",x"292",x"315", -- 0x08E8
x"260",x"260",x"260",x"260",x"260",x"260",x"260",x"260", -- 0x08F0
x"260",x"260",x"268",x"276",x"28C",x"2BA",x"315",x"382", -- 0x08F8
x"036",x"038",x"039",x"03B",x"03E",x"042",x"048",x"04E", -- 0x0900
x"05A",x"067",x"07F",x"09A",x"0D0",x"114",x"1A1",x"268", -- 0x0908
x"038",x"03A",x"03C",x"03E",x"041",x"044",x"04A",x"050", -- 0x0910
x"05C",x"069",x"080",x"09C",x"0D2",x"116",x"1A1",x"268", -- 0x0918
x"039",x"03C",x"03E",x"040",x"043",x"046",x"04C",x"052", -- 0x0920
x"05D",x"06B",x"083",x"09E",x"0D4",x"117",x"1A2",x"268", -- 0x0928
x"03B",x"03E",x"040",x"042",x"045",x"048",x"04D",x"054", -- 0x0930
x"05F",x"06C",x"084",x"0A0",x"0D5",x"119",x"1A3",x"268", -- 0x0938
x"03E",x"041",x"043",x"045",x"048",x"04B",x"050",x"057", -- 0x0940
x"062",x"06F",x"087",x"0A2",x"0D7",x"11B",x"1A3",x"268", -- 0x0948
x"042",x"044",x"046",x"048",x"04B",x"04E",x"054",x"05A", -- 0x0950
x"066",x"072",x"08A",x"0A5",x"0DA",x"11D",x"1A5",x"268", -- 0x0958
x"048",x"04A",x"04C",x"04D",x"050",x"054",x"05A",x"060", -- 0x0960
x"06B",x"078",x"090",x"0AA",x"0DF",x"121",x"1A7",x"268", -- 0x0968
x"04E",x"050",x"052",x"054",x"057",x"05A",x"060",x"066", -- 0x0970
x"071",x"07E",x"095",x"0B0",x"0E4",x"126",x"1AB",x"268", -- 0x0978
x"05A",x"05C",x"05D",x"05F",x"062",x"066",x"06B",x"071", -- 0x0980
x"07C",x"089",x"09F",x"0BB",x"0EE",x"12E",x"1B0",x"268", -- 0x0988
x"067",x"069",x"06B",x"06C",x"06F",x"072",x"078",x"07E", -- 0x0990
x"089",x"096",x"0AC",x"0C6",x"0F9",x"139",x"1BB",x"268", -- 0x0998
x"07F",x"080",x"083",x"084",x"087",x"08A",x"090",x"095", -- 0x09A0
x"09F",x"0AC",x"0C1",x"0DC",x"10D",x"14C",x"1CB",x"26F", -- 0x09A8
x"09A",x"09C",x"09E",x"0A0",x"0A2",x"0A5",x"0AA",x"0B0", -- 0x09B0
x"0BB",x"0C6",x"0DC",x"0F6",x"126",x"163",x"1DE",x"27E", -- 0x09B8
x"0D0",x"0D2",x"0D4",x"0D5",x"0D7",x"0DA",x"0DF",x"0E4", -- 0x09C0
x"0EE",x"0F9",x"10D",x"126",x"154",x"192",x"207",x"293", -- 0x09C8
x"114",x"115",x"117",x"118",x"11A",x"11C",x"121",x"125", -- 0x09D0
x"12E",x"138",x"14C",x"163",x"191",x"1CA",x"235",x"2BF", -- 0x09D8
x"1A1",x"1A1",x"1A2",x"1A3",x"1A3",x"1A5",x"1A7",x"1AB", -- 0x09E0
x"1B0",x"1BB",x"1CB",x"1DE",x"207",x"235",x"298",x"31A", -- 0x09E8
x"268",x"268",x"268",x"268",x"268",x"268",x"268",x"268", -- 0x09F0
x"268",x"268",x"26F",x"27D",x"293",x"2BF",x"31A",x"386", -- 0x09F8
x"050",x"052",x"053",x"055",x"058",x"05B",x"061",x"067", -- 0x0A00
x"072",x"07E",x"096",x"0B0",x"0E5",x"128",x"1B1",x"275", -- 0x0A08
x"052",x"054",x"056",x"057",x"05B",x"05D",x"063",x"069", -- 0x0A10
x"074",x"080",x"097",x"0B2",x"0E7",x"129",x"1B2",x"275", -- 0x0A18
x"053",x"056",x"057",x"059",x"05C",x"05F",x"065",x"06B", -- 0x0A20
x"075",x"082",x"099",x"0B4",x"0E8",x"12B",x"1B3",x"275", -- 0x0A28
x"055",x"057",x"059",x"05B",x"05E",x"061",x"066",x"06C", -- 0x0A30
x"077",x"084",x"09B",x"0B6",x"0EA",x"12C",x"1B4",x"275", -- 0x0A38
x"058",x"05B",x"05C",x"05E",x"061",x"064",x"069",x"06F", -- 0x0A40
x"07A",x"086",x"09D",x"0B8",x"0EC",x"12E",x"1B4",x"275", -- 0x0A48
x"05B",x"05D",x"05F",x"061",x"064",x"067",x"06C",x"073", -- 0x0A50
x"07E",x"089",x"0A0",x"0BA",x"0EE",x"130",x"1B6",x"275", -- 0x0A58
x"061",x"063",x"065",x"066",x"069",x"06C",x"072",x"078", -- 0x0A60
x"082",x"08F",x"0A5",x"0BF",x"0F3",x"134",x"1B8",x"275", -- 0x0A68
x"067",x"069",x"06B",x"06C",x"06F",x"073",x"078",x"07E", -- 0x0A70
x"088",x"095",x"0AB",x"0C5",x"0F8",x"138",x"1BB",x"275", -- 0x0A78
x"072",x"074",x"075",x"077",x"07A",x"07E",x"082",x"088", -- 0x0A80
x"093",x"09F",x"0B5",x"0CF",x"101",x"141",x"1C0",x"275", -- 0x0A88
x"07E",x"080",x"082",x"084",x"086",x"089",x"08F",x"095", -- 0x0A90
x"09F",x"0AB",x"0C1",x"0DA",x"10C",x"14B",x"1CB",x"275", -- 0x0A98
x"096",x"097",x"099",x"09B",x"09D",x"0A0",x"0A5",x"0AB", -- 0x0AA0
x"0B5",x"0C1",x"0D5",x"0EF",x"11F",x"15D",x"1DA",x"27C", -- 0x0AA8
x"0B0",x"0B2",x"0B4",x"0B6",x"0B8",x"0BA",x"0BF",x"0C5", -- 0x0AB0
x"0CF",x"0DA",x"0EF",x"108",x"136",x"172",x"1EC",x"28A", -- 0x0AB8
x"0E5",x"0E7",x"0E8",x"0EA",x"0EC",x"0EE",x"0F3",x"0F8", -- 0x0AC0
x"101",x"10C",x"11E",x"136",x"164",x"1A0",x"213",x"29E", -- 0x0AC8
x"127",x"128",x"12A",x"12B",x"12D",x"12F",x"133",x"137", -- 0x0AD0
x"140",x"14A",x"15D",x"172",x"19F",x"1D7",x"240",x"2C8", -- 0x0AD8
x"1B1",x"1B2",x"1B3",x"1B4",x"1B4",x"1B6",x"1B8",x"1BB", -- 0x0AE0
x"1C0",x"1CB",x"1DA",x"1EC",x"212",x"240",x"2A1",x"320", -- 0x0AE8
x"274",x"274",x"274",x"274",x"274",x"274",x"274",x"274", -- 0x0AF0
x"274",x"274",x"27B",x"288",x"29D",x"2C8",x"320",x"38B", -- 0x0AF8
x"06D",x"06F",x"070",x"072",x"075",x"078",x"07D",x"082", -- 0x0B00
x"08C",x"097",x"0AE",x"0C6",x"0F9",x"13B",x"1C0",x"27D", -- 0x0B08
x"06F",x"071",x"073",x"074",x"077",x"079",x"07E",x"084", -- 0x0B10
x"08E",x"099",x"0AF",x"0C8",x"0FB",x"13C",x"1C1",x"27D", -- 0x0B18
x"070",x"073",x"074",x"076",x"078",x"07B",x"080",x"086", -- 0x0B20
x"08F",x"09B",x"0B1",x"0CA",x"0FD",x"13D",x"1C1",x"27D", -- 0x0B28
x"072",x"074",x"076",x"078",x"07A",x"07D",x"082",x"087", -- 0x0B30
x"091",x"09C",x"0B2",x"0CB",x"0FE",x"13F",x"1C2",x"27D", -- 0x0B38
x"075",x"077",x"078",x"07A",x"07D",x"080",x"084",x"08A", -- 0x0B40
x"094",x"09F",x"0B5",x"0CD",x"100",x"141",x"1C2",x"27D", -- 0x0B48
x"078",x"079",x"07B",x"07D",x"080",x"082",x"087",x"08D", -- 0x0B50
x"097",x"0A1",x"0B7",x"0D0",x"102",x"142",x"1C4",x"27D", -- 0x0B58
x"07D",x"07E",x"080",x"082",x"084",x"087",x"08C",x"092", -- 0x0B60
x"09B",x"0A6",x"0BC",x"0D4",x"106",x"146",x"1C6",x"27D", -- 0x0B68
x"082",x"084",x"086",x"087",x"08A",x"08D",x"092",x"097", -- 0x0B70
x"0A1",x"0AC",x"0C1",x"0D9",x"10B",x"14A",x"1C9",x"27D", -- 0x0B78
x"08C",x"08E",x"08F",x"091",x"094",x"097",x"09B",x"0A1", -- 0x0B80
x"0AA",x"0B5",x"0CA",x"0E3",x"113",x"151",x"1CE",x"27D", -- 0x0B88
x"097",x"099",x"09B",x"09C",x"09F",x"0A1",x"0A6",x"0AC", -- 0x0B90
x"0B5",x"0C1",x"0D5",x"0ED",x"11D",x"15B",x"1D7",x"27D", -- 0x0B98
x"0AE",x"0AF",x"0B1",x"0B2",x"0B5",x"0B7",x"0BC",x"0C1", -- 0x0BA0
x"0CA",x"0D5",x"0E7",x"100",x"12F",x"16B",x"1E5",x"283", -- 0x0BA8
x"0C6",x"0C8",x"0CA",x"0CB",x"0CD",x"0D0",x"0D4",x"0D9", -- 0x0BB0
x"0E3",x"0ED",x"100",x"118",x"145",x"17F",x"1F6",x"290", -- 0x0BB8
x"0F9",x"0FB",x"0FD",x"0FE",x"100",x"102",x"106",x"10B", -- 0x0BC0
x"113",x"11D",x"12E",x"145",x"170",x"1AB",x"21A",x"2A2", -- 0x0BC8
x"139",x"13A",x"13C",x"13D",x"13F",x"141",x"144",x"148", -- 0x0BD0
x"150",x"159",x"16B",x"17F",x"1A9",x"1DF",x"245",x"2CA", -- 0x0BD8
x"1C0",x"1C1",x"1C1",x"1C2",x"1C2",x"1C4",x"1C6",x"1C9", -- 0x0BE0
x"1CE",x"1D7",x"1E5",x"1F6",x"219",x"245",x"2A2",x"31E", -- 0x0BE8
x"27B",x"27B",x"27B",x"27B",x"27B",x"27B",x"27B",x"27B", -- 0x0BF0
x"27B",x"27B",x"282",x"28E",x"2A1",x"2CA",x"31E",x"386", -- 0x0BF8
x"0A5",x"0A7",x"0A8",x"0A9",x"0AB",x"0AE",x"0B2",x"0B7", -- 0x0C00
x"0C0",x"0C9",x"0DD",x"0F3",x"123",x"162",x"1E0",x"292", -- 0x0C08
x"0A7",x"0A8",x"0AA",x"0AB",x"0AE",x"0B0",x"0B4",x"0B9", -- 0x0C10
x"0C1",x"0CB",x"0DE",x"0F5",x"125",x"163",x"1E1",x"292", -- 0x0C18
x"0A8",x"0AA",x"0AB",x"0AD",x"0AF",x"0B1",x"0B6",x"0BA", -- 0x0C20
x"0C2",x"0CC",x"0E0",x"0F6",x"126",x"164",x"1E1",x"292", -- 0x0C28
x"0A9",x"0AB",x"0AD",x"0AE",x"0B0",x"0B2",x"0B7",x"0BB", -- 0x0C30
x"0C4",x"0CD",x"0E1",x"0F8",x"127",x"165",x"1E2",x"292", -- 0x0C38
x"0AB",x"0AE",x"0AF",x"0B0",x"0B2",x"0B5",x"0B9",x"0BD", -- 0x0C40
x"0C6",x"0CF",x"0E3",x"0F9",x"129",x"167",x"1E2",x"292", -- 0x0C48
x"0AE",x"0B0",x"0B1",x"0B2",x"0B5",x"0B7",x"0BB",x"0C0", -- 0x0C50
x"0C9",x"0D2",x"0E5",x"0FB",x"12B",x"168",x"1E3",x"292", -- 0x0C58
x"0B2",x"0B4",x"0B6",x"0B7",x"0B9",x"0BB",x"0C0",x"0C4", -- 0x0C60
x"0CC",x"0D6",x"0E9",x"0FF",x"12E",x"16C",x"1E5",x"292", -- 0x0C68
x"0B7",x"0B9",x"0BA",x"0BB",x"0BD",x"0C0",x"0C4",x"0C9", -- 0x0C70
x"0D1",x"0DB",x"0EE",x"103",x"132",x"16F",x"1E8",x"292", -- 0x0C78
x"0C0",x"0C1",x"0C2",x"0C4",x"0C6",x"0C9",x"0CC",x"0D1", -- 0x0C80
x"0D9",x"0E2",x"0F5",x"10B",x"139",x"175",x"1EC",x"292", -- 0x0C88
x"0C9",x"0CB",x"0CC",x"0CD",x"0CF",x"0D2",x"0D6",x"0DB", -- 0x0C90
x"0E2",x"0EC",x"0FF",x"114",x"142",x"17D",x"1F4",x"292", -- 0x0C98
x"0DD",x"0DE",x"0E0",x"0E1",x"0E3",x"0E5",x"0E9",x"0EE", -- 0x0CA0
x"0F5",x"0FF",x"10E",x"126",x"152",x"18B",x"1FF",x"298", -- 0x0CA8
x"0F3",x"0F5",x"0F6",x"0F8",x"0F9",x"0FB",x"0FF",x"103", -- 0x0CB0
x"10B",x"114",x"126",x"13B",x"164",x"19C",x"20E",x"2A2", -- 0x0CB8
x"123",x"125",x"126",x"127",x"129",x"12B",x"12E",x"132", -- 0x0CC0
x"139",x"142",x"150",x"164",x"18D",x"1C4",x"22E",x"2B2", -- 0x0CC8
x"160",x"161",x"162",x"163",x"164",x"166",x"169",x"16C", -- 0x0CD0
x"173",x"17A",x"18B",x"19C",x"1C2",x"1F4",x"256",x"2D5", -- 0x0CD8
x"1E0",x"1E1",x"1E1",x"1E2",x"1E2",x"1E3",x"1E5",x"1E8", -- 0x0CE0
x"1EC",x"1F4",x"1FF",x"20E",x"22B",x"256",x"2AD",x"324", -- 0x0CE8
x"290",x"290",x"290",x"290",x"290",x"290",x"290",x"290", -- 0x0CF0
x"290",x"290",x"295",x"2A0",x"2B0",x"2D5",x"324",x"388", -- 0x0CF8
x"0EB",x"0ED",x"0EE",x"0EF",x"0F1",x"0F3",x"0F7",x"0FB", -- 0x0D00
x"103",x"10B",x"11E",x"132",x"160",x"19D",x"217",x"2C2", -- 0x0D08
x"0ED",x"0EE",x"0F0",x"0F1",x"0F3",x"0F5",x"0F8",x"0FD", -- 0x0D10
x"104",x"10C",x"11F",x"134",x"162",x"19E",x"217",x"2C2", -- 0x0D18
x"0EE",x"0F0",x"0F1",x"0F2",x"0F4",x"0F6",x"0FA",x"0FE", -- 0x0D20
x"105",x"10E",x"120",x"135",x"163",x"19F",x"217",x"2C2", -- 0x0D28
x"0EF",x"0F1",x"0F2",x"0F3",x"0F5",x"0F7",x"0FB",x"0FF", -- 0x0D30
x"106",x"10F",x"121",x"136",x"164",x"1A0",x"218",x"2C2", -- 0x0D38
x"0F1",x"0F3",x"0F4",x"0F5",x"0F7",x"0F9",x"0FD",x"101", -- 0x0D40
x"108",x"111",x"123",x"137",x"165",x"1A1",x"218",x"2C2", -- 0x0D48
x"0F3",x"0F5",x"0F6",x"0F7",x"0F9",x"0FB",x"0FF",x"103", -- 0x0D50
x"10B",x"113",x"125",x"139",x"167",x"1A3",x"219",x"2C2", -- 0x0D58
x"0F7",x"0F8",x"0FA",x"0FB",x"0FD",x"0FF",x"103",x"107", -- 0x0D60
x"10E",x"116",x"128",x"13C",x"16A",x"1A6",x"21B",x"2C2", -- 0x0D68
x"0FB",x"0FD",x"0FE",x"0FF",x"101",x"103",x"107",x"10B", -- 0x0D70
x"112",x"11A",x"12C",x"140",x"16D",x"1A8",x"21D",x"2C2", -- 0x0D78
x"103",x"104",x"105",x"106",x"108",x"10B",x"10E",x"112", -- 0x0D80
x"119",x"121",x"133",x"147",x"173",x"1AE",x"221",x"2C2", -- 0x0D88
x"10B",x"10C",x"10E",x"10F",x"111",x"113",x"116",x"11A", -- 0x0D90
x"121",x"12A",x"13B",x"14F",x"17B",x"1B5",x"228",x"2C2", -- 0x0D98
x"11E",x"11F",x"120",x"121",x"123",x"125",x"128",x"12C", -- 0x0DA0
x"133",x"13B",x"149",x"15F",x"18B",x"1C1",x"232",x"2C6", -- 0x0DA8
x"132",x"134",x"135",x"136",x"137",x"139",x"13C",x"140", -- 0x0DB0
x"147",x"14F",x"15F",x"173",x"19A",x"1D0",x"23F",x"2D0", -- 0x0DB8
x"160",x"162",x"163",x"164",x"165",x"167",x"16A",x"16D", -- 0x0DC0
x"173",x"17B",x"187",x"19A",x"1C1",x"1F7",x"25C",x"2DE", -- 0x0DC8
x"19A",x"19B",x"19C",x"19D",x"19E",x"1A0",x"1A2",x"1A5", -- 0x0DD0
x"1AB",x"1B2",x"1C1",x"1D0",x"1F3",x"224",x"282",x"2FD", -- 0x0DD8
x"217",x"217",x"217",x"218",x"218",x"219",x"21B",x"21D", -- 0x0DE0
x"221",x"228",x"232",x"23F",x"259",x"282",x"2D5",x"348", -- 0x0DE8
x"2BE",x"2BE",x"2BE",x"2BE",x"2BE",x"2BE",x"2BE",x"2BE", -- 0x0DF0
x"2BE",x"2BE",x"2C3",x"2CC",x"2DA",x"2FD",x"348",x"3AA", -- 0x0DF8
x"17D",x"17E",x"17E",x"17F",x"181",x"183",x"185",x"188", -- 0x0E00
x"18E",x"194",x"1A4",x"1B5",x"1DF",x"218",x"288",x"325", -- 0x0E08
x"17E",x"17F",x"180",x"180",x"182",x"184",x"186",x"189", -- 0x0E10
x"18F",x"195",x"1A4",x"1B6",x"1E0",x"219",x"288",x"325", -- 0x0E18
x"17E",x"180",x"180",x"182",x"183",x"185",x"187",x"18A", -- 0x0E20
x"18F",x"196",x"1A5",x"1B6",x"1E0",x"219",x"289",x"325", -- 0x0E28
x"17F",x"180",x"182",x"183",x"184",x"185",x"188",x"18B", -- 0x0E30
x"190",x"197",x"1A6",x"1B7",x"1E1",x"21A",x"289",x"325", -- 0x0E38
x"181",x"182",x"183",x"184",x"185",x"187",x"189",x"18C", -- 0x0E40
x"192",x"198",x"1A7",x"1B8",x"1E2",x"21B",x"289",x"325", -- 0x0E48
x"183",x"184",x"185",x"185",x"187",x"188",x"18B",x"18E", -- 0x0E50
x"194",x"199",x"1A9",x"1BA",x"1E4",x"21C",x"28A",x"325", -- 0x0E58
x"185",x"186",x"187",x"188",x"189",x"18B",x"18E",x"191", -- 0x0E60
x"196",x"19C",x"1AB",x"1BC",x"1E6",x"21E",x"28B",x"325", -- 0x0E68
x"188",x"189",x"18A",x"18B",x"18C",x"18E",x"191",x"194", -- 0x0E70
x"199",x"19F",x"1AE",x"1BF",x"1E8",x"220",x"28D",x"325", -- 0x0E78
x"18E",x"18F",x"18F",x"190",x"192",x"194",x"196",x"199", -- 0x0E80
x"19E",x"1A4",x"1B3",x"1C4",x"1ED",x"224",x"290",x"325", -- 0x0E88
x"194",x"195",x"196",x"197",x"198",x"199",x"19C",x"19F", -- 0x0E90
x"1A4",x"1AA",x"1B9",x"1C9",x"1F2",x"229",x"295",x"325", -- 0x0E98
x"1A4",x"1A4",x"1A5",x"1A6",x"1A7",x"1A9",x"1AB",x"1AE", -- 0x0EA0
x"1B3",x"1B9",x"1C3",x"1D8",x"200",x"232",x"29C",x"328", -- 0x0EA8
x"1B5",x"1B6",x"1B6",x"1B7",x"1B8",x"1BA",x"1BC",x"1BF", -- 0x0EB0
x"1C4",x"1C9",x"1D8",x"1E8",x"20B",x"23D",x"2A5",x"32F", -- 0x0EB8
x"1DF",x"1E0",x"1E0",x"1E1",x"1E2",x"1E4",x"1E6",x"1E8", -- 0x0EC0
x"1ED",x"1F2",x"1FB",x"20B",x"22E",x"260",x"2BD",x"339", -- 0x0EC8
x"214",x"214",x"215",x"216",x"217",x"218",x"21A",x"21C", -- 0x0ED0
x"220",x"225",x"232",x"23D",x"25B",x"287",x"2DF",x"352", -- 0x0ED8
x"288",x"288",x"289",x"289",x"289",x"28A",x"28B",x"28D", -- 0x0EE0
x"290",x"295",x"29C",x"2A5",x"2B8",x"2DF",x"32B",x"396", -- 0x0EE8
x"320",x"320",x"320",x"320",x"320",x"320",x"320",x"320", -- 0x0EF0
x"320",x"320",x"324",x"32B",x"335",x"352",x"396",x"3F3", -- 0x0EF8
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F00
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F08
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F10
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F18
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F20
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F28
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F30
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F38
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F40
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F48
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F50
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F58
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F60
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F68
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F70
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F78
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F80
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F88
x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F90
x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F98
x"254",x"254",x"254",x"254",x"254",x"254",x"254",x"254", -- 0x0FA0
x"254",x"254",x"254",x"264",x"284",x"2AB",x"302",x"379", -- 0x0FA8
x"25C",x"25C",x"25C",x"25C",x"25C",x"25C",x"25C",x"25C", -- 0x0FB0
x"25C",x"25C",x"264",x"26C",x"284",x"2AB",x"302",x"379", -- 0x0FB8
x"27C",x"27C",x"27C",x"27C",x"27C",x"27C",x"27C",x"27C", -- 0x0FC0
x"27C",x"27C",x"27C",x"284",x"29C",x"2C3",x"30A",x"379", -- 0x0FC8
x"2A3",x"2A3",x"2A3",x"2A3",x"2A3",x"2A3",x"2A3",x"2A3", -- 0x0FD0
x"2A3",x"2A3",x"2AB",x"2AB",x"2BB",x"2DB",x"322",x"381", -- 0x0FD8
x"302",x"302",x"302",x"302",x"302",x"302",x"302",x"302", -- 0x0FE0
x"302",x"302",x"302",x"302",x"302",x"322",x"359",x"3B0", -- 0x0FE8
x"371",x"371",x"371",x"371",x"371",x"371",x"371",x"371", -- 0x0FF0
x"371",x"371",x"371",x"371",x"371",x"381",x"3B0",x"3FF" -- 0x0FF8
);
begin
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= ROM(to_integer(unsigned(ADDR)))(9 downto 0);
end process;
end RTL;