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Stable overscan core
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@@ -88,7 +88,7 @@ set_output_delay -clock sdclk_pin -min -0.8 [get_ports SDRAM_*]
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# Set Multicycle Path
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#**************************************************************
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set_multicycle_path -from [get_clocks {sdclk_pin}] -to [get_clocks {clock|altpll_component|auto_generated|pll1|clk[2]}] -setup -end 2
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set_multicycle_path -from [get_clocks {sdclk_pin}] -to [get_clocks {clock|altpll_component|auto_generated|pll1|clk[0]}] -setup -end 2
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#**************************************************************
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@@ -100,7 +100,7 @@ always @(posedge clk_8) begin
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// timeout only when cpu owns the bus and when
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// neither dtack nor fast ram are active
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if(dtack_timeout != 3'd7) begin
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if(!tg68_dtack || br || tg68_cpuena || tg68_lds || tg68_uds)
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if(!tg68_dtack || br || tg68_cpuena || tg68_as)
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dtack_timeout <= 3'd0;
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else
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dtack_timeout <= dtack_timeout + 3'd1;
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