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Archie: common FDC with the ST core
This commit is contained in:
Gyorgy Szombathelyi
@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP3C25E144C8
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set_global_assignment -name TOP_LEVEL_ENTITY archimedes_mist_top
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:48:24 SEPTEMBER 20, 2014"
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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@@ -136,7 +136,7 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_*
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/sd.stp
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/fdc.stp
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
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set_global_assignment -name ENABLE_NCE_PIN OFF
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@@ -171,12 +171,13 @@ set_global_assignment -name SMART_RECOMPILE ON
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
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set_global_assignment -name FITTER_EFFORT "AUTO FIT"
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*]
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set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[*]
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set_global_assignment -name SEED 1
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set_global_assignment -name ENABLE_DRC_SETTINGS OFF
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set_location_assignment PLL_1 -to CLOCKS|altpll_component|auto_generated|pll1
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set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
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set_global_assignment -name VERILOG_FILE archimedes_mist_top.v
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set_global_assignment -name SYSTEMVERILOG_FILE rgb2ypbpr.sv
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set_global_assignment -name VERILOG_FILE sigma_delta_dac.v
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@@ -226,5 +227,4 @@ set_global_assignment -name QIP_FILE rom_reconfig_36.qip
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set_global_assignment -name QIP_FILE pll_vidc.qip
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set_global_assignment -name SIGNALTAP_FILE output_files/vidc.stp
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set_global_assignment -name SIGNALTAP_FILE output_files/sd.stp
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set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@@ -297,63 +297,63 @@ podules PODULES(
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.speed_i ( ioc_speed ),
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.wb_cyc ( cpu_cyc & podules_en),
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.wb_stb ( cpu_stb & podules_en),
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.wb_we ( cpu_we & podules_en),
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.wb_cyc ( cpu_cyc & podules_en ),
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.wb_stb ( cpu_stb & podules_en ),
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.wb_we ( cpu_we & podules_en ),
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.wb_dat_o ( pod_dat_o ),
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.wb_dat_i ( cpu_dat_o[15:0] ),
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.wb_adr ( cpu_address[15:2] )
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.wb_adr ( cpu_address[15:2] ),
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);
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wire [7:0] floppy_dat_o;
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wire floppy_en = ioc_cs & ioc_select[1];
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wire [7:0] floppy_dat_o;
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wire floppy_en = ioc_cs & ioc_select[1];
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// floppy drive signals.
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wire [3:0] floppy_drive;
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wire floppy_side;
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wire floppy_motor;
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wire floppy_inuse;
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wire floppy_density;
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wire floppy_reset;
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fdc1772 FDC1772 (
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.clkcpu ( CLKCPU_I ),
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.clk8m_en ( ioc_clk8m_en ),
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.wb_cyc ( cpu_cyc & floppy_en ),
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.wb_stb ( cpu_stb & floppy_en ),
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.wb_we ( cpu_we & floppy_en ),
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.wb_dat_o ( floppy_dat_o ),
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.wb_dat_i ( cpu_dat_o[23:16] ),
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.wb_adr ( cpu_address[15:2] ),
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.floppy_firq ( floppy_firq ),
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.floppy_drq ( floppy_drq ),
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.img_mounted ( img_mounted ),
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.img_size ( img_size ),
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.img_wp ( 0 ),
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.sd_lba ( sd_lba ),
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.sd_rd ( sd_rd ),
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.sd_wr ( sd_wr ),
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.sd_ack ( sd_ack ),
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.sd_buff_addr ( sd_buff_addr ),
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.sd_dout ( sd_dout ),
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.sd_din ( sd_din ),
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.sd_dout_strobe ( sd_dout_strobe ),
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.sd_din_strobe ( sd_din_strobe ),
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wire [3:0] floppy_drive;
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wire floppy_side;
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wire floppy_motor;
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wire floppy_inuse;
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wire floppy_density;
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wire floppy_reset;
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.floppy_drive ( floppy_drive ),
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.floppy_motor ( floppy_motor ),
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.floppy_inuse ( floppy_inuse ),
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.floppy_side ( floppy_side ),
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.floppy_density ( floppy_density ),
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.floppy_reset ( floppy_reset )
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wire fdc_sel = cpu_stb & cpu_cyc & floppy_en;
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fdc1772 #(.CLK(42000000)) FDC1772 (
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.clkcpu ( CLKCPU_I ),
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.clk8m_en ( ioc_clk8m_en ),
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.cpu_sel ( fdc_sel ),
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.cpu_rw ( !cpu_we ),
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.cpu_addr ( cpu_address[3:2] ),
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.cpu_dout ( floppy_dat_o ),
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.cpu_din ( cpu_dat_o[23:16] ),
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.irq ( floppy_firq ),
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.drq ( floppy_drq ),
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.img_mounted ( img_mounted ),
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.img_size ( img_size ),
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.img_wp ( 0 ),
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.sd_lba ( sd_lba ),
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.sd_rd ( sd_rd ),
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.sd_wr ( sd_wr ),
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.sd_ack ( sd_ack ),
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.sd_buff_addr ( sd_buff_addr ),
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.sd_dout ( sd_dout ),
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.sd_din ( sd_din ),
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.sd_dout_strobe ( sd_dout_strobe ),
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.sd_din_strobe ( sd_din_strobe ),
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.floppy_drive ( floppy_drive ),
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// .floppy_motor ( floppy_motor ),
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// .floppy_inuse ( floppy_inuse ),
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.floppy_side ( floppy_side ),
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// .floppy_density ( floppy_density ),
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.floppy_reset ( floppy_reset )
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);
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wire [7:0] latches_dat_o;
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wire latches_en = ioc_cs & ioc_select[5] & (ioc_speed == 2'd2);
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File diff suppressed because it is too large
Load Diff
@@ -25,9 +25,15 @@ module floppy (
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input step_in,
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input step_out,
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input [10:0] sector_len,
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input sector_base, // number of first sector on track (archie 0, dos 1)
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input [4:0] spt, // sectors/track
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input [9:0] sector_gap_len, // gap len/sector
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input hd,
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output dclk_en, // data clock enable
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output [6:0] track, // number of track under head
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output [3:0] sector, // number of sector under head, 0 = no sector
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output [4:0] sector, // number of sector under head, 0 = no sector
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output sector_hdr, // valid sector header under head
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output sector_data, // valid sector data under head
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@@ -41,9 +47,10 @@ parameter SYS_CLK = 8000000;
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assign sector_hdr = (sec_state == SECTOR_STATE_HDR);
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assign sector_data = (sec_state == SECTOR_STATE_DATA);
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// a standard DD floppy has a data rate of 250kBit/s and rotates at 300RPM
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localparam RATE = 20'd250000;
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localparam RATEDD = 20'd250000;
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localparam RATEHD = 20'd500000;
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localparam RPM = 10'd300;
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localparam STEPBUSY = 8'd18; // 18ms after step data can be read
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localparam SPINUP = 10'd500; // drive spins up in up to 800ms
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@@ -53,34 +60,36 @@ localparam SECTOR_HDR_LEN = 4'd6; // GUESSED: Sector header is 6 bytes
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localparam TRACKS = 8'd85; // max allowed track
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// Archimedes specific values
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localparam SECTOR_LEN = 11'd1024; // Default sector size is 1k on Archie ...
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localparam SPT = 4'd5; // ... with 5 sectors per track
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localparam SECTOR_BASE = 4'd0; // number of first sector on track (archie 0, dos 1)
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//localparam SECTOR_LEN = 11'd1024 // Default sector size is 1024 on Archie
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//localparam SECTOR_LEN = 11'd512; // Default sector size is 512 on ST ...
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//localparam SPT = 4'd10; // ... with 5 sectors per track
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//localparam SECTOR_BASE = 4'd1; // number of first sector on track (archie 0, dos 1)
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// number of physical bytes per track
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localparam BPT = RATE*60/(8*RPM);
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localparam BPTDD = RATEDD*60/(8*RPM);
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localparam BPTHD = RATEHD*60/(8*RPM);
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// report disk ready if it spins at full speed and head is not moving
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assign ready = select && (rate == RATE) && (step_busy == 0);
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assign ready = select && (rate == (hd ? RATEHD : RATEDD)) && (step_busy == 0);
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// ================================================================
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// ========================= INDEX PULSE ==========================
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// ================================================================
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// Index pulse generation. Pulse starts with the begin of index_pulse_start
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// and lasts INDEX_PULSE_CYCLES system clock cycles
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localparam INDEX_PULSE_CYCLES = INDEX_PULSE_LEN * SYS_CLK / 1000;
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reg [18:0] index_pulse_cnt;
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always @(posedge clk) begin
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if(index_pulse_start && (index_pulse_cnt == INDEX_PULSE_CYCLES-1)) begin
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index <= 1'b0;
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index_pulse_cnt <= 16'd0;
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end else if(index_pulse_cnt == INDEX_PULSE_CYCLES-1)
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index <= 1'b1;
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else
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index_pulse_cnt <= index_pulse_cnt + 16'd1;
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if(index_pulse_start && (index_pulse_cnt == INDEX_PULSE_CYCLES-1)) begin
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index <= 1'b0;
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index_pulse_cnt <= 19'd0;
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end else if(index_pulse_cnt == INDEX_PULSE_CYCLES-1)
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index <= 1'b1;
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else
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index_pulse_cnt <= index_pulse_cnt + 1'd1;
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end
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// ================================================================
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// ======================= track handling =========================
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// ================================================================
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@@ -88,91 +97,90 @@ end
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localparam[19:0] STEP_BUSY_CLKS = (SYS_CLK/1000)*STEPBUSY; // steprate is in ms
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assign track = current_track;
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reg [6:0] current_track = 7'd0;
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reg [6:0] current_track /* verilator public */ = 7'd0;
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reg step_inD;
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reg step_outD;
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reg [19:0] step_busy;
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reg [19:0] step_busy /* verilator public */;
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always @(posedge clk) begin
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step_inD <= step_in;
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step_outD <= step_out;
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step_inD <= step_in;
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step_outD <= step_out;
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if(step_busy != 0)
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step_busy <= step_busy - 18'd1;
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if(step_busy != 0)
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step_busy <= step_busy - 18'd1;
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if(select) begin
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// rising edge of step signal starts step
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if(step_in && !step_inD) begin
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if(current_track != 0) current_track <= current_track - 7'd1;
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step_busy <= STEP_BUSY_CLKS;
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end
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if(select) begin
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// rising edge of step signal starts step
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if(step_in && !step_inD) begin
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if(current_track != 0) current_track <= current_track - 7'd1;
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step_busy <= STEP_BUSY_CLKS;
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end
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if(step_out && !step_outD) begin
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if(current_track != TRACKS-1) current_track <= current_track + 7'd1;
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step_busy <= STEP_BUSY_CLKS;
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end
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end
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if(step_out && !step_outD) begin
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if(current_track != TRACKS-1) current_track <= current_track + 7'd1;
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step_busy <= STEP_BUSY_CLKS;
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end
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end
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end
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// ================================================================
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// ====================== sector handling =========================
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// ================================================================
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// track has BPT bytes
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// SPT sectors are stored on the track
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localparam SECTOR_GAP_LEN = BPT/SPT - (SECTOR_LEN + SECTOR_HDR_LEN);
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//localparam SECTOR_GAP_LEN = BPT/SPT - (SECTOR_LEN + SECTOR_HDR_LEN);
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assign sector = current_sector;
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localparam SECTOR_STATE_GAP = 2'd0;
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localparam SECTOR_STATE_HDR = 2'd1;
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localparam SECTOR_STATE_DATA = 2'd2;
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// we simulate an interleave of 1
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reg [3:0] start_sector = SECTOR_BASE;
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reg [4:0] start_sector = 4'd1;
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reg [1:0] sec_state;
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reg [9:0] sec_byte_cnt; // counting bytes within sectors
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reg [3:0] current_sector = SECTOR_BASE;
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reg [4:0] current_sector = 4'd1;
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always @(posedge clk) begin
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if (byte_clk_en) begin
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if(index_pulse_start) begin
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sec_byte_cnt <= SECTOR_GAP_LEN-1'd1;
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sec_state <= SECTOR_STATE_GAP; // track starts with gap
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current_sector <= start_sector; // track starts with sector 1
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end else begin
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if(sec_byte_cnt == 0) begin
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case(sec_state)
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SECTOR_STATE_GAP: begin
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sec_state <= SECTOR_STATE_HDR;
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sec_byte_cnt <= SECTOR_HDR_LEN-1'd1;
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end
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if(index_pulse_start) begin
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sec_byte_cnt <= sector_gap_len-1'd1;
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sec_state <= SECTOR_STATE_GAP; // track starts with gap
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current_sector <= start_sector; // track starts with sector 1
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end else begin
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if(sec_byte_cnt == 0) begin
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case(sec_state)
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SECTOR_STATE_GAP: begin
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sec_state <= SECTOR_STATE_HDR;
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sec_byte_cnt <= SECTOR_HDR_LEN-1'd1;
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end
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SECTOR_STATE_HDR: begin
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sec_state <= SECTOR_STATE_DATA;
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sec_byte_cnt <= SECTOR_LEN-1'd1;
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end
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SECTOR_STATE_HDR: begin
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sec_state <= SECTOR_STATE_DATA;
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sec_byte_cnt <= sector_len-1'd1;
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end
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SECTOR_STATE_DATA: begin
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sec_state <= SECTOR_STATE_GAP;
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sec_byte_cnt <= SECTOR_GAP_LEN-1'd1;
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if(current_sector == SECTOR_BASE+SPT-1)
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current_sector <= SECTOR_BASE;
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else
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current_sector <= sector + 4'd1;
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end
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SECTOR_STATE_DATA: begin
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sec_state <= SECTOR_STATE_GAP;
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sec_byte_cnt <= sector_gap_len-1'd1;
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if(current_sector == sector_base+spt-1)
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current_sector <= sector_base;
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else
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current_sector <= sector + 1'd1;
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end
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default:
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sec_state <= SECTOR_STATE_GAP;
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default:
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sec_state <= SECTOR_STATE_GAP;
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endcase
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end else
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sec_byte_cnt <= sec_byte_cnt - 10'd1;
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end
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end
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endcase
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end else
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sec_byte_cnt <= sec_byte_cnt - 10'd1;
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end
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end
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end
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// ================================================================
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@@ -187,7 +195,7 @@ always @(posedge clk) begin
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if (byte_clk_en) begin
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index_pulse_start <= 1'b0;
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||||
if(byte_cnt == BPT-1) begin
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||||
if(byte_cnt == ((hd ? BPTHD : BPTDD)-1'd1)) begin
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byte_cnt <= 0;
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index_pulse_start <= 1'b1;
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end else
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@@ -217,41 +225,41 @@ end
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localparam SPIN_UP_CLKS = SYS_CLK/1000*SPINUP;
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localparam SPIN_DOWN_CLKS = SYS_CLK/1000*SPINDOWN;
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reg [31:0] spin_up_counter;
|
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||||
// internal motor on signal that is only true if the drive is selected
|
||||
wire motor_on_sel = motor_on && select;
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||||
|
||||
// data rate determines rotation speed
|
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reg [31:0] rate = 0;
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||||
reg [31:0] rate /* verilator public */ = 0;
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||||
reg motor_onD;
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||||
|
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always @(posedge clk) begin
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||||
motor_onD <= motor_on_sel;
|
||||
motor_onD <= motor_on_sel;
|
||||
|
||||
// reset spin_up counter whenever motor state changes
|
||||
if(motor_onD != motor_on_sel)
|
||||
spin_up_counter <= 32'd0;
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||||
else begin
|
||||
spin_up_counter <= spin_up_counter + RATE;
|
||||
// reset spin_up counter whenever motor state changes
|
||||
if(motor_onD != motor_on_sel)
|
||||
spin_up_counter <= 32'd0;
|
||||
else begin
|
||||
spin_up_counter <= spin_up_counter + (hd ? RATEHD : RATEDD);
|
||||
|
||||
if(motor_on_sel) begin
|
||||
// spinning up
|
||||
if(spin_up_counter > SPIN_UP_CLKS) begin
|
||||
if(rate < RATE)
|
||||
rate <= rate + 32'd1;
|
||||
spin_up_counter <= spin_up_counter - (SPIN_UP_CLKS - RATE);
|
||||
end
|
||||
end else begin
|
||||
// spinning down
|
||||
if(spin_up_counter > SPIN_DOWN_CLKS) begin
|
||||
if(rate > 0)
|
||||
rate <= rate - 32'd1;
|
||||
spin_up_counter <= spin_up_counter - (SPIN_DOWN_CLKS - RATE);
|
||||
end
|
||||
end // else: !if(motor_on)
|
||||
end // else: !if(motor_onD != motor_on)
|
||||
if(motor_on_sel) begin
|
||||
// spinning up
|
||||
if(spin_up_counter > SPIN_UP_CLKS) begin
|
||||
if(rate < (hd ? RATEHD : RATEDD))
|
||||
rate <= rate + 32'd1;
|
||||
spin_up_counter <= spin_up_counter - (SPIN_UP_CLKS - (hd ? RATEHD : RATEDD));
|
||||
end
|
||||
end else begin
|
||||
// spinning down
|
||||
if(spin_up_counter > SPIN_DOWN_CLKS) begin
|
||||
if(rate > 0)
|
||||
rate <= rate - 32'd1;
|
||||
spin_up_counter <= spin_up_counter - (SPIN_DOWN_CLKS - (hd ? RATEHD : RATEDD));
|
||||
end
|
||||
end // else: !if(motor_on)
|
||||
end // else: !if(motor_onD != motor_on)
|
||||
end
|
||||
|
||||
|
||||
// Generate a data clock from the system clock. This depends on motor
|
||||
// speed and reaches the full rate when the disk rotates at 300RPM. No
|
||||
// valid data can be read until the disk has reached it's full speed.
|
||||
@@ -259,13 +267,13 @@ reg data_clk;
|
||||
reg data_clk_en;
|
||||
reg [31:0] clk_cnt;
|
||||
always @(posedge clk) begin
|
||||
data_clk_en <= 0;
|
||||
if(clk_cnt + rate > SYS_CLK/2) begin
|
||||
clk_cnt <= clk_cnt - (SYS_CLK/2 - rate);
|
||||
data_clk <= !data_clk;
|
||||
if (~data_clk) data_clk_en <= 1;
|
||||
end else
|
||||
clk_cnt <= clk_cnt + rate;
|
||||
end
|
||||
|
||||
data_clk_en <= 0;
|
||||
if(clk_cnt + rate > SYS_CLK/2) begin
|
||||
clk_cnt <= clk_cnt - (SYS_CLK/2 - rate);
|
||||
data_clk <= !data_clk;
|
||||
if (~data_clk) data_clk_en <= 1;
|
||||
end else
|
||||
clk_cnt <= clk_cnt + rate;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user