Archie: update SDRAM testbench

cores/archie/bench/sdram/sdram.cpp

@@ -5,6 +5,7 @@
 #include "edge.h"
 
 #include <iostream>
+#include <iomanip>
 #include <string>
 
 
@@ -130,10 +131,40 @@ int wb_read32(int address)
     uut->wb_we  = 0;
     uut->wb_cti = 0;
 
-    
     return uut->wb_dat_o;
 }
 
+int wb_write32(int address, int data)
+{
+    wait_ready();
+    wait_nack();
+
+    while (!Verilated::gotFinish())
+    {
+        if (wb_clk.PosEdge())
+        {
+            uut->wb_adr = address;
+            uut->wb_dat_i = data;
+            uut->wb_sel = 0xF;
+            uut->wb_cyc = 1;
+            uut->wb_stb = 1;
+            uut->wb_we  = 1;
+            uut->wb_cti = 0;
+            break;
+        }
+
+        tick();
+    }
+
+    wait_ack();
+
+    uut->wb_cyc = 0;
+    uut->wb_stb = 0;
+    uut->wb_we  = 0;
+    uut->wb_cti = 0;
+
+    return uut->wb_dat_o;
+}
 
 void wb_read32x4(int address, int result[4])
 {
@@ -218,19 +249,29 @@ int main(int argc, char** argv)
     tick();
     tick();
     wait_ready();
-
-    std::cout << std::hex << wb_read32(0) << std::dec << std::endl;
-    std::cout << std::hex << wb_read32(4) << std::dec << std::endl;
-    std::cout << std::hex << wb_read32(8) << std::dec << std::endl;
-    std::cout << std::hex << wb_read32(12) << std::dec << std::endl;
+    std::cout << "32 bit reads" << std::endl;
+    std::cout << std::setw(8) << std::setfill('0') << std::hex << wb_read32(0) << std::dec << std::endl;
+    std::cout << std::setw(8) << std::setfill('0') << std::hex << wb_read32(4) << std::dec << std::endl;
+    std::cout << std::setw(8) << std::setfill('0') << std::hex << wb_read32(8) << std::dec << std::endl;
+    std::cout << std::setw(8) << std::setfill('0') << std::hex << wb_read32(12) << std::dec << std::endl;
     
     int result[4] = {0,0};
     wb_read32x4(0, result);
+    std::cout << "128 bit read" << std::endl;
+    std::cout << std::setw(8) << std::setfill('0') << std::hex << result[0] << std::dec << std::endl;
+    std::cout << std::setw(8) << std::setfill('0') << std::hex << result[1] << std::dec << std::endl;
+    std::cout << std::setw(8) << std::setfill('0') << std::hex << result[2] << std::dec << std::endl;
+    std::cout << std::setw(8) << std::setfill('0') << std::hex << result[3] << std::dec << std::endl;
 
-    std::cout << std::hex << result[0] << std::dec << std::endl;
-    std::cout << std::hex << result[1] << std::dec << std::endl;
-    std::cout << std::hex << result[2] << std::dec << std::endl;
-    std::cout << std::hex << result[3] << std::dec << std::endl;
+    std::cout << "32 bit write/read back" << std::endl;
+    wb_write32(0xaaaa, 0x01020304);
+    std::cout << std::setw(8) << std::setfill('0') << std::hex << wb_read32(0xaaaa) << std::dec << std::endl;
+    wb_write32(0xbbbb, 0x05060708);
+    std::cout << std::setw(8) << std::setfill('0') << std::hex << wb_read32(0xbbbb) << std::dec << std::endl;
+
+
+    std::cout << std::setw(8) << std::setfill('0') << std::hex << wb_read32(0xaaaa) << std::dec << std::endl;
+    std::cout << std::setw(8) << std::setfill('0') << std::hex << wb_read32(0xbbbb) << std::dec << std::endl;
 
 
     for (int i=0; i < 64; i++)

cores/archie/bench/support/mt48lc16m16a2.v

@@ -201,7 +201,9 @@ module mt48lc16m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
    
 
     initial begin
+`ifndef VERILATOR
         Dq_reg = {data_bits{1'bz}};
+`endif
         Data_in_enable = 0; Data_out_enable = 0;
         Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1;
         Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0;
@@ -1028,7 +1030,7 @@ end
                 2'b10 : Dq_dqm = Bank2[{Row, Col}];
                 2'b11 : Dq_dqm = Bank3[{Row, Col}];
             endcase
-
+`ifndef VERILATOR
             // Dqm operation
             if (Dqm_reg0 [0] == 1'b1) begin
                 Dq_dqm [ 7 : 0] = 8'bz;
@@ -1036,15 +1038,21 @@ end
             if (Dqm_reg0 [1] == 1'b1) begin
                 Dq_dqm [15 : 8] = 8'bz;
             end
-
+`endif
             // Display debug message
             if (Dqm_reg0 !== 2'b11) begin
+`ifdef VERILATOR
+                Dq_reg <= Dq_dqm;
+`else
                 Dq_reg = #tAC Dq_dqm;
+`endif
                 if (Debug) begin
                     $display("%m : at time %t READ : Bank = %h Row = %h, Col = %h, Data = %h", $time, Bank, Row, Col, Dq_reg);
                 end
             end else begin
+`ifndef VERILATOR
                 Dq_reg = #tHZ {data_bits{1'bz}};
+`endif
                 if (Debug) begin
                     $display("%m : at time %t READ : Bank = %h Row = %h, Col = %h, Data = Hi-Z due to DQM", $time, Bank, Row, Col);
                 end