github.com/mist-devel.mist-board
1
0
Fork 0
mirror of https://github.com/mist-devel/mist-board.git synced 2026-02-22 23:07:12 +00:00
Code Issues Releases Wiki Activity

[Archie] Add composite sync switch via the scandoubler switch

Browse Source
This commit is contained in:
Gyorgy Szombathelyi
2019-02-21 23:52:11 +01:00
parent 5510e93b27
commit 51c6754a2f
2 changed files with 12 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
cores/archie/fpga/mist/archimedes_mist_top.v
View File

@@ -97,6 +97,7 @@ wire [7:0] joyA;
wire [7:0] joyB;
wire [1:0] buttons;
wire [1:0] switches;
wire scandoubler_disable;
wire ypbpr;
// the top file should generate the correct clocks for the machine
@@ -147,8 +148,8 @@ assign VGA_R = ypbpr?Pr:osd_r_o;
assign VGA_G = ypbpr? Y:osd_g_o;
assign VGA_B = ypbpr?Pb:osd_b_o;
wire CSync = ~(core_hs ^ core_vs);
assign VGA_HS = ypbpr ? CSync : core_hs;
assign VGA_VS = ypbpr? 1'b1 : core_vs;
assign VGA_HS = (scandoubler_disable | ypbpr) ? CSync : core_hs;
assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : core_vs;
// de-multiplex spi outputs from user_io and data_io
assign SPI_DO = (CONF_DATA0==0)?user_io_sdo:(SPI_SS2==0)?data_io_sdo:1'bZ;
@@ -162,12 +163,13 @@ user_io user_io(
.SPI_MISO (user_io_sdo ), // tristate handling inside user_io
.SPI_MOSI (SPI_DI ),
.SWITCHES (switches ),
.BUTTONS (buttons ),
.ypbpr (ypbpr ),
.SWITCHES (switches ),
.BUTTONS (buttons ),
.scandoubler_disable(scandoubler_disable),
.ypbpr (ypbpr ),
.JOY0 (joyA ),
.JOY1 (joyB ),
.JOY0 (joyA ),
.JOY1 (joyB ),
.kbd_out_data ( kbd_out_data ),
.kbd_out_strobe ( kbd_out_strobe ),

3
cores/archie/fpga/mist/user_io.v
View File

@@ -31,6 +31,7 @@ module user_io (
output [7:0] JOY0,
output [7:0] JOY1,
output scandoubler_disable,
output ypbpr,
input [7:0] kbd_out_data,
@@ -60,7 +61,9 @@ assign JOY1 = joystick_1[7:0];
assign BUTTONS = but_sw[1:0];
assign SWITCHES = but_sw[3:2];
assign scandoubler_disable = but_sw[4];
assign ypbpr = but_sw[5];
// this variant of user_io is for the achie core (type == a6) only
wire [7:0] core_type = 8'ha6;
reg [7:0] spi_byte_out;