mirror of
https://github.com/mist-devel/mist-board.git
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Moved palette handling before scan doubler
This commit is contained in:
harbaum
@@ -5,7 +5,6 @@
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// http://code.google.com/p/mist-board/
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//
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// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
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// Modified by Juan Carlos González Amestoy.
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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@@ -20,6 +19,18 @@
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// original atari video timing
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// mono color
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// pclk 32MHz 16/8MHz
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// hfreq 35.7kHz 15.75kHz
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// vfreq 71.2Hz 50/60Hz
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//
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// avg. values derived from frequencies:
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// hdisp 640 640/320
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// htot 896 1015/507
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// vdisp 400 200
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// vtot 501 315/262
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// TODO:
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// - async timing
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@@ -27,8 +38,8 @@
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// Overscan:
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// http://codercorner.com/fullscrn.txt
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// Examples: automation 000, 001, 097: bottom border
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// automation 168: top + bottom border
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// Examples: automation 000 + 001: bottom border
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// automation 097: top+ bottom border
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module video (
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// system interface
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@@ -81,29 +92,10 @@ module video (
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// deO is the internal display enable signal as used by the mfp. This is used
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// by software to generate a line interrupt and to e.g. do 512 color effects.
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// deO is active low
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assign deO = ~(scan_doubler_enable?sd_de:de);
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assign deO = ~me; // ~(scan_doubler_enable?sd_de:de);
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// similar for hsync
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assign hsO = scan_doubler_enable?sd_hs:(h_state == 2'd0);
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// special de and hs signals while scan doubler is being used
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wire sd_hs = vcnt[0] && (h_state == 2'd0);
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reg sd_de;
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always @(posedge clk) begin
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// begin of de: even line when memory is being read, begin of display phase
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if(!vcnt[0] && (v_state == 2'd3) && (hcnt == t5_h_end))
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sd_de <= 1'b1;
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// end of de: odd line, when memory is being read, end of display phase
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// There's a problem with this shifter: Color table changes affect the
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// VGA image after the scan doubler. Thus the display timing is much faster
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// than in a real ST. We artificially move the irq a little bit (160 clocks)
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// back so the irq latency results in color table changes in the blank/sync phase
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if(vcnt[0] && (v_state == 2'd3) && (hcnt == (t0_h_border_right - 10'd160)))
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sd_de <= 1'b0;
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end
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assign hsO = (st_h_state == 2'd0);
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// ---------------------------------------------------------------------------
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// -------------------------------- video mode -------------------------------
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@@ -164,15 +156,8 @@ wire [2:0] planes = mono?3'd1:(mid?3'd2:3'd4);
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// scandoubler is used for the mid and low rez mode
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wire scan_doubler_enable = mid || low;
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// line buffer for scan doubler for color video modes
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// the color modes have 80 words per line (320*4/16 or 640*2/16) and
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// we need space for two lines -> 160 words
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reg [15:0] sd_buffer0 [63:0];
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reg [15:0] sd_buffer1 [63:0];
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reg [15:0] sd_buffer2 [63:0];
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reg [15:0] sd_buffer3 [63:0];
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reg [6:0] sd_wptr;
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reg [5:0] sd_rptr;
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// line buffer for two lines of 640 pixels rgb data
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reg [8:0] sd_buffer [1279:0];
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reg [1:0] syncmode;
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reg [1:0] syncmode_latch;
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@@ -296,7 +281,7 @@ osd osd (
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// feed ST video signal into OSD
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.clk (clk ),
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.hcnt (hcnt ),
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.hcnt (vga_hcnt ),
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.vcnt (vcnt ),
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.in_r ({stvid_r, stvid_r}),
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.in_g ({stvid_g, stvid_g}),
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@@ -311,15 +296,15 @@ osd osd (
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// ----------------------- monochrome video signal ---------------------------
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// mono uses the lsb of blue palette entry 0 to invert video
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wire [2:0] blue0 = palette_b[0];
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wire mono_bit = blue0[0]^shift0[15];
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wire mono_bit = blue0[0]^shift_0[15];
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wire [2:0] mono_rgb = de?{mono_bit, mono_bit, mono_bit}:3'b100;
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// ------------------------- colour video signal -----------------------------
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// border color is taken from palette[0]
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wire [3:0] index16 = { shift3[15], shift2[15], shift1[15], shift0[15] };
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wire [2:0] color_r = de?palette_r[index16]:palette_r[0];
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wire [2:0] color_g = de?palette_g[index16]:palette_g[0];
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wire [2:0] color_b = de?palette_b[index16]:palette_b[0];
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reg [8:0] color, border_color;
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wire [2:0] color_r = de?color[8:6]:border_color[8:6];
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wire [2:0] color_g = de?color[5:3]:border_color[5:3];
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wire [2:0] color_b = de?color[2:0]:border_color[2:0];
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// --------------- de-multiplex color and mono into one vga signal -----------
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wire [2:0] stvid_r = mono?mono_rgb:color_r;
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@@ -327,15 +312,23 @@ wire [2:0] stvid_g = mono?mono_rgb:color_g;
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wire [2:0] stvid_b = mono?mono_rgb:color_b;
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// shift registers for up to 4 planes
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reg [15:0] shift0, shift1, shift2, shift3;
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reg [15:0] shift_0, shift_1, shift_2, shift_3;
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// this line is to be displayed darker in scanline mode
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wire scanline = scan_doubler_enable && vcnt[0];
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// reading the scan doubler ram results in one extra delay and thus
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// reading it has to look one vga_hcnt cycle into the future
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wire [9:0] vga_hcnt_next = (vga_hcnt == t5_h_end)?10'd0:(vga_hcnt+10'd1);
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always @(posedge clk) begin
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hs <= h_sync_pol ^ ((h_state == 2'd0)?1'b0:1'b1);
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hs <= h_sync_pol ^ ((vga_h_state == 2'd0)?1'b0:1'b1);
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vs <= v_sync_pol ^ ((v_state == 2'd0)?1'b0:1'b1);
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// color data is permanently read from the scan doubler buffers
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color <= sd_buffer[{vga_hcnt_next, !sd_toggle}];
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border_color <= sd_border_color[!sd_toggle];
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// drive video output and apply scanline effect if enabled
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if(!scanline || scanlines == 2'b00) begin //if no scanlines or not a scanline
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video_r <= blank?6'b000000:st_and_osd_r;
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@@ -365,61 +358,12 @@ always @(posedge clk) begin
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if(!scan_doubler_enable) begin
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// hires mode: shift one plane only and reload
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// shift0 register every 16 clocks
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if(hcnt[3:0] == 4'hf) shift0 <= data_latch[0];
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else shift0[15:1] <= shift0[14:0];
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// shift_0 register every 16 clocks
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if(vga_hcnt[3:0] == 4'hf) shift_0 <= data_latch[0];
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else shift_0[15:1] <= shift_0[14:0];
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// TODO: Color modes not using scan doubler
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end else begin
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// double buffered color mode: reload every 32 clocks
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// reset read counter right before data is being read
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if(hcnt == t5_h_end - 10'h1) sd_rptr <= 6'd0;
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// low rez 320x200
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if(low) begin
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// h_state == 2'd3 -> display enable
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// half pixel clock
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if(hcnt[0] == 1'b1) begin
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if(hcnt[4:1] == 4'hf) begin
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// read words for all four planes
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shift0 <= sd_buffer0[{!sd_toggle, sd_rptr[5:1]}];
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shift1 <= sd_buffer1[{!sd_toggle, sd_rptr[5:1]}];
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shift2 <= sd_buffer2[{!sd_toggle, sd_rptr[5:1]}];
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shift3 <= sd_buffer3[{!sd_toggle, sd_rptr[5:1]}];
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sd_rptr <= sd_rptr + 6'd2;
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end else begin
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// shift every second pixel
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shift0[15:1] <= shift0[14:0];
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shift1[15:1] <= shift1[14:0];
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shift2[15:1] <= shift2[14:0];
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shift3[15:1] <= shift3[14:0];
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end
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end
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end
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// med rez 640x200
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else if(mid) begin
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if(hcnt[3:0] == 4'hf) begin
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// read words for all two planes
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if(sd_rptr[0] == 1'b0) begin
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shift0 <= sd_buffer0[{!sd_toggle, sd_rptr[5:1]}];
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shift1 <= sd_buffer1[{!sd_toggle, sd_rptr[5:1]}];
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end else begin
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shift0 <= sd_buffer2[{!sd_toggle, sd_rptr[5:1]}];
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shift1 <= sd_buffer3[{!sd_toggle, sd_rptr[5:1]}];
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end
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sd_rptr <= sd_rptr + 6'd1;
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end else begin
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// shift every pixel
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shift0[15:1] <= shift0[14:0];
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shift1[15:1] <= shift1[14:0];
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shift2[15:1] <= 15'h0000;
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shift3[15:1] <= 15'h0000;
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end
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end
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end
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end
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@@ -439,20 +383,76 @@ always @(posedge clk) begin
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// this is the magic used to do "overscan".
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// the magic actually involves more than writing zero (60hz)
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// within line 200. But this is sufficient for our detection
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if((vcnt == 10'd399)||(vcnt == 10'd400)) begin
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if(vcnt[9:2] == 8'd99) begin
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// syncmode has changed from 1 to 0 (50 to 60 hz)
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if((syncmode[1] == 1'b0) && (last_syncmode == 1'b1))
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overscan_detect <= 1'b1;
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end
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// latch overscan state at topleft screen edge
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if((hcnt == t4_h_border_left) && (vcnt == t10_v_border_top)) begin
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if((vga_hcnt == t4_h_border_left) && (vcnt == t10_v_border_top)) begin
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// save and reset overscan
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overscan <= overscan_detect;
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overscan_detect <= 1'b0;
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end
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end
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// ---------------------------------------------------------------------------
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// ------------------------------- scan doubler ------------------------------
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// ---------------------------------------------------------------------------
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// scan doubler signale indicating first or second buffer used
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wire sd_toggle = vcnt[1];
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// four scan doubler shift registers for up to 4 planes
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reg [15:0] sd_shift_0, sd_shift_1, sd_shift_2, sd_shift_3;
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// register to save the border color for delayed output through scan doubler
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reg [8:0] sd_border_color[2];
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// msb of the shift registers is the index used to access the palette registers
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wire [3:0] sd_index = { sd_shift_3[15], sd_shift_2[15],
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sd_shift_1[15], sd_shift_0[15]};
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always @(posedge clk) begin
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// save border color to cope with only line delay imposed by scan doubler
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if(st_hcnt == t4_h_border_left)
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sd_border_color[sd_toggle] <= {palette_r[0], palette_g[0], palette_b[0]};
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// permanently move data from data_latch into scan doublers shift registers
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if((bus_cycle == 4'd15) && (plane == 2'd0)) begin
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// clear shift registers since some of them may be unused and need to forced to 0
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sd_shift_1 <= 16'h0000;
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sd_shift_2 <= 16'h0000;
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sd_shift_3 <= 16'h0000;
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// load data into shift registers as required by color depth
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sd_shift_0 <= data_latch[0];
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if(planes > 3'd1)
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sd_shift_1 <= data_latch[1];
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if(planes > 3'd2) begin
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sd_shift_2 <= data_latch[2];
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sd_shift_3 <= data_latch[3];
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end
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end else begin
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if((planes == 3'd1) ||
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((planes == 3'd2) && (vga_hcnt[0] == 1'b1)) ||
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((planes == 3'd4) && (vga_hcnt[1:0] == 2'b11))) begin
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sd_shift_0[15:1] <= sd_shift_0[14:0];
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sd_shift_1[15:1] <= sd_shift_1[14:0];
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sd_shift_2[15:1] <= sd_shift_2[14:0];
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sd_shift_3[15:1] <= sd_shift_3[14:0];
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end
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end
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// move data from input buffer into line buffer
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if((st_h_state == 2'd3) && (vga_hcnt[0] == 1'b0)) begin
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sd_buffer[{st_hcnt[9:0], sd_toggle}] <=
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{palette_r[sd_index], palette_g[sd_index], palette_b[sd_index]};
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end
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end
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// ---------------------------------------------------------------------------
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// ------------------------------- memory engine -----------------------------
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// ---------------------------------------------------------------------------
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@@ -468,7 +468,7 @@ reg [1:0] plane;
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reg me, me_v;
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// required pixel offset allowing for prefetch of 1, 2 or 4 planes (16, 32 or 64 pixels)
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wire [9:0] memory_prefetch = { 3'b000, planes, 4'b0000 };
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wire [9:0] memory_prefetch = scan_doubler_enable?{ 4'd0, planes, 3'd0 }:{ 3'd0, planes, 4'd0 };
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wire [9:0] me_h_start = t5_h_end - memory_prefetch;
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wire [9:0] me_h_end = t0_h_border_right - memory_prefetch;
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// line offset required for scan doubler
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@@ -476,64 +476,52 @@ wire [9:0] me_v_offset = scan_doubler_enable?10'd2:10'd0;
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wire [9:0] me_v_start = t11_v_end - me_v_offset;
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wire [9:0] me_v_end = t6_v_border_bot - me_v_offset;
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// scan doubler signale indicating first or second buffer used
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wire sd_toggle = vcnt[1];
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always @(posedge clk) begin
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// line in which memory access is enabled
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// in scan doubler mode two lines ahead of vertical display enable
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if(hcnt == v_event) begin
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if(vga_hcnt == v_event) begin
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if(vcnt == me_v_start) me_v <= 1'b1;
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if(vcnt == me_v_end) me_v <= 1'b0;
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end
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// memory enable signal 16/32/64 bits (16*planes) ahead of display enable (de)
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if(me_v) begin
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if(hcnt == me_h_start) me <= 1'b1;
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if(hcnt == me_h_end) me <= 1'b0;
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if(st_hcnt == me_h_start) me <= 1'b1;
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if(st_hcnt == me_h_end) me <= 1'b0;
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end
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// starting new image at left/top start of border
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if((hcnt == t4_h_border_left) && (vcnt == t10_v_border_top)) begin
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vaddr <= _v_bas_ad;
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// make sure each line starts with plane 0
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if(st_hcnt == me_h_start)
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plane <= 2'd0;
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// starting new image at left/top start of (vga) border, this doesn't matter
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// and is easier than coping with the differnt resultions of the st video
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// modes
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if((vga_hcnt == t4_h_border_left) && (vcnt == t10_v_border_top)) begin
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vaddr <= _v_bas_ad;
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// copy syncmode
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syncmode_latch <= syncmode;
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end else begin
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// ---- scan doubler pointer handling -----
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// reset write pointer only every second line since in color mode a line has
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// twice the bytes per line
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if((hcnt == v_event) && vcnt[0])
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sd_wptr <= 7'd0;
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// read if memory enable is active and only within the video bus cycle
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if(me && (bus_cycle == 3)) begin
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// move data directly into data latch if not using scan doubler ...
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data_latch[plane] <= data;
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// video transfer happens in cycle 3
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if(bus_cycle == 3) begin
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// read if memory enable is active
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if(me) begin
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// move incoming video data into data latch
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data_latch[plane] <= data;
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vaddr <= vaddr + 23'd1;
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end
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// ... and store it in buffer for later scan doubler use
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case(sd_wptr[1:0])
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2'b00: sd_buffer0[{sd_toggle, sd_wptr[6:2]}] <= data;
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2'b01: sd_buffer1[{sd_toggle, sd_wptr[6:2]}] <= data;
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2'b10: sd_buffer2[{sd_toggle, sd_wptr[6:2]}] <= data;
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2'b11: sd_buffer3[{sd_toggle, sd_wptr[6:2]}] <= data;
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endcase
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// increase scan doubler address
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sd_wptr <= sd_wptr + 7'd1;
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// advance plane counter
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if(planes != 1) begin
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plane <= plane + 2'd1;
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if(plane == planes - 2'd1)
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plane <= 2'd0;
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end
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vaddr <= vaddr + 23'd1;
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end
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end
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end
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@@ -542,42 +530,72 @@ end
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// ------------------------- video timing generator --------------------------
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// ---------------------------------------------------------------------------
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reg [9:0] hcnt; // horizontal pixel counter
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reg [9:0] vcnt; // vertical line counter
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// Two horizontal timings are generated: a vga one and a st one. Both are identical
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// without the scan doubler being used (mono mode), but in scan doubler mode the
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// st timing has exactly half the pixel rate as the vga one and all times are exactly
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// twice as long
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reg [9:0] vga_hcnt; // horizontal pixel counter
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reg [1:0] vga_h_state; // 0=sync, 1=blank, 2=border, 3=display
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reg [1:0] h_state; // 0=sync, 1=blank, 2=border, 3=display
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reg [1:0] v_state; // 0=sync, 1=blank, 2=border, 3=display
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reg [9:0] st_hcnt; // horizontal pixel counter
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reg [1:0] st_h_state; // 0=sync, 1=blank, 2=border, 3=display
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// A seperate vertical timing is not needed, vcnt[9:1] is the st line
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reg [9:0] vcnt; // vertical line counter
|
||||
reg [1:0] v_state; // 0=sync, 1=blank, 2=border, 3=display
|
||||
|
||||
// blank level is also used during sync
|
||||
wire blank = (v_state == 2'd1) || (h_state == 2'd1) || (v_state == 2'd0) || (h_state == 2'd0);
|
||||
wire de = (v_state == 2'd3) && (h_state == 2'd3);
|
||||
wire blank = (v_state == 2'd1) || (vga_h_state == 2'd1) || (v_state == 2'd0) || (vga_h_state == 2'd0);
|
||||
wire de = (v_state == 2'd3) && (vga_h_state == 2'd3);
|
||||
|
||||
wire border =
|
||||
((v_state == 2'd2) && ((h_state == 2'd3) || (h_state == 2'd2)) || // top/bottom border
|
||||
(h_state == 2'd2) && ((v_state == 2'd3) || (v_state == 2'd2))); // left/right border
|
||||
((v_state == 2'd2) && ((vga_h_state == 2'd3) || (vga_h_state == 2'd2)) || // top/bottom border
|
||||
(vga_h_state == 2'd2) && ((v_state == 2'd3) || (v_state == 2'd2))); // left/right border
|
||||
|
||||
// time in horizontal timing where vertical states change (at the begin of the left blank phase)
|
||||
wire [9:0] v_event = t3_h_blank_left;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(reset) begin
|
||||
hcnt <= 10'd0;
|
||||
// It is important to reset the vga_hcnt counter here and this way (using reset which is the
|
||||
// plls init signal). This is necessary to keep the video states in sync with the cpus memory
|
||||
// timing.
|
||||
vga_hcnt <= 10'd0;
|
||||
vcnt <= 10'd0;
|
||||
end else begin
|
||||
// ------------- horizontal signal generation -------------
|
||||
if(hcnt == t5_h_end) hcnt <= 10'd0;
|
||||
else hcnt <= hcnt + 10'd1;
|
||||
// ------------- horizontal VGA timing generation -------------
|
||||
if(vga_hcnt == t5_h_end) vga_hcnt <= 10'd0;
|
||||
else vga_hcnt <= vga_hcnt + 10'd1;
|
||||
|
||||
// generate horizontal video signal states
|
||||
if( hcnt == t2_h_sync ) h_state <= 2'd0;
|
||||
if((hcnt == t0_h_border_right) || (hcnt == t4_h_border_left)) h_state <= 2'd2;
|
||||
if((hcnt == t1_h_blank_right) || (hcnt == t3_h_blank_left)) h_state <= 2'd1;
|
||||
if( hcnt == t5_h_end) h_state <= 2'd3;
|
||||
if( vga_hcnt == t2_h_sync ) vga_h_state <= 2'd0;
|
||||
if((vga_hcnt == t0_h_border_right) || (vga_hcnt == t4_h_border_left)) vga_h_state <= 2'd2;
|
||||
if((vga_hcnt == t1_h_blank_right) || (vga_hcnt == t3_h_blank_left)) vga_h_state <= 2'd1;
|
||||
if( vga_hcnt == t5_h_end) vga_h_state <= 2'd3;
|
||||
|
||||
// vertical state changes at end of hsync (begin of left blank)
|
||||
if(hcnt == v_event) begin
|
||||
// ------------- horizontal ST timing generation -------------
|
||||
// Run st timing at full speed if no scan doubler is being used. Otherwise run
|
||||
// it at half speed
|
||||
if((!scan_doubler_enable) || vga_hcnt[0]) begin
|
||||
if(st_hcnt == t5_h_end) begin
|
||||
// changing video modes toggles scan_doubler_enable and will bring
|
||||
// the two hcnt counters out of sync. So we'll resync st_hcnt with vgs_hcnt here
|
||||
if((vga_hcnt == t5_h_end) && (!scan_doubler_enable || !vcnt[0]))
|
||||
st_hcnt <= 10'd0;
|
||||
end else
|
||||
st_hcnt <= st_hcnt + 10'd1;
|
||||
|
||||
// ------------- vertical signal generation -------------
|
||||
// generate horizontal video signal states
|
||||
if( st_hcnt == t2_h_sync ) st_h_state <= 2'd0;
|
||||
if((st_hcnt == t0_h_border_right) || (st_hcnt == t4_h_border_left)) st_h_state <= 2'd2;
|
||||
if((st_hcnt == t1_h_blank_right) || (st_hcnt == t3_h_blank_left)) st_h_state <= 2'd1;
|
||||
if( st_hcnt == t5_h_end) st_h_state <= 2'd3;
|
||||
end
|
||||
|
||||
// vertical state changes at end of hsync (begin of left blank)
|
||||
if(vga_hcnt == v_event) begin
|
||||
|
||||
// ------------- vertical timing generation -------------
|
||||
// increase vcnt
|
||||
if(vcnt == t11_v_end) vcnt <= 10'd0;
|
||||
else vcnt <= vcnt + 10'd1;
|
||||
|
||||
Reference in New Issue
Block a user