C16: simplify IEC connection, update 1541 CS from C64

cores/c16/c1541/c1541_logic.vhd

@@ -20,9 +20,9 @@ entity c1541_logic is
     reset           : in std_logic;
 
     -- serial bus
-    sb_data_oe      : out std_logic;
+    sb_data_oe      : buffer std_logic;
     sb_data_in      : in std_logic;
-    sb_clk_oe       : out std_logic;
+    sb_clk_oe       : buffer std_logic;
     sb_clk_in       : in std_logic;
     sb_atn_oe       : out std_logic;
     sb_atn_in       : in std_logic;
@@ -120,6 +120,7 @@ architecture SYN of c1541_logic is
   signal uc3_pa_oe      : std_logic_vector(7 downto 0);
   signal uc3_pb_oe      : std_logic_vector(7 downto 0);
 
+  signal cpu_a_slice    : std_logic_vector(3 downto 0);
 begin
 
   reset_n <= not reset;
@@ -137,14 +138,24 @@ begin
   end process;
 
   -- decode logic
-  -- RAM $0000-$07FF (2KB)
-  ram_cs <= '1' when STD_MATCH(cpu_a(15 downto 0), "00000-----------") else '0';
-  -- UC1 (VIA6522) $1800-$180F
-  uc1_cs2_n <= '0' when STD_MATCH(cpu_a(15 downto 0), "000110000000----") else '1';
-  -- UC3 (VIA6522) $1C00-$1C0F
-  uc3_cs2_n <= '0' when STD_MATCH(cpu_a(15 downto 0), "000111000000----") else '1';
-  -- ROM $C000-$FFFF (16KB)
-  rom_cs <= '1' when STD_MATCH(cpu_a(15 downto 0), "11--------------") else '0';
+  process (cpu_a, cpu_a_slice)
+  begin
+    ram_cs <= '0';
+    uc1_cs2_n <= '1';
+    uc3_cs2_n <= '1';
+    rom_cs <= cpu_a(15);  -- ROM $C000-$FFFF (16KB)
+
+    -- address decoder logic using a 74LS42 BCD decoder
+    cpu_a_slice <= cpu_a(15)&cpu_a(12)&cpu_a(11)&cpu_a(10);
+    case cpu_a_slice is
+      when "0000" => ram_cs <= '1';     -- RAM $0000-$07FF (2KB) + mirrors
+      when "0001" => ram_cs <= '1';     -- RAM $0000-$07FF (2KB) + mirrors
+      when "0110" => uc1_cs2_n <= '0';  -- UC1 (VIA6522) $1800-$180F + mirrors
+      when "0111" => uc3_cs2_n <= '0';  -- UC3 (VIA6522) $1C00-$1C0F + mirrors
+      when others => null;
+    end case;
+
+  end process;
 
   -- qualified write signals
   ram_wr <= '1' when ram_cs = '1' and cpu_rw_n = '0' else '0';
@@ -161,19 +172,13 @@ begin
   uc1_pa_i(0) <= tr00_sense_n;
   uc1_pa_i(7 downto 1) <= (others => '0');  -- NC
   -- PB
-  uc1_pb_i(0) <=  '1' when sb_data_in = '0' else
-                  '1' when (uc1_pb_o(1) = '1' and uc1_pb_oe_n(1) = '0') else  -- DAR comment : external OR wired
-                  '1' when atn = '1' else                                     -- DAR comment : external OR wired 
-                  '0';
-  sb_data_oe <=   '1' when (uc1_pb_o(1) = '1' and uc1_pb_oe_n(1) = '0') else
-                  '1' when atn = '1' else
-                  '0';
-  uc1_pb_i(2) <=  '1' when sb_clk_in = '0' else
-                  '1' when (uc1_pb_o(3) = '1' and uc1_pb_oe_n(3) = '0') else  -- DAR comment : external OR wired
-                  '0';
-  sb_clk_oe <=    '1' when (uc1_pb_o(3) = '1' and uc1_pb_oe_n(3) = '0') else '0';
-		
-  atna <= uc1_pb_o(4); -- when uc1_pc_oe = '1'
+
+  uc1_pb_i(0) <=  not (sb_data_in and sb_data_oe);
+  sb_data_oe <=   not (uc1_pb_o(1) or uc1_pb_oe_n(1)) and not atn;
+  uc1_pb_i(2) <=  not (sb_clk_in and sb_clk_oe);
+  sb_clk_oe <=    not (uc1_pb_o(3) or uc1_pb_oe_n(3));
+
+  atna <= uc1_pb_o(4) or uc1_pb_oe_n(4);
   uc1_pb_i(6 downto 5) <= DEVICE_SELECT xor ds;     -- allows override
   uc1_pb_i(7) <= not sb_atn_in;
 

cores/c16/c1541/c1541_sd.vhd

@@ -161,9 +161,9 @@ begin
     sb_clk_oe  => iec_clk_o,
     sb_atn_oe  => iec_atn_o,
 		
-    sb_data_in => not iec_data_i,
-    sb_clk_in  => not iec_clk_i,
-    sb_atn_in  => not iec_atn_i,
+    sb_data_in => iec_data_i,
+    sb_clk_in  => iec_clk_i,
+    sb_atn_in  => iec_atn_i,
     
     -- drive-side interface
     ds              => "00",     -- device select

cores/c16/c16.v

@@ -291,11 +291,11 @@ assign ram_data=(RW & ~CAS)?DIN:8'hff;				// internal ram_data should be 0xff wh
 
 // connect IEC bus
 
-assign IEC_DATAOUT=port_out[0];
-assign port_in[7]=IEC_DATAIN;
-assign IEC_CLKOUT=port_out[1];
-assign port_in[6]=IEC_CLKIN;
-assign IEC_ATNOUT=port_out[2];
+assign IEC_DATAOUT=~port_out[0];
+assign port_in[7]=IEC_DATAIN & IEC_DATAOUT;
+assign IEC_CLKOUT=~port_out[1];
+assign port_in[6]=IEC_CLKIN & IEC_CLKOUT;
+assign IEC_ATNOUT=~port_out[2];
 //assign ATN=IEC_ATNIN;
 assign IEC_RESET=sreset;
 

cores/c16/c16_mist.v

@@ -653,9 +653,9 @@ C16 #(.INTERNAL_ROM(0)) c16 (
 	.basic_dl_write  ( basic_dl_wr    ),
 	
 	.IEC_DATAOUT ( c16_iec_data_o ),
-	.IEC_DATAIN  ( !c16_iec_data_i ),
+	.IEC_DATAIN  ( c16_iec_data_i ),
 	.IEC_CLKOUT  ( c16_iec_clk_o ),
-	.IEC_CLKIN   ( !c16_iec_clk_i ),
+	.IEC_CLKIN   ( c16_iec_clk_i ),
 	.IEC_ATNOUT  ( c16_iec_atn_o ),
 	.IEC_RESET   ( ),
 
@@ -818,17 +818,17 @@ wire c16_iec_atn_o;
 wire c16_iec_data_o;
 wire c16_iec_clk_o;
 
-wire c16_iec_atn_i  = !((!c16_iec_atn_o)  & (!c1541_iec_atn_o) );
-wire c16_iec_data_i = !((!c16_iec_data_o) & (!c1541_iec_data_o));
-wire c16_iec_clk_i  = !((!c16_iec_clk_o)  & (!c1541_iec_clk_o) );
+wire c16_iec_atn_i  = c1541_iec_atn_o;
+wire c16_iec_data_i = c1541_iec_data_o;
+wire c16_iec_clk_i  = c1541_iec_clk_o;
 
 wire c1541_iec_atn_o;
 wire c1541_iec_data_o;
 wire c1541_iec_clk_o;
 
-wire c1541_iec_atn_i  = c16_iec_atn_i;
-wire c1541_iec_data_i = c16_iec_data_i;
-wire c1541_iec_clk_i  = c16_iec_clk_i;
+wire c1541_iec_atn_i  = c16_iec_atn_o;
+wire c1541_iec_data_i = c16_iec_data_o;
+wire c1541_iec_clk_i  = c16_iec_clk_o;
 
 c1541_sd c1541_sd (
 	.clk32 ( clk32 ),