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Remove orphan sources

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This commit is contained in:
Gyorgy Szombathelyi
2019-03-19 10:05:33 +01:00
parent 2117e192da
commit 6daeb76733
82 changed files with 0 additions and 19521 deletions
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274
cores/arcade/pacman/pace/src/pace/pace_pkg.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
package pace_pkg is
--
-- PACE constants which *MUST* be defined
--
type PACETargetType is
(
PACE_TARGET_NANOBOARD_NB1,
PACE_TARGET_DE0,
PACE_TARGET_DE0_NANO, -- EP4CE22
PACE_TARGET_DE1,
PACE_TARGET_DE2,
PACE_TARGET_DE2_70, -- EP2C70
PACE_TARGET_DE2_115, -- EP4CE115
PACE_TARGET_P2, -- A02 build
PACE_TARGET_P2A, -- A04/A build (SRAM byte selects)
PACE_TARGET_P3M,
PACE_TARGET_S3A_700, -- Spartan 3A/N Starter Kit
PACE_TARGET_RC10,
PACE_TARGET_NX2_12,
PACE_TARGET_NEXYS_3, -- Digilent S6 board
PACE_TARGET_CYC3DEV,
PACE_TARGET_CYC5GXDEV,
PACE_TARGET_COCO3PLUS,
PACE_TARGET_S5A,
PACE_TARGET_CARTEBLANCHE_250,
PACE_TARGET_CARTEBLANCHE_500,
PACE_TARGET_BEMICRO,
PACE_TARGET_MIST,
PACE_TARGET_OPENEP3C16,
PACE_TARGET_S5A_R2_EP4C,
PACE_TARGET_S5A_R2_EP3SL,
PACE_TARGET_S5A_R2B0_EP4C,
PACE_TARGET_S5A_R2B0_EP3SL,
PACE_TARGET_S5A_R2C0_EP4C,
PACE_TARGET_S5A_R2C0_EP3SL,
PACE_TARGET_S5L_A0_EP4C,
PACE_TARGET_S5L_A0_EP3SL
);
type PACEFpgaVendor_t is
(
PACE_FPGA_VENDOR_ALTERA,
PACE_FPGA_VENDOR_XILINX,
PACE_FPGA_VENDOR_LATTICE
);
type PACEFpgaFamily_t is
(
PACE_FPGA_FAMILY_CYCLONE1,
PACE_FPGA_FAMILY_CYCLONE2,
PACE_FPGA_FAMILY_CYCLONE3,
PACE_FPGA_FAMILY_CYCLONE4,
PACE_FPGA_FAMILY_CYCLONE5,
PACE_FPGA_FAMILY_CYCLONE6,
PACE_FPGA_FAMILY_STRATIX_III,
PACE_FPGA_FAMILY_SPARTAN3,
PACE_FPGA_FAMILY_SPARTAN3A,
PACE_FPGA_FAMILY_SPARTAN3E
);
type PACEJamma_t is
(
PACE_JAMMA_NONE,
PACE_JAMMA_MAPLE,
PACE_JAMMA_NGC,
PACE_JAMMA_PS2
);
-- Types
type ByteArrayType is array (natural range <>) of std_logic_vector(7 downto 0);
type from_CLKRST_t is record
arst : std_logic;
arst_n : std_logic;
rst : std_logic_vector(0 to 3);
clk_ref : std_logic; --reference clock
clk : std_logic_vector(0 to 3);
end record;
-- maximums from the DE2 target
constant PACE_NUM_SWITCHES : natural := 18;
subtype from_SWITCHES_t is std_logic_vector(PACE_NUM_SWITCHES-1 downto 0);
constant PACE_NUM_BUTTONS : natural := 4;
subtype from_BUTTONS_t is std_logic_vector(PACE_NUM_BUTTONS-1 downto 0);
constant PACE_NUM_LEDS : natural := 18;
subtype to_LEDS_t is std_logic_vector(PACE_NUM_LEDS-1 downto 0);
--
-- JAMMA interface data structures
-- - note: all signals are active LOW
--
type from_JAMMA_player_t is record
start : std_logic;
up : std_logic;
down : std_logic;
left : std_logic;
right : std_logic;
button : std_logic_vector(1 to 5);
end record;
type from_JAMMA_player_a is array (natural range <>) of from_JAMMA_player_t;
type from_JAMMA_t is record
coin_cnt : std_logic_vector(1 to 2);
service : std_logic;
tilt : std_logic;
test : std_logic;
coin : std_logic_vector(1 to 2);
p : from_JAMMA_player_a(1 to 2);
end record;
--
-- INPUTS
--
subtype analogue_in_t is std_logic_vector(9 downto 0);
type analogue_in_a is array (natural range <>) of analogue_in_t;
type from_INPUTS_t is record
ps2_kclk : std_logic;
ps2_kdat : std_logic;
ps2_mclk : std_logic;
ps2_mdat : std_logic;
jamma_n : from_JAMMA_t;
-- up to 4 10-bit analgue inputs
analogue : analogue_in_a(1 to 4);
end record;
type in8_t is record
d : std_logic_vector(7 downto 0);
end record;
type from_MAPPED_INPUTS_t is array (natural range <>) of in8_t;
--
-- SRAM interface data structure
--
type from_SRAM_t is record
d : std_logic_vector(31 downto 0);
end record;
type to_SRAM_t is record
a : std_logic_vector(23 downto 0);
d : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0);
cs : std_logic;
oe : std_logic;
we : std_logic;
end record;
function NULL_TO_SRAM return to_SRAM_t;
--
-- FLASH interface data structure
--
type from_FLASH_t is record
d : std_logic_vector(15 downto 0);
end record;
type to_FLASH_t is record
a : std_logic_vector(21 downto 0);
d : std_logic_vector(15 downto 0);
we : std_logic;
cs : std_logic;
oe : std_logic;
end record;
function NULL_TO_FLASH return to_FLASH_t;
type from_AUDIO_t is record
clk : std_logic;
end record;
type to_AUDIO_t is record
clk : std_logic;
ldata : std_logic_vector(15 downto 0);
rdata : std_logic_vector(15 downto 0);
end record;
function NULL_TO_AUDIO return to_AUDIO_t;
type from_SPI_t is record
din : std_logic;
end record;
type to_SPI_t is record
clk : std_logic;
mode : std_logic;
sel : std_logic;
ena : std_logic;
dout : std_logic;
end record;
function NULL_TO_SPI return to_SPI_t;
type to_SERIAL_t is record
txd : std_logic;
rts : std_logic;
end record;
function NULL_TO_SERIAL return to_SERIAL_t;
type from_SERIAL_t is record
dcd : std_logic;
rxd : std_logic;
cts : std_logic;
end record;
constant PACE_NUM_GPI : natural := 72;
subtype from_GP_t is std_logic_vector(PACE_NUM_GPI-1 downto 0);
constant PACE_NUM_GPO : natural := PACE_NUM_GPI;
type to_GP_t is record
d : std_logic_vector(PACE_NUM_GPO-1 downto 0);
oe : std_logic_vector(PACE_NUM_GPO-1 downto 0);
end record;
function NULL_TO_GP return to_GP_t;
subtype SND_A_t is std_logic_vector(7 downto 0);
subtype SND_D_t is std_logic_vector(7 downto 0);
type to_SOUND_t is record
a : SND_A_t;
d : SND_D_t;
rd : std_logic;
wr : std_logic;
end record;
type from_SOUND_t is record
d : SND_D_t;
end record;
function NULL_TO_SOUND return to_SOUND_t;
--
-- OSD interface data structure
--
type from_OSD_t is record
d : std_logic_vector(7 downto 0);
end record;
function NULL_FROM_OSD return from_OSD_t;
type to_OSD_t is record
en : std_logic;
a : std_logic_vector(7 downto 0);
d : std_logic_vector(7 downto 0);
we : std_logic;
end record;
function NULL_TO_OSD return to_OSD_t;
-- create a constant that automatically determines
-- whether this is simulation or synthesis
constant IN_SIMULATION : BOOLEAN := false
-- synthesis translate_off
or true
-- synthesis translate_on
;
constant IN_SYNTHESIS : boolean := not IN_SIMULATION;
end;

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cores/arcade/pacman/pace/src/target/mist/custom_io.vhd
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library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.target_pkg.all;
use work.platform_pkg.all;
use work.project_pkg.all;
entity custom_io is
port
(
project_i : out from_PROJECT_IO_t;
project_o : in to_PROJECT_IO_t;
platform_i : out from_PLATFORM_IO_t;
platform_o : in to_PLATFORM_IO_t;
target_i : out from_TARGET_IO_t;
target_o : in to_TARGET_IO_t
);
end entity custom_io;
architecture SYN of custom_io is
begin
end architecture SYN;

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cores/arcade/pacman/pace/src/target/mist/target_pkg.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.pace_pkg.all;
package target_pkg is
--
-- PACE constants which *MUST* be defined
--
constant PACE_TARGET : PACETargetType := PACE_TARGET_MIST;
constant PACE_FPGA_VENDOR : PACEFpgaVendor_t := PACE_FPGA_VENDOR_ALTERA;
constant PACE_FPGA_FAMILY : PACEFpgaFamily_t := PACE_FPGA_FAMILY_CYCLONE3;
constant PACE_CLKIN0 : natural := 27;
constant PACE_HAS_SPI : boolean := false;
--
-- DE1-specific constants
--
type from_TARGET_IO_t is record
not_used : std_logic;
end record;
type to_TARGET_IO_t is record
not_used : std_logic;
end record;
end;

271
cores/arcade/pacman/pace/src/target/mist/target_top.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.pace_pkg.all;
use work.sdram_pkg.all;
use work.video_controller_pkg.all;
use work.maple_pkg.all;
use work.gamecube_pkg.all;
use work.project_pkg.all;
use work.platform_pkg.all;
use work.target_pkg.all;
entity target_top is
port
(
--//////////////////// Clock Input ////////////////////
CLOCK_27 : in std_logic_vector(1 downto 0); -- 50 MHz
--//////////////////////// SPI ////////////////////////
SPI_SCK : in std_logic;
SPI_DI : in std_logic;
SPI_DO : out std_logic;
CONF_DATA0 : in std_logic;
--//////////////////////// Speaker ////////////////////////
AUDIO_L : out std_logic;
AUDIO_R : out std_logic;
--//////////////////// VGA ////////////////////////////
VGA_VS : out std_logic; -- VGA H_SYNC
VGA_HS : out std_logic; -- VGA V_SYNC
VGA_R : out std_logic_vector(5 downto 0); -- VGA Red[3:0]
VGA_G : out std_logic_vector(5 downto 0); -- VGA Green[3:0]
VGA_B : out std_logic_vector(5 downto 0); -- VGA Blue[3:0]
SDRAM_nCS : out std_logic
-- DATA0 : in std_logic; -- DATA0
);
end target_top;
architecture SYN of target_top is
component user_io
port ( SPI_CLK, SPI_SS_IO, SPI_MOSI :in std_logic;
SPI_MISO : out std_logic;
JOY0 : out std_logic_vector(5 downto 0);
SWITCHES : out std_logic_vector(1 downto 0);
BUTTONS : out std_logic_vector(1 downto 0);
CORE_TYPE : in std_logic_vector(7 downto 0)
);
end component user_io;
signal init : std_logic := '1';
signal clock_50 : std_logic;
signal clkrst_i : from_CLKRST_t;
signal buttons_i : from_BUTTONS_t;
signal switches_i : from_SWITCHES_t;
signal leds_o : to_LEDS_t;
signal inputs_i : from_INPUTS_t;
signal flash_i : from_FLASH_t;
signal flash_o : to_FLASH_t;
signal sram_i : from_SRAM_t;
signal sram_o : to_SRAM_t;
signal sdram_i : from_SDRAM_t;
signal sdram_o : to_SDRAM_t;
signal video_i : from_VIDEO_t;
signal video_o : to_VIDEO_t;
signal audio_i : from_AUDIO_t;
signal audio_o : to_AUDIO_t;
signal ser_i : from_SERIAL_t;
signal ser_o : to_SERIAL_t;
signal project_i : from_PROJECT_IO_t;
signal project_o : to_PROJECT_IO_t;
signal platform_i : from_PLATFORM_IO_t;
signal platform_o : to_PLATFORM_IO_t;
signal target_i : from_TARGET_IO_t;
signal target_o : to_TARGET_IO_t;
signal joystick : std_logic_vector(5 downto 0);
signal switches : std_logic_vector(1 downto 0);
signal buttons : std_logic_vector(1 downto 0);
--//********************
begin
SDRAM_nCS <= '1'; -- don't select SDRAM
-- // Need Clock 50Mhz to Clock 27Mhz
BLK_CLOCKING : block
begin
clkrst_i.clk_ref <= CLOCK_27(0);
GEN_PLL : if PACE_HAS_PLL generate
pll_27_inst : entity work.pllclk_ez --entity work.pllclk_ez --entity work.pll
port map
(
inclk0 => CLOCK_27(0),
c0 => clkrst_i.clk(0), --30Mhz
c1 => clkrst_i.clk(1), --40Mhz
c3 => clock_50, --40Mhz
c4 => clkrst_i.clk(2) --18.46Mhz
);
end generate GEN_PLL;
end block BLK_CLOCKING;
-- FPGA STARTUP
-- should extend power-on reset if registers init to '0'
process (clock_50)
variable count : std_logic_vector (11 downto 0) := (others => '0');
begin
if rising_edge(clock_50) then
if count = X"FFF" then
init <= '0';
else
count := count + 1;
init <= '1';
end if;
end if;
end process;
clkrst_i.arst <= init;
clkrst_i.arst_n <= not clkrst_i.arst;
GEN_RESETS : for i in 0 to 3 generate
process (clkrst_i.clk(i), clkrst_i.arst)
variable rst_r : std_logic_vector(2 downto 0) := (others => '0');
begin
if clkrst_i.arst = '1' then
rst_r := (others => '1');
elsif rising_edge(clkrst_i.clk(i)) then
rst_r := rst_r(rst_r'left-1 downto 0) & '0';
end if;
clkrst_i.rst(i) <= rst_r(rst_r'left);
end process;
end generate GEN_RESETS;
-- inputs
user_io_d : user_io
port map
(
SPI_CLK => SPI_SCK,
SPI_SS_IO => CONF_DATA0,
SPI_MISO => SPI_DO,
SPI_MOSI => SPI_DI,
JOY0 => joystick,
SWITCHES => switches,
BUTTONS => buttons,
CORE_TYPE => X"a2" -- PACE core type
);
switches_i(0) <= switches(0);
switches_i(1) <= switches(1);
GEN_NO_JAMMA : if PACE_JAMMA = PACE_JAMMA_NONE generate
inputs_i.jamma_n.coin(1) <= not buttons(0);
inputs_i.jamma_n.p(1).start <= not buttons(1);
inputs_i.jamma_n.p(1).up <= not joystick(3);
inputs_i.jamma_n.p(1).down <= not joystick(2);
inputs_i.jamma_n.p(1).left <= not joystick(1);
inputs_i.jamma_n.p(1).right <= not joystick(0);
inputs_i.jamma_n.p(1).button(1) <= not joystick(4);
inputs_i.jamma_n.p(1).button(2) <= not joystick(5);
inputs_i.jamma_n.p(1).button(3) <= '1';
inputs_i.jamma_n.p(1).button(4) <= '1';
inputs_i.jamma_n.p(1).button(5) <= '1';
end generate GEN_NO_JAMMA;
-- not currently wired to any inputs
inputs_i.jamma_n.coin_cnt <= (others => '1');
inputs_i.jamma_n.coin(2) <= '1';
inputs_i.jamma_n.p(2).start <= '1';
inputs_i.jamma_n.p(2).up <= '1';
inputs_i.jamma_n.p(2).down <= '1';
inputs_i.jamma_n.p(2).left <= '1';
inputs_i.jamma_n.p(2).right <= '1';
inputs_i.jamma_n.p(2).button <= (others => '1');
inputs_i.jamma_n.service <= '1';
inputs_i.jamma_n.tilt <= '1';
inputs_i.jamma_n.test <= '1';
BLK_VIDEO : block
begin
video_i.clk <= clkrst_i.clk(1); -- by convention
video_i.clk_ena <= '1';
video_i.reset <= clkrst_i.rst(1);
VGA_R <= video_o.rgb.r(video_o.rgb.r'left downto video_o.rgb.r'left-5);
VGA_G <= video_o.rgb.g(video_o.rgb.g'left downto video_o.rgb.g'left-5);
VGA_B <= video_o.rgb.b(video_o.rgb.b'left downto video_o.rgb.b'left-5);
VGA_HS <= video_o.hsync;
VGA_VS <= video_o.vsync;
end block BLK_VIDEO;
BLK_AUDIO : block
begin
dacl : entity work.sigma_delta_dac
port map (
clk => CLOCK_27(0),
din => audio_o.ldata(15 downto 8),
dout => AUDIO_L
);
dacr : entity work.sigma_delta_dac
port map (
clk => CLOCK_27(0),
din => audio_o.rdata(15 downto 8),
dout => AUDIO_R
);
end block BLK_AUDIO;
pace_inst : entity work.pace
port map
(
-- clocks and resets
clkrst_i => clkrst_i,
-- misc inputs and outputs
buttons_i => buttons_i,
switches_i => switches_i,
leds_o => open,
-- controller inputs
inputs_i => inputs_i,
-- external ROM/RAM
flash_i => flash_i,
flash_o => flash_o,
sram_i => sram_i,
sram_o => sram_o,
sdram_i => sdram_i,
sdram_o => sdram_o,
-- VGA video
video_i => video_i,
video_o => video_o,
-- sound
audio_i => audio_i,
audio_o => audio_o,
-- SPI (flash)
spi_i.din => '0',
spi_o => open,
-- serial
ser_i => ser_i,
ser_o => ser_o,
-- custom i/o
project_i => project_i,
project_o => project_o,
platform_i => platform_i,
platform_o => platform_o,
target_i => target_i,
target_o => target_o
);
end SYN;

72
cores/arcade/pacman/pace/src/target/mist/user_io.v
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module user_io(
input SPI_CLK,
input SPI_SS_IO,
output reg SPI_MISO,
input SPI_MOSI,
input [7:0] CORE_TYPE,
output [5:0] JOY0,
output [5:0] JOY1,
output [1:0] BUTTONS,
output [1:0] SWITCHES
);
reg [6:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [5:0] joystick0;
reg [5:0] joystick1;
reg [3:0] but_sw;
assign JOY0 = joystick0;
assign JOY1 = joystick1;
assign BUTTONS = but_sw[1:0];
assign SWITCHES = but_sw[3:2];
always@(negedge SPI_CLK) begin
if(SPI_SS_IO == 1) begin
SPI_MISO <= 1'bZ;
end else begin
if(cnt < 8) begin
SPI_MISO <= CORE_TYPE[7-cnt];
end else begin
SPI_MISO <= 1'bZ;
end
end
end
always@(posedge SPI_CLK) begin
if(SPI_SS_IO == 1) begin
cnt <= 0;
end else begin
sbuf[6:1] <= sbuf[5:0];
sbuf[0] <= SPI_MOSI;
cnt <= cnt + 1;
if(cnt == 7) begin
cmd[7:1] <= sbuf;
cmd[0] <= SPI_MOSI;
end
if(cnt == 15) begin
if(cmd == 1) begin
but_sw[3:1] <= sbuf[2:0];
but_sw[0] <= SPI_MOSI;
end
if(cmd == 2) begin
joystick0[5:1] <= sbuf[4:0];
joystick0[0] <= SPI_MOSI;
end
if(cmd == 3) begin
joystick1[5:1] <= sbuf[4:0];
joystick1[0] <= SPI_MOSI;
end
end
end
end
// always@(posedge clk2) begin
// LED <= ~LED;
// end
endmodule

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cores/arcade/pacman/pace/synth/platform/pacman/mist/Makefile
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# fpga makefile
# 2012, rok.krajnc@gmail.com
### programs ###
MAP=quartus_map
FIT=quartus_fit
ASM=quartus_asm
PGM=quartus_pgm
### project ###
PROJECT=pacman
### build rules ###
# all
all:
@echo Making FPGA programming files ...
@make map
@make fit
@make asm
map:
@echo Running mapper ...
@$(MAP) $(PROJECT)
fit:
@echo Running fitter ...
@$(FIT) $(PROJECT)
asm:
@echo Running assembler ...
@$(ASM) $(PROJECT)
run:
@$(PGM) -c USB-Blaster -m jtag -o "p;$(PROJECT).sof"
# clean
clean:
@echo clean
@rm -rf ./out/
@rm -rf ./db/
@rm -rf ./incremental_db/

23
cores/arcade/pacman/pace/synth/platform/pacman/mist/pacman.qpf
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@@ -1,23 +0,0 @@
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
QUARTUS_VERSION = "5.0"
DATE = "19:21:54 August 25, 2005"
# Revisions
PROJECT_REVISION = "pacman"

206
cores/arcade/pacman/pace/synth/platform/pacman/mist/pacman.qsf
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# copyright (c) 1991-2005 altera corporation
# your use of altera corporation's design tools, logic functions
# and other software and tools, and its ampp partner logic
# functions, and any output files any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the altera program license
# subscription agreement, altera megacore function license
# agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by altera and sold by
# altera or its authorized distributors. please refer to the
# applicable agreement for further details.
# the default values for assignments are stored in the file
# pacman_assignment_defaults.qdf
# if this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
# altera recommends that you do not modify this file. this
# file is updated automatically by the quartus ii software
# and any changes you make may be lost or overwritten.
# project-wide assignments
# ========================
set_global_assignment -name LAST_QUARTUS_VERSION 12.1
# pin & location assignments
# ==========================
# analysis & synthesis assignments
# ================================
set_global_assignment -name TOP_LEVEL_ENTITY target_top
# fitter assignments
# ==================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
# assembler assignments
# =====================
set_global_assignment -name SEED 1
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27[0]
set_location_assignment PIN_55 -to CLOCK_27[1]
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_46 -to UART_TX
set_location_assignment PIN_31 -to UART_RX
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_90 -to SPI_SS4
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name VHDL_FILE ../../../../src/pace/pace_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../src/pace/pace_pkg_body.vhd
set_global_assignment -name VHDL_FILE ../../../../src/pace/stubs/sdram_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../src/pace/video/video_controller_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../src/pace/video/video_controller_pkg_body.vhd
set_global_assignment -name VHDL_FILE ../../../../src/pace/video/tilemapctl_e.vhd
set_global_assignment -name VHDL_FILE ../../../../src/pace/video/bitmapctl_e.vhd
set_global_assignment -name VHDL_FILE ../../../../src/pace/video/sprite_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../src/pace/video/sprite_pkg_body.vhd
set_global_assignment -name VHDL_FILE project_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/platform_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../src/target/mist/target_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../device/cycloneiii/pll.vhd
set_global_assignment -name VHDL_FILE ../../../device/cycloneiii/sprom.vhd
set_global_assignment -name VHDL_FILE ../../../device/cycloneiii/dpram.vhd
set_global_assignment -name VHDL_FILE ../../../device/cycloneiii/spram.vhd
set_global_assignment -name VHDL_FILE ../../../../src/pace/clk_div.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/ps2/ps2kbd_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/ps2/ps2kbd.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80se.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/Z80.vhd
set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/altera_mem.vhd
set_global_assignment -name VHDL_FILE ../../../../src/pace/video/video_controller.vhd
set_global_assignment -name VHDL_FILE ../../../../src/platform/pengo/tilemapctl.vhd
set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/spritereg.vhd
set_global_assignment -name VHDL_FILE ../../../../src/platform/pengo/spritectl.vhd
set_global_assignment -name VHDL_FILE ../../../../src/pace/video/sprite_array.vhd
set_global_assignment -name VHDL_FILE ../../../../src/pace/video/video_mixer.vhd
set_global_assignment -name VHDL_FILE ../../../../src/pace/Graphics.VHD
set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/InputMapper.VHD
set_global_assignment -name VHDL_FILE ../../../../src/pace/Inputs.VHD
set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/Pacman_Interrupts.vhd
set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/Pacman_vramMapper.vhd
set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/platform.vhd
set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/pacsnd.Vhd
set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/sound.vhd
set_global_assignment -name VHDL_FILE ../../../../src/pace/pace.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/io/gamecube/gamecube_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/load_upcounter.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/conversion.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_read2.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_write.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/mfifo.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_bus.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_joy.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/toys/led_chaser.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/toys/pwm_chaser.vhd
set_global_assignment -name VHDL_FILE ../../../../src/component/toys/pwmout.vhd
set_global_assignment -name VHDL_FILE ../../../../src/target/mist/target_top.vhd
set_global_assignment -name VHDL_FILE ../../../../src/target/mist/custom_io.vhd
set_global_assignment -name VERILOG_FILE ../../../../src/target/mist/user_io.v
set_global_assignment -name VHDL_FILE ../../../../src/component/sound/sigma_delta_dac.vhd
set_global_assignment -name QIP_FILE pllclk_ez.qip
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
cores/arcade/pacman/pace/synth/platform/pacman/mist/pacman.qws
View File

Binary file not shown.

5
cores/arcade/pacman/pace/synth/platform/pacman/mist/pllclk_ez.qip
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@@ -1,5 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "12.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pllclk_ez.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pllclk_ez.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pllclk_ez.ppf"]

495
cores/arcade/pacman/pace/synth/platform/pacman/mist/pllclk_ez.vhd
View File

@@ -1,495 +0,0 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pllclk_ez.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 177 11/07/2012 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pllclk_ez IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pllclk_ez;
ARCHITECTURE SYN OF pllclk_ez IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire9_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire9_bv(0 DOWNTO 0) <= "0";
sub_wire9 <= To_stdlogicvector(sub_wire9_bv);
sub_wire5 <= sub_wire0(3);
sub_wire4 <= sub_wire0(4);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c0 <= sub_wire2;
c2 <= sub_wire3;
c4 <= sub_wire4;
c3 <= sub_wire5;
locked <= sub_wire6;
sub_wire7 <= inclk0;
sub_wire8 <= sub_wire9(0 DOWNTO 0) & sub_wire7;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 100,
clk0_duty_cycle => 50,
clk0_multiply_by => 111,
clk0_phase_shift => "0",
clk1_divide_by => 25,
clk1_duty_cycle => 50,
clk1_multiply_by => 37,
clk1_phase_shift => "0",
clk2_divide_by => 125,
clk2_duty_cycle => 50,
clk2_multiply_by => 74,
clk2_phase_shift => "0",
clk3_divide_by => 20,
clk3_duty_cycle => 50,
clk3_multiply_by => 37,
clk3_phase_shift => "0",
clk4_divide_by => 27000000,
clk4_duty_cycle => 50,
clk4_multiply_by => 18449999,
clk4_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pllclk_ez",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_USED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire8,
clk => sub_wire0,
locked => sub_wire6
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "100"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "25"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "125"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "20"
-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "29.969999"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "39.959999"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "15.984000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "49.950001"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "18.450001"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "111"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "37"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "74"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "37"
-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "30.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "16.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "50.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "18.45000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pllclk_ez.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "100"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "111"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "37"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "125"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "74"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "20"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "37"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "27000000"
-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "18449999"
-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

58
cores/arcade/pacman/pace/synth/platform/pacman/mist/project_pkg.vhd
View File

@@ -1,58 +0,0 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.pace_pkg.all;
use work.target_pkg.all;
use work.video_controller_pkg.all;
package project_pkg is
--
-- PACE constants which *MUST* be defined
--
-- Reference clock is 16MHz
constant PACE_HAS_PLL : boolean := true;
--constant PACE_HAS_SRAM : boolean := true;
constant PACE_HAS_SDRAM : boolean := false;
constant PACE_HAS_FLASH : boolean := false;
constant PACE_HAS_SERIAL : boolean := false;
constant PACE_JAMMA : PACEJamma_t := PACE_JAMMA_NONE;
constant PACE_VIDEO_CONTROLLER_TYPE : PACEVideoController_t := PACE_VIDEO_VGA_800x600_60Hz;
constant PACE_CLK0_DIVIDE_BY : natural := 5;
constant PACE_CLK0_MULTIPLY_BY : natural := 3; -- 16*15/8 = 30MHz
constant PACE_CLK1_DIVIDE_BY : natural := 5;
constant PACE_CLK1_MULTIPLY_BY : natural := 4; -- 16*5/2 = 40MHz
constant PACE_VIDEO_H_SCALE : integer := 2;
constant PACE_VIDEO_V_SCALE : integer := 2;
constant PACE_VIDEO_H_SYNC_POLARITY : std_logic := '1';
constant PACE_VIDEO_V_SYNC_POLARITY : std_logic := '1';
constant PACE_VIDEO_BORDER_RGB : RGB_t := RGB_GREEN;
constant PACE_HAS_OSD : boolean := false;
constant PACE_OSD_XPOS : natural := 0;
constant PACE_OSD_YPOS : natural := 0;
-- Pacman-specific constants
constant PACMAN_ROM_IN_SRAM : boolean := false;
constant PACMAN_USE_INTERNAL_WRAM : boolean := true;
constant PACMAN_USE_VIDEO_VBLANK : boolean := true;
-- derived
constant PACE_HAS_SRAM : boolean := PACMAN_ROM_IN_SRAM or
not PACMAN_USE_INTERNAL_WRAM;
type from_PROJECT_IO_t is record
not_used : std_logic;
end record;
type to_PROJECT_IO_t is record
not_used : std_logic;
end record;
end;

1
cores/arcade/pacman/readme.txt
View File

@@ -1 +0,0 @@
Source code for the Pacman FPGA configuration for use against https://svn.pacedev.net/repos/pace/

62
cores/minimig/fpga/altera/minimig_mist.jdi
View File

@@ -1,62 +0,0 @@
<sld_project_info>
<project>
<hash md5_digest_80b="e8250947f302ae101f0e"/>
</project>
<file_info/>
<hub_info ir_width="8" node_count="1"/>
<node_info>
<node hpath="sld_signaltap:auto_signaltap_0" instance_id="0" mfg_id="110" node_id="0" sld_node_info="0x30006E00" version="6">
<parameters>
<parameter name="lpm_type" type="string" value="sld_signaltap"/>
<parameter name="sld_node_info" type="unknown" value="805334528"/>
<parameter name="SLD_IP_VERSION" type="dec" value="6"/>
<parameter name="SLD_IP_MINOR_VERSION" type="dec" value="0"/>
<parameter name="SLD_COMMON_IP_VERSION" type="dec" value="0"/>
<parameter name="sld_data_bits" type="unknown" value="124"/>
<parameter name="sld_trigger_bits" type="unknown" value="124"/>
<parameter name="SLD_NODE_CRC_BITS" type="dec" value="32"/>
<parameter name="sld_node_crc_hiword" type="unknown" value="44938"/>
<parameter name="sld_node_crc_loword" type="unknown" value="15587"/>
<parameter name="SLD_INCREMENTAL_ROUTING" type="dec" value="0"/>
<parameter name="sld_sample_depth" type="unknown" value="1024"/>
<parameter name="sld_segment_size" type="unknown" value="1024"/>
<parameter name="SLD_RAM_BLOCK_TYPE" type="string" value="AUTO"/>
<parameter name="sld_state_bits" type="unknown" value="11"/>
<parameter name="sld_buffer_full_stop" type="unknown" value="1"/>
<parameter name="SLD_MEM_ADDRESS_BITS" type="dec" value="7"/>
<parameter name="SLD_DATA_BIT_CNTR_BITS" type="dec" value="4"/>
<parameter name="sld_trigger_level" type="unknown" value="1"/>
<parameter name="sld_trigger_in_enabled" type="unknown" value="0"/>
<parameter name="sld_advanced_trigger_entity" type="unknown" value="basic,1,"/>
<parameter name="sld_trigger_level_pipeline" type="unknown" value="1"/>
<parameter name="sld_enable_advanced_trigger" type="unknown" value="0"/>
<parameter name="SLD_ADVANCED_TRIGGER_1" type="string" value="NONE"/>
<parameter name="SLD_ADVANCED_TRIGGER_2" type="string" value="NONE"/>
<parameter name="SLD_ADVANCED_TRIGGER_3" type="string" value="NONE"/>
<parameter name="SLD_ADVANCED_TRIGGER_4" type="string" value="NONE"/>
<parameter name="SLD_ADVANCED_TRIGGER_5" type="string" value="NONE"/>
<parameter name="SLD_ADVANCED_TRIGGER_6" type="string" value="NONE"/>
<parameter name="SLD_ADVANCED_TRIGGER_7" type="string" value="NONE"/>
<parameter name="SLD_ADVANCED_TRIGGER_8" type="string" value="NONE"/>
<parameter name="SLD_ADVANCED_TRIGGER_9" type="string" value="NONE"/>
<parameter name="SLD_ADVANCED_TRIGGER_10" type="string" value="NONE"/>
<parameter name="sld_inversion_mask_length" type="unknown" value="396"/>
<parameter name="sld_inversion_mask" type="unknown" value="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
<parameter name="sld_power_up_trigger" type="unknown" value="0"/>
<parameter name="SLD_STATE_FLOW_MGR_ENTITY" type="string" value="state_flow_mgr_entity.vhd"/>
<parameter name="sld_state_flow_use_generated" type="unknown" value="0"/>
<parameter name="sld_current_resource_width" type="unknown" value="1"/>
<parameter name="sld_attribute_mem_mode" type="unknown" value="OFF"/>
<parameter name="SLD_STORAGE_QUALIFIER_BITS" type="dec" value="1"/>
<parameter name="SLD_STORAGE_QUALIFIER_GAP_RECORD" type="dec" value="0"/>
<parameter name="SLD_STORAGE_QUALIFIER_MODE" type="string" value="OFF"/>
<parameter name="SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION" type="dec" value="0"/>
<parameter name="sld_storage_qualifier_inversion_mask_length" type="unknown" value="0"/>
<parameter name="SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY" type="string" value="basic"/>
<parameter name="SLD_STORAGE_QUALIFIER_PIPELINE" type="dec" value="0"/>
</parameters>
<inputs/>
<outputs/>
</node>
</node_info>
</sld_project_info>

BIN
cores/minimig/fpga/altera/minimig_mist.qws
View File

Binary file not shown.

5
cores/sms/pll.qip
View File

@@ -1,5 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

397
cores/sms/pll.vhd
View File

@@ -1,397 +0,0 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 27,
clk0_duty_cycle => 50,
clk0_multiply_by => 64,
clk0_phase_shift => "0",
clk1_divide_by => 27,
clk1_duty_cycle => 50,
clk1_multiply_by => 64,
clk1_phase_shift => "-2500",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "64.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "64.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "64.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "64.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-2.50000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "64"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "64"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2500"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

23
cores/sms/sms_mist.qpf
View File

@@ -1,23 +0,0 @@
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
QUARTUS_VERSION = "7.2"
DATE = "17:25:25 January 26, 2008"
# Revisions
PROJECT_REVISION = "sms_mist"

353
cores/sms/sms_mist.qsf
View File

@@ -1,353 +0,0 @@
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
set_global_assignment -name TOP_LEVEL_ENTITY sms_mist
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:49:11 JANUARY 31, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
# Pin & Location Assignments
# ==========================
# Timing Assignments
# ==================
set_global_assignment -name IGNORE_CLOCK_SETTINGS ON
set_global_assignment -name TPD_REQUIREMENT "5 ns"
set_global_assignment -name TSU_REQUIREMENT "5 ns"
set_global_assignment -name TCO_REQUIREMENT "5 ns"
set_global_assignment -name TH_REQUIREMENT "5 ns"
set_global_assignment -name FMAX_REQUIREMENT "101.58 MHz"
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM ON
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name AUTO_RESOURCE_SHARING OFF
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name FLEX10K_DEVICE_IO_STANDARD LVTTL/LVCMOS
# Assembler Assignments
# =====================
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name ENABLE_DRC_SETTINGS ON
set_global_assignment -name ENABLE_CLOCK_LATENCY ON
set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON
set_global_assignment -name IGNORE_LCELL_BUFFERS ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "FAST FIT"
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS ON
set_global_assignment -name AUTO_PACKED_REGISTERS "MINIMIZE AREA"
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS OFF
set_global_assignment -name IGNORE_CARRY_BUFFERS ON
set_global_assignment -name IGNORE_CASCADE_BUFFERS ON
set_global_assignment -name AUTO_GLOBAL_CLOCK ON
set_global_assignment -name AUTO_RAM_RECOGNITION ON
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION AUTO
set_global_assignment -name STATE_MACHINE_PROCESSING AUTO
set_global_assignment -name FMAX_REQUIREMENT "34 MHz" -section_id clk32
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES "DONT CARE"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27[0]
set_location_assignment PIN_55 -to CLOCK_27[1]
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_46 -to UART_TX
set_location_assignment PIN_31 -to UART_RX
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_90 -to SPI_SS4
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SDRAM_CLK
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SPI_SCK
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VHDL_FILE src/video.vhd
set_global_assignment -name VHDL_FILE src/pal_video.vhd
set_global_assignment -name VHDL_FILE src/ntsc_video.vhd
set_global_assignment -name VERILOG_FILE src/scandoubler.v
set_global_assignment -name VERILOG_FILE src/data_io.v
set_global_assignment -name VERILOG_FILE src/osd.v
set_global_assignment -name VERILOG_FILE src/user_io.v
set_global_assignment -name VHDL_FILE src/sprom.vhd
set_global_assignment -name VHDL_FILE src/spram.vhd
set_global_assignment -name VERILOG_FILE src/sdram.v
set_global_assignment -name VHDL_FILE src/dpram.vhd
set_global_assignment -name VHDL_FILE t80/T80se.vhd
set_global_assignment -name VHDL_FILE src/vga_video.vhd
set_global_assignment -name VHDL_FILE src/vdp_sprites.vhd
set_global_assignment -name VHDL_FILE src/vdp_sprite_shifter.vhd
set_global_assignment -name VHDL_FILE src/vdp_main.vhd
set_global_assignment -name VHDL_FILE src/vdp_cram.vhd
set_global_assignment -name VHDL_FILE src/vdp_background.vhd
set_global_assignment -name VHDL_FILE src/vdp.vhd
set_global_assignment -name VHDL_FILE src/system.vhd
set_global_assignment -name VHDL_FILE src/sms_mist.vhd
set_global_assignment -name VHDL_FILE src/psg_tone.vhd
set_global_assignment -name VHDL_FILE src/psg_noise.vhd
set_global_assignment -name VHDL_FILE src/psg.vhd
set_global_assignment -name VHDL_FILE src/io.vhd
set_global_assignment -name VHDL_FILE src/dac.vhd
set_global_assignment -name VHDL_FILE t80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE t80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE t80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE t80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE t80/T80.vhd
set_global_assignment -name QIP_FILE pll.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

35
cores/sms/src/dac.vhd
View File

@@ -1,35 +0,0 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dac is
Port (
clk : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (5 downto 0);
output: out STD_LOGIC);
end dac;
architecture rtl of dac is
signal delta_adder: unsigned(7 downto 0);
signal sigma_adder: unsigned(7 downto 0);
signal sigma_latch: unsigned(7 downto 0) := "01000000";
signal delta_b : unsigned(7 downto 0);
begin
delta_b <= sigma_latch(7)&sigma_latch(7)&"000000";
delta_adder <= unsigned(input) + delta_b;
sigma_adder <= delta_adder + sigma_latch;
process (clk, delta_adder)
begin
if rising_edge(clk) then
sigma_latch <= sigma_adder;
output <= sigma_adder(7);
end if;
end process;
end rtl;

119
cores/sms/src/data_io.v
View File

@@ -1,119 +0,0 @@
//
// data_io.v
//
// io controller writable ram for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module data_io (
// io controller spi interface
input sck,
input ss,
input sdi,
output downloading, // signal indicating an active download
output [24:0] size, // number of bytes in input buffer
// external ram interface
input clk,
output reg wr,
output reg [24:0] a,
output [7:0] d
);
assign d = data;
parameter START_ADDR = 25'h0;
assign size = addr;
// *********************************************************************************
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg [6:0] sbuf;
reg [7:0] cmd /* synthesis noprune */;
reg [7:0] data /* synthesis noprune */;
reg [4:0] cnt /* synthesis noprune */;
reg [24:0] addr /* synthesis noprune */;
reg rclk /* synthesis noprune */;
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
assign downloading = downloading_reg;
reg downloading_reg = 1'b0;
// data_io has its own SPI interface to the io controller
always@(posedge sck, posedge ss) begin
if(ss == 1'b1)
cnt <= 5'd0;
else begin
rclk <= 1'b0;
// don't shift in last bit. It is evaluated directly
// when writing to ram
if(cnt != 15)
sbuf <= { sbuf[5:0], sdi};
// increase target address after write
if(rclk)
addr <= addr + 25'd1;
// count 0-7 8-15 8-15 ...
if(cnt < 15) cnt <= cnt + 4'd1;
else cnt <= 4'd8;
// finished command byte
if(cnt == 7)
cmd <= {sbuf, sdi};
// prepare/end transmission
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(sdi) begin
addr <= START_ADDR;
downloading_reg <= 1'b1;
end else
downloading_reg <= 1'b0;
end
// command 0x54: UIO_FILE_TX
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
data <= {sbuf, sdi};
rclk <= 1'b1;
a <= addr;
end
end
end
reg rclkD, rclkD2;
always@(posedge clk) begin
// bring rclk from spi clock domain into core clock domain
rclkD <= rclk;
rclkD2 <= rclkD;
wr <= 1'b0;
if(rclkD && !rclkD2)
wr <= 1'b1;
end
endmodule

130
cores/sms/src/dpram.vhd
View File

@@ -1,130 +0,0 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED";
outdata_reg_b : string := "UNREGISTERED"
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END dpram;
ARCHITECTURE SYN OF dpram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(width_a-1 DOWNTO 0);
q_b <= sub_wire1(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
numwords_b => 2**widthad_a,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => outdata_reg_a,
outdata_reg_b => outdata_reg_a,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => widthad_a,
widthad_b => widthad_a,
width_a => width_a,
width_b => width_a,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;

93
cores/sms/src/io.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity io is
Port(
clk: in STD_LOGIC;
WR_n: in STD_LOGIC;
RD_n: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (7 downto 0);
D_in: in STD_LOGIC_VECTOR (7 downto 0);
D_out: out STD_LOGIC_VECTOR (7 downto 0);
J1_up: in STD_LOGIC;
J1_down: in STD_LOGIC;
J1_left: in STD_LOGIC;
J1_right:in STD_LOGIC;
J1_tl: in STD_LOGIC;
J1_tr: in STD_LOGIC;
J2_up: in STD_LOGIC;
J2_down: in STD_LOGIC;
J2_left: in STD_LOGIC;
J2_right:in STD_LOGIC;
J2_tl: in STD_LOGIC;
J2_tr: in STD_LOGIC;
RESET: in STD_LOGIC);
end io;
architecture rtl of io is
signal ctrl: std_logic_vector(7 downto 0) := (others=>'1');
begin
process (clk)
begin
if rising_edge(clk) then
if WR_n='0' then
ctrl <= D_in;
end if;
end if;
end process;
-- J1_tr <= ctrl(4) when ctrl(0)='0' else 'Z';
-- J2_tr <= ctrl(6) when ctrl(2)='0' else 'Z';
process (clk)
begin
if rising_edge(clk) then
if RD_n='0' then
if A(0)='0' then
D_out(7) <= J2_down;
D_out(6) <= J2_up;
-- 5=j1_tr
if ctrl(0)='0' then
D_out(5) <= ctrl(4);
else
D_out(5) <= J1_tr;
end if;
D_out(4) <= J1_tl;
D_out(3) <= J1_right;
D_out(2) <= J1_left;
D_out(1) <= J1_down;
D_out(0) <= J1_up;
else
-- 7=j2_th
if ctrl(3)='0' then
D_out(7) <= ctrl(7);
else
D_out(7) <= '1';
end if;
-- 6=j1_th
if ctrl(1)='0' then
D_out(6) <= ctrl(5);
else
D_out(6) <= '1';
end if;
D_out(5) <= '1';
D_out(4) <= '1';
-- 4=j2_tr
if ctrl(2)='0' then
D_out(3) <= ctrl(6);
else
D_out(3) <= J2_tr;
end if;
D_out(2) <= J2_tl;
D_out(1) <= J2_right;
D_out(0) <= J2_left;
end if;
end if;
end if;
end process;
end rtl;

1382
cores/sms/src/mboot.mif
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110
cores/sms/src/ntsc_video.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ntsc_video is
Port (
clk8: in std_logic;
x: out unsigned(8 downto 0);
y: out unsigned(7 downto 0);
color: in std_logic_vector(5 downto 0);
hsync: out std_logic;
vsync: out std_logic;
red: out std_logic_vector(1 downto 0);
green: out std_logic_vector(1 downto 0);
blue: out std_logic_vector(1 downto 0));
end ntsc_video;
architecture Behavioral of ntsc_video is
signal hcount: unsigned(8 downto 0) := (others => '0');
signal vcount: unsigned(8 downto 0) := (others => '0');
signal y9: unsigned(8 downto 0);
signal in_vbl: std_logic;
signal screen_sync: std_logic;
signal vbl_vsync: std_logic;
signal vbl_hsync: std_logic;
signal visible: boolean;
begin
process (clk8)
begin
if rising_edge(clk8) then
if hcount=507 then
hcount <= (others => '0');
if vcount=261 then
vcount <= (others=>'0');
else
vcount <= vcount + 1;
end if;
else
hcount <= hcount + 1;
end if;
end if;
end process;
process (hcount)
begin
if hcount<38 then
screen_sync <= '0';
else
screen_sync <= '1';
end if;
end process;
in_vbl <= '1' when vcount<9 else '0';
x <= hcount-166;
y9 <= vcount-40;
y <= y9(7 downto 0);
--vblank <= '1' when hcount=0 and vcount=0 else '0';
--hblank <= '1' when hcount=0 else '0';
process (vcount,hcount)
begin
if vcount<3 or (vcount>=6 and vcount<9) then
-- _^^^^^_^^^^^ : low pulse = 2.35us
if hcount<19 or (hcount>=254 and hcount<254+19) then
vbl_hsync <= '0';
vbl_vsync <= '0';
else
vbl_hsync <= '1';
vbl_vsync <= '0';
end if;
else
-- ____^^ : high pulse = 4.7us
if hcount<(254-38) or (hcount>=254 and hcount<508-38) then
vbl_vsync <= '0';
vbl_hsync <= '0';
else
vbl_vsync <= '1';
vbl_hsync <= '0';
end if;
end if;
end process;
hsync <= not screen_sync when in_vbl='0' else vbl_hsync;
vsync <= not vbl_vsync when in_vbl='1' else '0';
visible <= (hcount>=164 and hcount<420 and vcount>=40 and vcount<232);
process (clk8)
begin
if rising_edge(clk8) then
if visible then
red <= color(1 downto 0);
green <= color(3 downto 2);
blue <= color(5 downto 4);
else
red <= (others=>'0');
green <= (others=>'0');
blue <= (others=>'0');
end if;
end if;
end process;
end Behavioral;

182
cores/sms/src/osd.v
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// A simple OSD implementation. Can be hooked up between a cores
// VGA output and the physical VGA pins
module osd (
// OSDs pixel clock, should be synchronous to cores pixel clock to
// avoid jitter.
input pclk,
// SPI interface
input sck,
input ss,
input sdi,
// VGA signals coming from core
input [5:0] red_in,
input [5:0] green_in,
input [5:0] blue_in,
input hs_in,
input vs_in,
// VGA signals going to video connector
output [5:0] red_out,
output [5:0] green_out,
output [5:0] blue_out,
output hs_out,
output vs_out
);
parameter OSD_X_OFFSET = 10'd0;
parameter OSD_Y_OFFSET = 10'd0;
parameter OSD_COLOR = 3'd1;
localparam OSD_WIDTH = 10'd256;
localparam OSD_HEIGHT = 10'd128;
// *********************************************************************************
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg [7:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [10:0] bcnt;
reg osd_enable;
reg [7:0] osd_buffer [2047:0]; // the OSD buffer itself
// the OSD has its own SPI interface to the io controller
always@(posedge sck, posedge ss) begin
if(ss == 1'b1) begin
cnt <= 5'd0;
bcnt <= 11'd0;
end else begin
sbuf <= { sbuf[6:0], sdi};
// 0:7 is command, rest payload
if(cnt < 15)
cnt <= cnt + 4'd1;
else
cnt <= 4'd8;
if(cnt == 7) begin
cmd <= {sbuf[6:0], sdi};
// lower three command bits are line address
bcnt <= { sbuf[1:0], sdi, 8'h00};
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(sbuf[6:3] == 4'b0100)
osd_enable <= sdi;
end
// command 0x20: OSDCMDWRITE
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
osd_buffer[bcnt] <= {sbuf[6:0], sdi};
bcnt <= bcnt + 11'd1;
end
end
end
// *********************************************************************************
// video timing and sync polarity anaylsis
// *********************************************************************************
// horizontal counter
reg [9:0] h_cnt;
reg hsD, hsD2;
reg [9:0] hs_low, hs_high;
wire hs_pol = hs_high < hs_low;
wire [9:0] h_dsp_width = hs_pol?hs_low:hs_high;
wire [9:0] h_dsp_ctr = { 1'b0, h_dsp_width[9:1] };
always @(posedge pclk) begin
// bring hsync into local clock domain
hsD <= hs_in;
hsD2 <= hsD;
// falling edge of hs_in
if(!hsD && hsD2) begin
h_cnt <= 10'd0;
hs_high <= h_cnt;
end
// rising edge of hs_in
else if(hsD && !hsD2) begin
h_cnt <= 10'd0;
hs_low <= h_cnt;
end
else
h_cnt <= h_cnt + 10'd1;
end
// vertical counter
reg [9:0] v_cnt;
reg vsD, vsD2;
reg [9:0] vs_low, vs_high;
wire vs_pol = vs_high < vs_low;
wire [9:0] v_dsp_width = vs_pol?vs_low:vs_high;
wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_width[9:1] };
always @(posedge hsD) begin
// bring vsync into local clock domain
vsD <= vs_in;
vsD2 <= vsD;
// falling edge of vs_in
if(!vsD && vsD2) begin
v_cnt <= 10'd0;
vs_high <= v_cnt;
end
// rising edge of vs_in
else if(vsD && !vsD2) begin
v_cnt <= 10'd0;
vs_low <= v_cnt;
end
else
v_cnt <= v_cnt + 10'd1;
end
// area in which OSD is being displayed
wire [9:0] h_osd_start = h_dsp_ctr + OSD_X_OFFSET - (OSD_WIDTH >> 1);
wire [9:0] h_osd_end = h_dsp_ctr + OSD_X_OFFSET + (OSD_WIDTH >> 1) - 1;
wire [9:0] v_osd_start = v_dsp_ctr + OSD_Y_OFFSET - (OSD_HEIGHT >> 1);
wire [9:0] v_osd_end = v_dsp_ctr + OSD_Y_OFFSET + (OSD_HEIGHT >> 1) - 1;
reg h_osd_active, v_osd_active;
always @(posedge pclk) begin
if(hs_in != hs_pol) begin
if(h_cnt == h_osd_start) h_osd_active <= 1'b1;
if(h_cnt == h_osd_end) h_osd_active <= 1'b0;
end
if(vs_in != vs_pol) begin
if(v_cnt == v_osd_start) v_osd_active <= 1'b1;
if(v_cnt == v_osd_end) v_osd_active <= 1'b0;
end
end
wire osd_de = osd_enable && h_osd_active && v_osd_active;
wire [7:0] osd_hcnt = h_cnt - h_osd_start + 7'd1; // one pixel offset for osd_byte register
wire [6:0] osd_vcnt = v_cnt - v_osd_start;
wire osd_pixel = osd_byte[osd_vcnt[3:1]];
reg [7:0] osd_byte;
always @(posedge pclk)
osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt}];
wire [2:0] osd_color = OSD_COLOR;
assign red_out = !osd_de?red_in: {osd_pixel, osd_pixel, osd_color[2], red_in[5:3] };
assign green_out = !osd_de?green_in:{osd_pixel, osd_pixel, osd_color[1], green_in[5:3]};
assign blue_out = !osd_de?blue_in: {osd_pixel, osd_pixel, osd_color[0], blue_in[5:3] };
assign hs_out = hs_in;
assign vs_out = vs_in;
endmodule

116
cores/sms/src/pal_video.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pal_video is
Port (
clk8: in std_logic;
x: out unsigned(8 downto 0);
y: out unsigned(7 downto 0);
color: in std_logic_vector(5 downto 0);
hsync: out std_logic;
vsync: out std_logic;
red: out std_logic_vector(1 downto 0);
green: out std_logic_vector(1 downto 0);
blue: out std_logic_vector(1 downto 0));
end pal_video;
architecture Behavioral of pal_video is
signal hcount: unsigned(8 downto 0) := (others => '0');
signal vcount: unsigned(8 downto 0) := (others => '0');
signal y9: unsigned(8 downto 0);
signal in_vbl: std_logic;
signal screen_sync: std_logic;
signal vbl_hsync: std_logic;
signal vbl_vsync: std_logic;
signal visible: boolean;
begin
process (clk8)
begin
if rising_edge(clk8) then
if hcount=511 then
hcount <= (others => '0');
if vcount=311 then
vcount <= (others=>'0');
else
vcount <= vcount + 1;
end if;
else
hcount <= hcount + 1;
end if;
end if;
end process;
process (hcount)
begin
if hcount<37 then
screen_sync <= '0';
else
screen_sync <= '1';
end if;
end process;
in_vbl <= '1' when vcount<5 else '0';
x <= hcount-164;
y9 <= vcount-64;
y <= y9(7 downto 0);
--vblank <= '1' when hcount=0 and vcount=0 else '0';
--hblank <= '1' when hcount=0 else '0';
process (vcount,hcount)
begin
if vcount<2 then
if hcount<240 or (hcount>=256 and hcount<496) then
vbl_vsync <= '0';
vbl_hsync <= '0';
else
vbl_vsync <= '1';
vbl_hsync <= '0';
end if;
elsif vcount=2 then
if hcount<240 or (hcount>=256 and hcount<272) then
vbl_hsync <= '0';
vbl_vsync <= '0';
else
vbl_hsync <= '1';
vbl_vsync <= '0';
end if;
else
if hcount<16 or (hcount>=256 and hcount<272) then
vbl_hsync <= '0';
vbl_vsync <= '0';
else
vbl_hsync <= '1';
vbl_vsync <= '0';
end if;
end if;
end process;
hsync <= not screen_sync when in_vbl='0' else vbl_hsync;
vsync <= not vbl_vsync when in_vbl='1' else '0';
visible <= (hcount>=166 and hcount<422 and vcount>=64 and vcount<256);
process (clk8)
begin
if rising_edge(clk8) then
if visible then
red <= color(1 downto 0);
green <= color(3 downto 2);
blue <= color(5 downto 4);
else
red <= (others=>'0');
green <= (others=>'0');
blue <= (others=>'0');
end if;
end if;
end process;
end Behavioral;

137
cores/sms/src/psg.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity psg is
port (clk : in STD_LOGIC;
WR_n : in STD_LOGIC;
D_in : in STD_LOGIC_VECTOR (7 downto 0);
output: out STD_LOGIC);
end entity;
architecture rtl of psg is
signal clk_divide : unsigned(4 downto 0) := "00000";
signal clk32 : std_logic;
signal regn : std_logic_vector(2 downto 0);
signal tone0 : std_logic_vector(9 downto 0):="0000100000";
signal tone1 : std_logic_vector(9 downto 0):="0000100000";
signal tone2 : std_logic_vector(9 downto 0):="0000100000";
signal ctrl3 : std_logic_vector(2 downto 0):="100";
signal volume0 : std_logic_vector(3 downto 0):="1111";
signal volume1 : std_logic_vector(3 downto 0):="1111";
signal volume2 : std_logic_vector(3 downto 0):="1111";
signal volume3 : std_logic_vector(3 downto 0):="1111";
signal output0 : std_logic_vector(3 downto 0);
signal output1 : std_logic_vector(3 downto 0);
signal output2 : std_logic_vector(3 downto 0);
signal output3 : std_logic_vector(3 downto 0);
signal outputs : std_logic_vector(5 downto 0);
component psg_tone is
port (clk : in STD_LOGIC;
tone : in STD_LOGIC_VECTOR (9 downto 0);
volume: in STD_LOGIC_VECTOR (3 downto 0);
output: out STD_LOGIC_VECTOR (3 downto 0));
end component;
component psg_noise is
port (clk : in STD_LOGIC;
style : in STD_LOGIC_VECTOR (2 downto 0);
tone : in STD_LOGIC_VECTOR (9 downto 0);
volume: in STD_LOGIC_VECTOR (3 downto 0);
output: out STD_LOGIC_VECTOR (3 downto 0));
end component;
component dac is
port (clk : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (5 downto 0);
output: out STD_LOGIC);
end component;
begin
t0: psg_tone
port map (
clk => clk32,
tone => tone0,
volume => volume0,
output => output0);
t1: psg_tone
port map (
clk => clk32,
tone => tone1,
volume => volume1,
output => output1);
t2: psg_tone
port map (
clk => clk32,
tone => tone2,
volume => volume2,
output => output2);
t3: psg_noise
port map(
clk => clk32,
style => ctrl3,
tone => tone2,
volume => volume3,
output => output3);
inst_dac: dac
port map (
clk => clk,
input => outputs,
output => output );
process (clk)
begin
if rising_edge(clk) then
clk_divide <= clk_divide+1;
end if;
end process;
clk32 <= std_logic(clk_divide(4));
process (clk, WR_n)
begin
if rising_edge(clk) and WR_n='0' then
if D_in(7)='1' then
case D_in(6 downto 4) is
when "000" => tone0(3 downto 0) <= D_in(3 downto 0);
when "010" => tone1(3 downto 0) <= D_in(3 downto 0);
when "100" => tone2(3 downto 0) <= D_in(3 downto 0);
when "110" => ctrl3 <= D_in(2 downto 0);
when "001" => volume0 <= D_in(3 downto 0);
when "011" => volume1 <= D_in(3 downto 0);
when "101" => volume2 <= D_in(3 downto 0);
when "111" => volume3 <= D_in(3 downto 0);
when others =>
end case;
regn <= D_in(6 downto 4);
else
case regn is
when "000" => tone0(9 downto 4) <= D_in(5 downto 0);
when "010" => tone1(9 downto 4) <= D_in(5 downto 0);
when "100" => tone2(9 downto 4) <= D_in(5 downto 0);
when "110" =>
when "001" => volume0 <= D_in(3 downto 0);
when "011" => volume1 <= D_in(3 downto 0);
when "101" => volume2 <= D_in(3 downto 0);
when "111" => volume3 <= D_in(3 downto 0);
when others =>
end case;
end if;
end if;
end process;
outputs <= std_logic_vector(
unsigned("00"&output0)
+ unsigned("00"&output1)
+ unsigned("00"&output2)
+ unsigned("00"&output3)
);
end rtl;

56
cores/sms/src/psg_noise.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity psg_noise is
port (
clk : in STD_LOGIC;
style : in STD_LOGIC_VECTOR (2 downto 0);
tone : in STD_LOGIC_VECTOR (9 downto 0);
volume : in STD_LOGIC_VECTOR (3 downto 0);
output : out STD_LOGIC_VECTOR (3 downto 0));
end psg_noise;
architecture rtl of psg_noise is
signal counter : unsigned(9 downto 0);
signal v : std_logic;
signal shift : std_logic_vector(15 downto 0) := "1000000000000000";
begin
process (clk, tone)
begin
if rising_edge(clk) then
if counter="000000001" then
v <= not v;
case style(1 downto 0) is
when "00" => counter <= "0000010000";
when "01" => counter <= "0000100000";
when "10" => counter <= "0001000000";
when "11" => counter <= unsigned(tone);
when others =>
end case;
else
counter <= counter-1;
end if;
end if;
end process;
process (v)
variable feedback: std_logic;
begin
if rising_edge(v) then
if (style(2)='1') then
feedback := shift(0) xor shift(3);
else
feedback := shift(0);
end if;
shift <= feedback & shift(15 downto 1);
end if;
end process;
output <= (shift(0)&shift(0)&shift(0)&shift(0)) or volume;
end rtl;

34
cores/sms/src/psg_tone.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity psg_tone is
Port (
clk : in STD_LOGIC;
tone : in STD_LOGIC_VECTOR (9 downto 0);
volume: in STD_LOGIC_VECTOR (3 downto 0);
output: out STD_LOGIC_VECTOR (3 downto 0));
end psg_tone;
architecture rtl of psg_tone is
signal counter : unsigned(9 downto 0) := (0=>'1', others=>'0');
signal v : std_logic := '0';
begin
process (clk, tone)
begin
if rising_edge(clk) then
if counter="000000000" then
v <= not v;
counter <= unsigned(tone);
else
counter <= counter-1;
end if;
end if;
end process;
output <= (v&v&v&v) or volume;
end rtl;

147
cores/sms/src/scandoubler.v
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@@ -1,147 +0,0 @@
//
// scandoubler.v
//
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module scandoubler (
// system interface
input clk_in,
input clk_out,
input scanlines,
// shifter video interface
input hs_in,
input vs_in,
input [5:0] r_in,
input [5:0] g_in,
input [5:0] b_in,
// output interface
output reg [5:0] r_out,
output reg [5:0] g_out,
output reg [5:0] b_out,
output reg vs_out,
output reg hs_out
);
// scan doubler output register
reg [17:0] sd_out;
// --------------------- create output signals -----------------
// latch everything once more to make it glitch free and apply scanline effect
reg scanline;
always @(posedge clk_out) begin
vs_out <= vs_in;
hs_out <= hs_sd;
// reset scanlines at every new screen
if(vs_out != vs_in)
scanline <= 1'b0;
// toggle scanlines at begin of every hsync
if(hs_out && !hs_sd)
scanline <= !scanline;
// if no scanlines or not a scanline
if(!scanlines || !scanline) begin
r_out <= { sd_out[17:12] };
g_out <= { sd_out[11:6] };
b_out <= { sd_out[5:0] };
end else begin
r_out <= { 1'b0, sd_out[17:13] };
g_out <= { 1'b0, sd_out[11:7] };
b_out <= { 1'b0, sd_out[5:1] };
end
end
// ==================================================================
// ======================== the line buffers ========================
// ==================================================================
// 2 lines of 1024 pixels 3*6 bit RGB
reg [17:0] sd_buffer [2047:0];
// use alternating sd_buffers when storing/reading data
reg vsD;
reg line_toggle;
always @(negedge clk_in) begin
vsD <= vs_in;
if(vsD != vs_in)
line_toggle <= 1'b0;
// begin of incoming hsync
if(hsD && !hs_in)
line_toggle <= !line_toggle;
end
always @(negedge clk_in) begin
sd_buffer[{line_toggle, hcnt}] <= { r_in, g_in, b_in };
end
// ==================================================================
// =================== horizontal timing analysis ===================
// ==================================================================
// total hsync time (in 16MHz cycles), hs_total reaches 1024
reg [9:0] hs_max;
reg [9:0] hs_rise;
reg [9:0] hcnt;
reg hsD;
always @(negedge clk_in) begin
hsD <= hs_in;
// falling edge of hsync indicates start of line
if(hsD && !hs_in) begin
hs_max <= hcnt;
hcnt <= 10'd0;
end else
hcnt <= hcnt + 10'd1;
// save position of rising edge
if(!hsD && hs_in)
hs_rise <= hcnt;
end
// ==================================================================
// ==================== output timing generation ====================
// ==================================================================
reg [9:0] sd_hcnt;
reg hs_sd;
// timing generation runs 32 MHz (twice the input signal analysis speed)
always @(posedge clk_out) begin
// output counter synchronous to input and at twice the rate
sd_hcnt <= sd_hcnt + 10'd1;
if(hsD && !hs_in) sd_hcnt <= hs_max;
if(sd_hcnt == hs_max) sd_hcnt <= 10'd0;
// replicate horizontal sync at twice the speed
if(sd_hcnt == hs_max) hs_sd <= 1'b0;
if(sd_hcnt == hs_rise) hs_sd <= 1'b1;
// read data from line sd_buffer
sd_out <= sd_buffer[{~line_toggle, sd_hcnt}];
end
endmodule

185
cores/sms/src/sdram.v
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//
// sdram.v
//
// sdram controller implementation for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sdram (
// interface to the MT48LC16M16 chip
inout [15:0] sd_data, // 16 bit bidirectional data bus
output reg [12:0] sd_addr, // 13 bit multiplexed address bus
output reg [1:0] sd_dqm, // two byte masks
output reg [1:0] sd_ba, // two banks
output sd_cs, // a single chip select
output sd_we, // write enable
output sd_ras, // row address select
output sd_cas, // columns address select
// cpu/chipset interface
input init, // init signal after FPGA config to initialize RAM
input clk, // sdram is accessed at up to 128MHz
input clkref, // reference clock to sync to
input [7:0] din, // data input from chipset/cpu
output [7:0] dout, // data output to chipset/cpu
input [24:0] addr, // 25 bit byte address
input oe, // cpu/chipset requests read
input we // cpu/chipset requests write
);
// falling edge on oe/we/rfsh starts state machine
// no burst configured
localparam RASCAS_DELAY = 3'd3; // tRCD=20ns -> 3 cycles@128MHz
localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd3; // 2/3 allowed
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
// ---------------------------------------------------------------------
localparam STATE_IDLE = 3'd0; // first state in cycle
localparam STATE_CMD_START = 3'd0; // state in which a new command can be started
localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY; // 4 command can be continued
localparam STATE_READ = STATE_CMD_CONT + CAS_LATENCY + 4'd1; //
localparam STATE_LAST = 3'd7; // last state in cycle
assign dout = addr[0]?sd_data[7:0]:sd_data[15:8];
reg [2:0] q /* synthesis noprune */;
always @(posedge clk) begin
// 112Mhz counter synchronous to 14 Mhz clock
// force counter to pass state 5->6 exactly after the rising edge of clkref
// since clkref is two clocks early
if(((q == 7) && ( clkref == 0)) ||
((q == 0) && ( clkref == 1)) ||
((q != 7) && (q != 0)))
q <= q + 3'd1;
end
// ---------------------------------------------------------------------
// --------------------------- startup/reset ---------------------------
// ---------------------------------------------------------------------
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
reg [4:0] reset;
always @(posedge clk) begin
if(init) reset <= 5'h1f;
else if((q == STATE_LAST) && (reset != 0))
reset <= reset - 5'd1;
end
// ---------------------------------------------------------------------
// ------------------ generate ram control signals ---------------------
// ---------------------------------------------------------------------
// all possible commands
localparam CMD_INHIBIT = 4'b1111;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_AUTO_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
reg [3:0] sd_cmd; // current command sent to sd ram
// drive control signals according to current command
assign sd_cs = sd_cmd[3];
assign sd_ras = sd_cmd[2];
assign sd_cas = sd_cmd[1];
assign sd_we = sd_cmd[0];
// drive ram data lines when writing, set them as inputs otherwise
// the eight bits are sent on both bytes ports. Which one's actually
// written depends on the state of dqm of which only one is active
// at a time when writing
assign sd_data = we?{din, din}:16'bZZZZZZZZZZZZZZZZ;
// assign dout = addr[0]?sd_data[7:0]:sd_data[15:8];
always @(posedge clk) begin
sd_cmd <= CMD_INHIBIT; // default: idle
if(reset != 0) begin
// initialization takes place at the end of the reset phase
if(q == STATE_CMD_START) begin
if(reset == 13) begin
sd_cmd <= CMD_PRECHARGE;
sd_addr[10] <= 1'b1; // precharge all banks
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
sd_addr <= MODE;
end
end
end else begin
// normal operation
// ------------------- cpu/chipset read/write ----------------------
if(we || oe) begin
// RAS phase
if(q == STATE_CMD_START) begin
sd_cmd <= CMD_ACTIVE;
sd_addr <= addr[21:9];
sd_ba <= addr[23:22];
// always return both bytes in a read. Only the correct byte
// is being stored during read. On write only one of the two
// bytes is enabled
if(!we) sd_dqm <= 2'b00;
else sd_dqm <= { addr[0], ~addr[0] };
end
// CAS phase
if(q == STATE_CMD_CONT) begin
sd_cmd <= we?CMD_WRITE:CMD_READ;
sd_addr <= { 4'b0010, addr[24], addr[8:1] }; // auto precharge
end
end
// read phase
// if(oe) begin
// if(q == STATE_READ)
// dout <= addr[0]?sd_data[7:0]:sd_data[15:8];
// end
// ------------------------ no access --------------------------
else begin
if(q == STATE_CMD_START)
sd_cmd <= CMD_AUTO_REFRESH;
end
end
end
endmodule

432
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity sms_mist is
port (
-- Clocks
CLOCK_27 : in std_logic_vector(1 downto 0); -- 27 MHz
-- SDRAM
SDRAM_nCS : out std_logic; -- Chip Select
SDRAM_DQ : inout std_logic_vector(15 downto 0); -- SDRAM Data bus 16 Bits
SDRAM_A : out std_logic_vector(12 downto 0); -- SDRAM Address bus 13 Bits
SDRAM_DQMH : out std_logic; -- SDRAM High Data Mask
SDRAM_DQML : out std_logic; -- SDRAM Low-byte Data Mask
SDRAM_nWE : out std_logic; -- SDRAM Write Enable
SDRAM_nCAS : out std_logic; -- SDRAM Column Address Strobe
SDRAM_nRAS : out std_logic; -- SDRAM Row Address Strobe
SDRAM_BA : out std_logic_vector(1 downto 0); -- SDRAM Bank Address
SDRAM_CLK : out std_logic; -- SDRAM Clock
SDRAM_CKE: out std_logic; -- SDRAM Clock Enable
-- SPI
SPI_SCK : in std_logic;
SPI_DI : in std_logic;
SPI_DO : out std_logic;
SPI_SS2 : in std_logic;
SPI_SS3 : in std_logic;
CONF_DATA0 : in std_logic;
-- VGA output
VGA_HS, -- H_SYNC
VGA_VS : out std_logic; -- V_SYNC
VGA_R, -- Red[5:0]
VGA_G, -- Green[5:0]
VGA_B : out std_logic_vector(5 downto 0); -- Blue[5:0]
-- Audio
AUDIO_L,
AUDIO_R : out std_logic
);
end sms_mist;
architecture Behavioral of sms_mist is
component scandoubler is
port (
clk_in: in std_logic;
clk_out: in std_logic;
scanlines: in std_logic;
hs_in: in std_logic;
vs_in: in std_logic;
r_in: in std_logic_vector(5 downto 0);
g_in: in std_logic_vector(5 downto 0);
b_in: in std_logic_vector(5 downto 0);
r_out: out std_logic_vector(5 downto 0);
g_out: out std_logic_vector(5 downto 0);
b_out: out std_logic_vector(5 downto 0);
hs_out: out std_logic;
vs_out: out std_logic
);
end component;
component video is
port (
clk8: in std_logic;
pal: in std_logic;
x: out unsigned(8 downto 0);
y: out unsigned(7 downto 0);
color: in std_logic_vector(5 downto 0);
hsync: out std_logic;
vsync: out std_logic;
red: out std_logic_vector(1 downto 0);
green: out std_logic_vector(1 downto 0);
blue: out std_logic_vector(1 downto 0));
end component;
component sdram is
port( sd_data : inout std_logic_vector(15 downto 0);
sd_addr : out std_logic_vector(12 downto 0);
sd_dqm : out std_logic_vector(1 downto 0);
sd_ba : out std_logic_vector(1 downto 0);
sd_cs : out std_logic;
sd_we : out std_logic;
sd_ras : out std_logic;
sd_cas : out std_logic;
init : in std_logic;
clk : in std_logic;
clkref : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
addr : in std_logic_vector(24 downto 0);
oe : in std_logic;
we : in std_logic
);
end component;
constant CONF_STR : string := "SMS;SMS;O1,Video,NTSC,PAL;O2,Scanlines,Off,On;O3,Joysticks,Normal,Swapped;T4,Pause;T5,Reset";
function to_slv(s: string) return std_logic_vector is
constant ss: string(1 to s'length) := s;
variable rval: std_logic_vector(1 to 8 * s'length);
variable p: integer;
variable c: integer;
begin
for i in ss'range loop
p := 8 * i;
c := character'pos(ss(i));
rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8));
end loop;
return rval;
end function;
component user_io
generic ( STRLEN : integer := 0 );
port ( SPI_CLK, SPI_SS_IO, SPI_MOSI :in std_logic;
SPI_MISO : out std_logic;
conf_str : in std_logic_vector(8*STRLEN-1 downto 0);
JOY0 : out std_logic_vector(5 downto 0);
JOY1 : out std_logic_vector(5 downto 0);
status: out std_logic_vector(7 downto 0);
SWITCHES : out std_logic_vector(1 downto 0);
BUTTONS : out std_logic_vector(1 downto 0);
scandoubler_disable : out std_logic;
-- clk : in std_logic;
ps2_clk : out std_logic;
ps2_data : out std_logic
);
end component user_io;
component data_io is
port(sck: in std_logic;
ss: in std_logic;
sdi: in std_logic;
downloading: out std_logic;
size: out std_logic_vector(24 downto 0);
clk: in std_logic;
wr: out std_logic;
a: out std_logic_vector(24 downto 0);
d: out std_logic_vector(7 downto 0)
);
end component data_io;
component osd
port ( pclk, sck, ss, sdi, hs_in, vs_in : in std_logic;
red_in, blue_in, green_in : in std_logic_vector(5 downto 0);
red_out, blue_out, green_out : out std_logic_vector(5 downto 0);
hs_out, vs_out : out std_logic
);
end component osd;
signal clk_64M: std_logic;
signal clk_cpu: std_logic;
signal clk16: std_logic;
signal clk_div : unsigned(1 downto 0);
signal x: unsigned(8 downto 0);
signal y: unsigned(7 downto 0);
signal color: std_logic_vector(5 downto 0);
signal audio: std_logic;
signal pll_locked: std_logic;
signal ram_oe_n: STD_LOGIC;
signal ram_a: STD_LOGIC_VECTOR(21 downto 0);
signal sys_a: STD_LOGIC_VECTOR(21 downto 0);
signal ram_din: STD_LOGIC_VECTOR(7 downto 0);
signal ram_dout: STD_LOGIC_VECTOR(7 downto 0);
signal ram_we: std_logic;
signal ram_oe: std_logic;
signal sdram_dqm: std_logic_vector(1 downto 0);
signal switches : std_logic_vector(1 downto 0);
signal buttons : std_logic_vector(1 downto 0);
signal joy0 : std_logic_vector(5 downto 0);
signal joy1 : std_logic_vector(5 downto 0);
signal joya : std_logic_vector(5 downto 0);
signal joyb : std_logic_vector(5 downto 0);
signal scandoubler_disable : std_logic;
signal status : std_logic_vector(7 downto 0);
signal j1_tr : std_logic;
signal j2_tr : std_logic;
signal r : std_logic_vector(1 downto 0);
signal g : std_logic_vector(1 downto 0);
signal b : std_logic_vector(1 downto 0);
signal vs: std_logic;
signal hs: std_logic;
signal video_r: std_logic_vector(5 downto 0);
signal video_g: std_logic_vector(5 downto 0);
signal video_b: std_logic_vector(5 downto 0);
signal sd_r : std_logic_vector(5 downto 0);
signal sd_g : std_logic_vector(5 downto 0);
signal sd_b : std_logic_vector(5 downto 0);
signal sd_hs: std_logic;
signal sd_vs: std_logic;
signal osd_clk: std_logic;
signal osd_r : std_logic_vector(5 downto 0);
signal osd_g : std_logic_vector(5 downto 0);
signal osd_b : std_logic_vector(5 downto 0);
signal osd_hs : std_logic;
signal osd_vs : std_logic;
signal ioctl_wr : std_logic;
signal ioctl_addr : std_logic_vector(24 downto 0);
signal ioctl_data : std_logic_vector(7 downto 0);
signal ioctl_ram_addr : std_logic_vector(24 downto 0);
signal ioctl_ram_data : std_logic_vector(7 downto 0);
signal ioctl_ram_wr : std_logic := '0';
signal downl : std_logic := '0';
signal size : std_logic_vector(24 downto 0) := (others=>'0');
signal reset_n : std_logic := '1';
signal dbr : std_logic := '0';
begin
clock_inst: work.pll
port map (
inclk0 => CLOCK_27(0),
c0 => clk_64M,
c1 => SDRAM_CLK,
locked => pll_locked);
-- generate 16MHz video clock from 64MHz main clock by dividing it by 4
process(clk_64M)
begin
if rising_edge(clk_64M) then
clk_div <= clk_div + 1;
end if;
clk16 <= clk_div(1);
end process;
-- generate 8MHz system clock from 16MHz video clock
process(clk16)
begin
if rising_edge(clk16) then
clk_cpu <= not clk_cpu;
end if;
end process;
video_inst: video
port map (
clk8 => clk_cpu,
pal => status(1),
x => x,
y => y,
color => color,
hsync => hs,
vsync => vs,
red => r,
green => g,
blue => b
);
video_r <= r & r & r;
video_g <= g & g & g;
video_b <= b & b & b;
scandouble_inst: scandoubler
port map(
clk_in => clk_cpu,
clk_out => clk16,
scanlines => status(2),
hs_in => hs,
vs_in => vs,
r_in => video_r,
g_in => video_g,
b_in => video_b,
r_out => sd_r,
g_out => sd_g,
b_out => sd_b,
hs_out => sd_hs,
vs_out => sd_vs
);
--scandoubler_disable <= '1';
VGA_HS <= not(hs xor vs) when scandoubler_disable = '1' else sd_hs;
VGA_VS <= '1' when scandoubler_disable = '1' else sd_vs;
osd_clk <= clk_cpu when scandoubler_disable = '1' else clk16;
osd_hs <= hs when scandoubler_disable = '1' else sd_hs;
osd_vs <= vs when scandoubler_disable = '1' else sd_vs;
osd_r <= video_r when scandoubler_disable = '1' else sd_r;
osd_g <= video_g when scandoubler_disable = '1' else sd_g;
osd_b <= video_b when scandoubler_disable = '1' else sd_b;
osd_inst : osd
port map (
pclk => osd_clk,
sdi => SPI_DI,
sck => SPI_SCK,
ss => SPI_SS3,
red_in => osd_r,
green_in => osd_g,
blue_in => osd_b,
hs_in => osd_hs,
vs_in => osd_vs,
red_out => VGA_R,
green_out => VGA_G,
blue_out => VGA_B
);
-- sdram interface
SDRAM_CKE <= '1';
SDRAM_DQMH <= sdram_dqm(1);
SDRAM_DQML <= sdram_dqm(0);
sdram_inst : sdram
port map( sd_data => SDRAM_DQ,
sd_addr => SDRAM_A,
sd_dqm => sdram_dqm,
sd_cs => SDRAM_nCS,
sd_ba => SDRAM_BA,
sd_we => SDRAM_nWE,
sd_ras => SDRAM_nRAS,
sd_cas => SDRAM_nCAS,
clk => clk_64M,
clkref => clk_cpu,
init => not pll_locked,
din => ram_din,
addr => "000" & ram_a,
we => ram_we,
oe => ram_oe,
dout => ram_dout
);
ram_a <= ioctl_ram_addr(21 downto 0) when downl = '1' else sys_a;
ram_din <= ioctl_ram_data;
ram_we <= '1' when ioctl_ram_wr = '1' else '0';
ram_oe <= '0' when downl = '1' else not ram_oe_n;
data_io_inst: data_io
port map(SPI_SCK, SPI_SS2, SPI_DI, downl, size, clk_cpu, ioctl_wr, ioctl_addr, ioctl_data);
process(clk_cpu)
begin
if falling_edge(clk_cpu) then
if downl='1' then
reset_n <= '0';
dbr <= '1';
else
reset_n <= '1';
end if;
if ioctl_wr ='1' then
-- io controller sent a new byte.
ioctl_ram_wr <= '1';
ioctl_ram_addr <= ioctl_addr;
ioctl_ram_data <= ioctl_data;
else
ioctl_ram_wr <= '0';
end if;
end if;
end process;
user_io_d : user_io
generic map (STRLEN => CONF_STR'length)
port map (
SPI_CLK => SPI_SCK,
SPI_SS_IO => CONF_DATA0,
SPI_MISO => SPI_DO,
SPI_MOSI => SPI_DI,
conf_str => to_slv(CONF_STR),
status => status,
JOY0 => joy0,
JOY1 => joy1,
SWITCHES => switches,
BUTTONS => buttons,
scandoubler_disable => scandoubler_disable,
-- clk => open,
ps2_clk => open,
ps2_data => open
);
-- joysticks can be swapped
joya <= joy1 when status(3)='0' else joy0;
joyb <= joy0 when status(3)='0' else joy1;
system_inst: work.system
port map (
clk_cpu => clk_cpu,
clk_vdp => clk_cpu,
-- ram interface used for cartridge emulation
ram_oe_n => ram_oe_n,
ram_a => sys_a,
ram_do => ram_dout,
-- buttons and joysticks
j1_up => not joya(3),
j1_down => not joya(2),
j1_left => not joya(1),
j1_right => not joya(0),
j1_tl => not joya(4),
j1_tr => not joya(5),
j2_up => not joyb(3),
j2_down => not joyb(2),
j2_left => not joyb(1),
j2_right => not joyb(0),
j2_tl => not joyb(4),
j2_tr => not joyb(5),
reset => not buttons(1) and not status(5) and not status(0) and pll_locked and reset_n,
pause => not status(4),
-- video
x => x,
y => y,
color => color,
audio => audio,
dbr => dbr
);
AUDIO_L <= audio;
AUDIO_R <= audio;
end Behavioral;

90
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@@ -1,90 +0,0 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY spram IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED"
);
PORT
(
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END spram;
ARCHITECTURE SYN OF spram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => outdata_reg_a,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => widthad_a,
width_a => width_a,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => address,
data_a => data,
q_a => sub_wire0
);
END SYN;

82
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sprom IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED"
);
PORT
(
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END sprom;
ARCHITECTURE SYN OF sprom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => outdata_reg_a,
widthad_a => widthad_a,
width_a => width_a,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
END SYN;

373
cores/sms/src/system.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.all;
entity system is
port (
clk_cpu: in STD_LOGIC;
clk_vdp: in STD_LOGIC;
ram_oe_n: out STD_LOGIC;
ram_a: out STD_LOGIC_VECTOR(21 downto 0);
ram_do: in STD_LOGIC_VECTOR(7 downto 0);
j1_up: in STD_LOGIC;
j1_down: in STD_LOGIC;
j1_left: in STD_LOGIC;
j1_right: in STD_LOGIC;
j1_tl: in STD_LOGIC;
j1_tr: in STD_LOGIC;
j2_up: in STD_LOGIC;
j2_down: in STD_LOGIC;
j2_left: in STD_LOGIC;
j2_right: in STD_LOGIC;
j2_tl: in STD_LOGIC;
j2_tr: in STD_LOGIC;
reset: in STD_LOGIC;
pause: in STD_LOGIC;
x: in UNSIGNED(8 downto 0);
y: in UNSIGNED(7 downto 0);
color: out STD_LOGIC_VECTOR(5 downto 0);
audio: out STD_LOGIC;
dbr: in STD_LOGIC);
end system;
architecture Behavioral of system is
-- component dummy_z80 is
component T80se is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
port(
RESET_n: in std_logic;
CLK_n: in std_logic;
CLKEN: in std_logic;
WAIT_n: in std_logic;
INT_n: in std_logic;
NMI_n: in std_logic;
BUSRQ_n: in std_logic;
M1_n: out std_logic;
MREQ_n: out std_logic;
IORQ_n: out std_logic;
RD_n: out std_logic;
WR_n: out std_logic;
RFSH_n: out std_logic;
HALT_n: out std_logic;
BUSAK_n: out std_logic;
A: out std_logic_vector(15 downto 0);
DI: in std_logic_vector(7 downto 0);
DO: out std_logic_vector(7 downto 0)
);
end component;
component vdp is
port (
cpu_clk: in STD_LOGIC;
vdp_clk: in STD_LOGIC;
RD_n: in STD_LOGIC;
WR_n: in STD_LOGIC;
IRQ_n: out STD_LOGIC;
A: in STD_LOGIC_VECTOR(7 downto 0);
D_in: in STD_LOGIC_VECTOR(7 downto 0);
D_out: out STD_LOGIC_VECTOR(7 downto 0);
x: in unsigned(8 downto 0);
y: in unsigned(7 downto 0);
color: out std_logic_vector (5 downto 0));
end component;
component psg is
port (
clk: in STD_LOGIC;
WR_n: in STD_LOGIC;
D_in: in STD_LOGIC_VECTOR (7 downto 0);
output: out STD_LOGIC);
end component;
component io is
port (
clk: in STD_LOGIC;
WR_n: in STD_LOGIC;
RD_n: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (7 downto 0);
D_in: in STD_LOGIC_VECTOR (7 downto 0);
D_out: out STD_LOGIC_VECTOR (7 downto 0);
J1_up: in STD_LOGIC;
J1_down: in STD_LOGIC;
J1_left: in STD_LOGIC;
J1_right: in STD_LOGIC;
J1_tl: in STD_LOGIC;
J1_tr: in STD_LOGIC;
J2_up: in STD_LOGIC;
J2_down: in STD_LOGIC;
J2_left: in STD_LOGIC;
J2_right: in STD_LOGIC;
J2_tl: in STD_LOGIC;
J2_tr: in STD_LOGIC;
RESET: in STD_LOGIC);
end component;
signal RESET_n: std_logic;
signal RD_n: std_logic;
signal WR_n: std_logic;
signal IRQ_n: std_logic;
signal IO_n: std_logic;
signal A: std_logic_vector(15 downto 0);
signal D_in: std_logic_vector(7 downto 0);
signal D_out: std_logic_vector(7 downto 0);
signal vdp_RD_n: std_logic;
signal vdp_WR_n: std_logic;
signal vdp_D_out: std_logic_vector(7 downto 0);
signal psg_WR_n: std_logic;
signal ctl_WR_n: std_logic;
signal io_RD_n: std_logic;
signal io_WR_n: std_logic;
signal io_D_out: std_logic_vector(7 downto 0);
signal ram_WR_n: std_logic;
signal ram_D_out: std_logic_vector(7 downto 0);
signal cart_ram_D_out:std_logic_vector(7 downto 0);
signal rom_WR_n: std_logic;
signal boot_rom_D_out: std_logic_vector(7 downto 0);
signal reset_counter: unsigned(3 downto 0) := "1111";
signal bootloader: std_logic := '0';
signal irom_D_out: std_logic_vector(7 downto 0);
signal irom_RD_n: std_logic := '1';
signal bank0: std_logic_vector(7 downto 0) := "00000000";
signal bank1: std_logic_vector(7 downto 0) := "00000001";
signal bank2: std_logic_vector(7 downto 0) := "00000010";
signal ram_e: std_logic := '0';
begin
-- z80_inst: dummy_z80
z80_inst: T80se
port map(
RESET_n => RESET_n and reset,
CLK_n => clk_cpu,
CLKEN => '1',
WAIT_n => '1',
INT_n => IRQ_n,
NMI_n => pause,
BUSRQ_n => '1',
M1_n => open,
MREQ_n => open,
IORQ_n => IO_n,
RD_n => RD_n,
WR_n => WR_n,
RFSH_n => open,
HALT_n => open,
BUSAK_n => open,
A => A,
DI => D_out,
DO => D_in
);
vdp_inst: vdp
port map (
cpu_clk => clk_cpu,
vdp_clk => clk_vdp,
RD_n => vdp_RD_n,
WR_n => vdp_WR_n,
IRQ_n => IRQ_n,
A => A(7 downto 0),
D_in => D_in,
D_out => vdp_D_out,
x => x,
y => y,
color => color);
psg_inst: psg
port map (
clk => clk_cpu,
WR_n => psg_WR_n,
D_in => D_in,
output => audio);
io_inst: io
port map (
clk => clk_cpu,
WR_n => io_WR_n,
RD_n => io_RD_n,
A => A(7 downto 0),
D_in => D_in,
D_out => io_D_out,
J1_up => j1_up,
J1_down => j1_down,
J1_left => j1_left,
J1_right => j1_right,
J1_tl => j1_tl,
J1_tr => j1_tr,
J2_up => j2_up,
J2_down => j2_down,
J2_left => j2_left,
J2_right => j2_right,
J2_tl => j2_tl,
J2_tr => j2_tr,
RESET => reset);
ram_inst : entity work.spram
generic map
(
widthad_a => 13
)
port map
(
clock => clk_cpu,
address => A(12 downto 0),
wren => not ram_WR_n,
data => D_in,
q => ram_D_out
);
ram_inst2 : entity work.spram
generic map
(
widthad_a => 13
)
port map
(
clock => clk_cpu,
address => A(12 downto 0),
wren => not ram_WR_n,
data => D_in,
q => cart_ram_D_out
);
boot_rom_inst : entity work.sprom
generic map
(
init_file => "mboot.mif",
widthad_a => 14
)
port map
(
clock => clk_cpu,
address => A(13 downto 0),
q => boot_rom_D_out
);
-- glue logic
vdp_WR_n <= WR_n when io_n='0' and A(7 downto 6)="10" else '1';
vdp_RD_n <= RD_n when io_n='0' and (A(7 downto 6)="01" or A(7 downto 6)="10") else '1';
psg_WR_n <= WR_n when io_n='0' and A(7 downto 6)="01" else '1';
ctl_WR_n <= WR_n when io_n='0' and A(7 downto 6)="00" and A(0)='0' else '1';
io_WR_n <= WR_n when io_n='0' and A(7 downto 6)="00" and A(0)='1' else '1';
io_RD_n <= RD_n when io_n='0' and A(7 downto 6)="11" else '1';
ram_WR_n <= WR_n when io_n='1' and A(15 downto 14)="11" else '1';
process (clk_cpu)
begin
if rising_edge(clk_cpu) then
if reset='0' then
bootloader <= '0';
end if;
-- memory control
if reset_counter>0 then
reset_counter <= reset_counter - 1;
elsif ctl_WR_n='0' then
if bootloader='0' then
bootloader <= '1';
reset_counter <= (others=>'1');
end if;
end if;
end if;
end process;
reset_n <= '0' when reset_counter>0 else '1';
irom_D_out <= boot_rom_D_out when bootloader='0' and A(15 downto 14)="00" and dbr='0' else ram_do;
process (io_n,A,vdp_D_out,io_D_out,irom_D_out,ram_D_out)
begin
if io_n='0' then
case A(7 downto 6) is
when "11" =>
D_out <= io_D_out;
when others =>
D_out <= vdp_D_out;
end case;
else
if A(15 downto 14)="11" then
D_out <= ram_D_out;
elsif (A(15 downto 14)="10" and ram_e='1') then
D_out <= cart_ram_D_out;
else
D_out <= irom_D_out;
end if;
end if;
end process;
-- external ram control
process (clk_cpu)
begin
if(RESET_n='0' or reset='0') then
bank0 <= "00000000";
bank1 <= "00000001";
bank2 <= "00000010";
else
if rising_edge(clk_cpu) then
if WR_n='0' and A(15 downto 2)="11111111111111" then
case A(1 downto 0) is
when "00" =>
if (D_in(3) = '1') then
ram_e <= '1';
end if;
when "01" => bank0 <= D_in;
when "10" => bank1 <= D_in;
when "11" => bank2 <= D_in;
when others =>
end case;
end if;
end if;
end if;
end process;
ram_oe_n <= RD_n;
ram_a(13 downto 0) <= A(13 downto 0);
process (reset,A,bank0,bank1,bank2)
begin
case A(15 downto 14) is
when "00" =>
-- first kilobyte is always from bank 0
if A(13 downto 10)="0000" then
ram_a(21 downto 14) <= (others=>'0');
else
ram_a(21 downto 14) <= bank0;
end if;
when "01" =>
ram_a(21 downto 14) <= bank1;
when others =>
if(ram_e) = '0' then
ram_a(21 downto 14) <= bank2;
end if;
end case;
end process;
end Behavioral;

191
cores/sms/src/user_io.v
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@@ -1,191 +0,0 @@
//
// user_io.v
//
// user_io for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// parameter STRLEN and the actual length of conf_str have to match
module user_io #(parameter STRLEN=0) (
input [(8*STRLEN)-1:0] conf_str,
input SPI_CLK,
input SPI_SS_IO,
output reg SPI_MISO,
input SPI_MOSI,
output [5:0] JOY0,
output [5:0] JOY1,
output [1:0] BUTTONS,
output [1:0] SWITCHES,
output scandoubler_disable,
output reg [7:0] status,
input clk,
output ps2_clk,
output reg ps2_data
);
reg [6:0] sbuf;
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [7:0] byte_cnt; // counts bytes
reg [5:0] joystick0;
reg [5:0] joystick1;
reg [4:0] but_sw;
assign JOY0 = joystick0;
assign JOY1 = joystick1;
assign BUTTONS = but_sw[1:0];
assign SWITCHES = but_sw[3:2];
assign scandoubler_disable = but_sw[4];
// this variant of user_io is for 8 bit cores (type == a4) only
wire [7:0] core_type = 8'ha4;
// drive MISO only when transmitting core id
always@(negedge SPI_CLK or posedge SPI_SS_IO) begin
if(SPI_SS_IO == 1) begin
SPI_MISO <= 1'bZ;
end else begin
// first byte returned is always core type, further bytes are
// command dependent
if(byte_cnt == 0) begin
SPI_MISO <= core_type[~bit_cnt];
end else begin
// reading config string
if(cmd == 8'h14) begin
// returning a byte from string
if(byte_cnt < STRLEN + 1)
SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
else
SPI_MISO <= 1'b0;
end
end
end
end
// 8 byte fifo to store ps2 bytes
localparam PS2_FIFO_BITS = 3;
reg [7:0] ps2_fifo [(2**PS2_FIFO_BITS)-1:0];
reg [PS2_FIFO_BITS-1:0] ps2_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_tx_state;
reg [7:0] ps2_tx_byte;
reg ps2_parity;
assign ps2_clk = clk || (ps2_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_r_inc;
always@(posedge clk) begin
ps2_r_inc <= 1'b0;
if(ps2_r_inc)
ps2_rptr <= ps2_rptr + 1;
// transmitter is idle?
if(ps2_tx_state == 0) begin
// data in fifo present?
if(ps2_wptr != ps2_rptr) begin
// load tx register from fifo
ps2_tx_byte <= ps2_fifo[ps2_rptr];
ps2_r_inc <= 1'b1;
// reset parity
ps2_parity <= 1'b1;
// start transmitter
ps2_tx_state <= 4'd1;
// put start bit on data line
ps2_data <= 1'b0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_tx_state >= 1)&&(ps2_tx_state < 9)) begin
ps2_data <= ps2_tx_byte[0]; // data bits
ps2_tx_byte[6:0] <= ps2_tx_byte[7:1]; // shift down
if(ps2_tx_byte[0])
ps2_parity <= !ps2_parity;
end
// transmission of parity
if(ps2_tx_state == 9)
ps2_data <= ps2_parity;
// transmission of stop bit
if(ps2_tx_state == 10)
ps2_data <= 1'b1; // stop bit is 1
// advance state machine
if(ps2_tx_state < 11)
ps2_tx_state <= ps2_tx_state + 4'd1;
else
ps2_tx_state <= 4'd0;
end
end
// SPI receiver
always@(posedge SPI_CLK or posedge SPI_SS_IO) begin
if(SPI_SS_IO == 1) begin
bit_cnt <= 3'd0;
byte_cnt <= 8'd0;
end else begin
sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
bit_cnt <= bit_cnt + 3'd1;
if(bit_cnt == 7) byte_cnt <= byte_cnt + 8'd1;
// finished reading command byte
if(bit_cnt == 7) begin
if(byte_cnt == 0)
cmd <= { sbuf, SPI_MOSI};
if(byte_cnt != 0) begin
if(cmd == 8'h01)
but_sw <= { sbuf[3:0], SPI_MOSI };
if(cmd == 8'h02)
joystick0 <= { sbuf[4:0], SPI_MOSI };
if(cmd == 8'h03)
joystick1 <= { sbuf[4:0], SPI_MOSI };
if(cmd == 8'h05) begin
// store incoming keyboard bytes in
ps2_fifo[ps2_wptr] <= { sbuf, SPI_MOSI };
ps2_wptr <= ps2_wptr + 1;
end
if(cmd == 8'h15) begin
status <= { sbuf[4:0], SPI_MOSI };
end
end
end
end
end
endmodule

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cores/sms/src/vdp.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vdp is
port (
cpu_clk: in STD_LOGIC;
vdp_clk: in STD_LOGIC;
RD_n: in STD_LOGIC;
WR_n: in STD_LOGIC;
IRQ_n: out STD_LOGIC;
A: in STD_LOGIC_VECTOR (7 downto 0);
D_in: in STD_LOGIC_VECTOR (7 downto 0);
D_out: out STD_LOGIC_VECTOR (7 downto 0);
x: unsigned(8 downto 0);
y: unsigned(7 downto 0);
color: out std_logic_vector (5 downto 0));
end vdp;
architecture Behavioral of vdp is
component vdp_main is
port (
clk: in std_logic;
vram_A: out std_logic_vector(13 downto 0);
vram_D: in std_logic_vector(7 downto 0);
cram_A: out std_logic_vector(4 downto 0);
cram_D: in std_logic_vector(5 downto 0);
x: unsigned(8 downto 0);
y: unsigned(7 downto 0);
color: out std_logic_vector (5 downto 0);
display_on: in std_logic;
mask_column0: in std_logic;
overscan: in std_logic_vector (3 downto 0);
bg_address: in std_logic_vector (2 downto 0);
bg_scroll_x: in unsigned(7 downto 0);
bg_scroll_y: in unsigned(7 downto 0);
disable_hscroll: in std_logic;
spr_address: in std_logic_vector (5 downto 0);
spr_high_bit: in std_logic;
spr_shift: in std_logic;
spr_tall: in std_logic);
end component;
component vdp_cram is
port (
cpu_clk: in STD_LOGIC;
cpu_WE: in std_logic;
cpu_A: in std_logic_vector(4 downto 0);
cpu_D: in std_logic_vector(5 downto 0);
vdp_clk: in STD_LOGIC;
vdp_A: in std_logic_vector(4 downto 0);
vdp_D: out std_logic_vector(5 downto 0));
end component;
-- helper bits
signal data_write: std_logic;
signal address_ff: std_logic := '0';
signal to_cram: boolean := false;
-- vram and cram lines for the cpu interface
signal xram_cpu_A: std_logic_vector(13 downto 0);
signal vram_cpu_WE: std_logic;
signal cram_cpu_WE: std_logic;
signal vram_cpu_D_out: std_logic_vector(7 downto 0);
signal xram_cpu_A_incr: std_logic := '0';
-- vram and cram lines for the video interface
signal vram_vdp_A: std_logic_vector(13 downto 0);
signal vram_vdp_D: std_logic_vector(7 downto 0);
signal cram_vdp_A: std_logic_vector(4 downto 0);
signal cram_vdp_D: std_logic_vector(5 downto 0);
-- control bits
signal display_on: std_logic := '1';
signal disable_hscroll: std_logic := '0';
signal mask_column0: std_logic := '0';
signal overscan: std_logic_vector (3 downto 0) := "0000";
signal irq_frame_en: std_logic := '0';
signal irq_line_en: std_logic := '0';
signal irq_line_count: unsigned(7 downto 0) := (others=>'1');
signal bg_address: std_logic_vector (2 downto 0) := (others=>'0');
signal bg_scroll_x: unsigned(7 downto 0) := (others=>'0');
signal bg_scroll_y: unsigned(7 downto 0) := (others=>'0');
signal spr_address: std_logic_vector (5 downto 0) := (others=>'0');
signal spr_shift: std_logic := '0';
signal spr_tall: std_logic := '0';
signal spr_high_bit: std_logic := '0';
-- various counters
signal last_y0: std_logic := '0';
signal vbi_done: std_logic := '0';
signal virq_flag: std_logic := '0';
signal reset_virq_flag: boolean := false;
signal irq_counter: unsigned(5 downto 0) := (others=>'0');
signal hbl_counter: unsigned(7 downto 0) := (others=>'0');
signal vbl_irq: std_logic;
signal hbl_irq: std_logic;
begin
vdp_main_inst: vdp_main
port map(
clk => vdp_clk,
vram_A => vram_vdp_A,
vram_D => vram_vdp_D,
cram_A => cram_vdp_A,
cram_D => cram_vdp_D,
x => x,
y => y,
color => color,
display_on => display_on,
mask_column0 => mask_column0,
overscan => overscan,
bg_address => bg_address,
bg_scroll_x => bg_scroll_x,
bg_scroll_y => bg_scroll_y,
disable_hscroll=>disable_hscroll,
spr_address => spr_address,
spr_high_bit => spr_high_bit,
spr_shift => spr_shift,
spr_tall => spr_tall);
vdp_vram_inst : entity work.dpram
generic map
(
init_file => "vram.mif",
widthad_a => 14
)
port map
(
clock_a => cpu_clk,
address_a => xram_cpu_A(13 downto 0),
wren_a => vram_cpu_WE,
data_a => D_in,
q_a => vram_cpu_D_out,
clock_b => not vdp_clk,
address_b => vram_vdp_A,
wren_b => '0',
data_b => (others => '0'),
q_b => vram_vdp_D
);
vdp_cram_inst: vdp_cram
port map (
cpu_clk => cpu_clk,
cpu_WE => cram_cpu_WE,
cpu_A => xram_cpu_A(4 downto 0),
cpu_D => D_in(5 downto 0),
vdp_clk => vdp_clk,
vdp_A => cram_vdp_A,
vdp_D => cram_vdp_D);
data_write <= not WR_n and not A(0);
cram_cpu_WE <= data_write when to_cram else '0';
vram_cpu_WE <= data_write when not to_cram else '0';
process (cpu_clk)
begin
if rising_edge(cpu_clk) then
if WR_n='0' then
if A(0)='0' then
xram_cpu_A_incr <= '1';
else
if address_ff='0' then
xram_cpu_A(7 downto 0) <= D_in;
else
xram_cpu_A(13 downto 8) <= D_in(5 downto 0);
to_cram <= D_in(7 downto 6)="11";
case D_in is
when "10000000" =>
disable_hscroll<= xram_cpu_A(6);
mask_column0 <= xram_cpu_A(5);
irq_line_en <= xram_cpu_A(4);
spr_shift <= xram_cpu_A(3);
when "10000001" =>
display_on <= xram_cpu_A(6);
irq_frame_en <= xram_cpu_A(5);
spr_tall <= xram_cpu_A(1);
when "10000010" =>
bg_address <= xram_cpu_A(3 downto 1);
when "10000101" =>
spr_address <= xram_cpu_A(6 downto 1);
when "10000110" =>
spr_high_bit <= xram_cpu_A(2);
when "10000111" =>
overscan <= xram_cpu_A(3 downto 0);
when "10001000" =>
bg_scroll_x <= unsigned(xram_cpu_A(7 downto 0));
when "10001001" =>
bg_scroll_y <= unsigned(xram_cpu_A(7 downto 0));
when "10001010" =>
irq_line_count <= unsigned(xram_cpu_A(7 downto 0));
when others =>
end case;
end if;
address_ff <= not address_ff;
end if;
elsif RD_n='0' then
case A(7 downto 6)&A(0) is
when "010" =>
D_out <= std_logic_vector(y);
when "011" =>
D_out <= "11111111"; -- std_logic_vector(x(7 downto 0)); -- bad in VGA mode ...
when "100" =>
D_out <= vram_cpu_D_out;
xram_cpu_A_incr <= '1';
when "101" =>
D_out(7) <= virq_flag;
D_out(6 downto 0) <= (others=>'0');
reset_virq_flag <= true;
when others =>
end case;
elsif xram_cpu_A_incr='1' then
xram_cpu_A <= std_logic_vector(unsigned(xram_cpu_A) + 1);
xram_cpu_A_incr <= '0';
else
reset_virq_flag <= false;
end if;
end if;
end process;
process (vdp_clk)
begin
if rising_edge(vdp_clk) then
-- we need to make sure we only send one vbi per image since the
-- y counter repeats within the image and the value 192 occurs twice
if y=0 then
vbi_done <= '0';
end if;
if x=256 and y=192 and not (last_y0=std_logic(y(0))) then
if(vbi_done='0') then
vbl_irq <= irq_frame_en;
vbi_done <= '1';
end if;
else
vbl_irq <= '0';
end if;
end if;
end process;
process (vdp_clk)
begin
if rising_edge(vdp_clk) then
if x=256 and not (last_y0=std_logic(y(0))) then
last_y0 <= std_logic(y(0));
if y<192 then
if hbl_counter=0 then
hbl_irq <= irq_line_en;
hbl_counter <= irq_line_count;
else
hbl_counter <= hbl_counter-1;
end if;
else
hbl_counter <= irq_line_count;
end if;
else
hbl_irq <= '0';
end if;
end if;
end process;
process (vdp_clk)
begin
if rising_edge(vdp_clk) then
if vbl_irq='1' then
virq_flag <= '1';
elsif reset_virq_flag then
virq_flag <= '0';
end if;
end if;
end process;
process (vdp_clk)
begin
if rising_edge(vdp_clk) then
if vbl_irq='1' or hbl_irq='1' then
irq_counter <= (others=>'1');
elsif irq_counter>0 then
irq_counter <= irq_counter-1;
end if;
end if;
end process;
IRQ_n <= '0' when irq_counter>0 else '1';
end Behavioral;

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cores/sms/src/vdp_background.vhd
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library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity vdp_background is
port (
clk: in std_logic;
reset: in std_logic;
table_address: in std_logic_vector(13 downto 11);
scroll_x: in unsigned(7 downto 0);
disable_hscroll: in std_logic;
y: in unsigned(7 downto 0);
vram_A: out std_logic_vector(13 downto 0);
vram_D: in std_logic_vector(7 downto 0);
color: out std_logic_vector(4 downto 0);
priority: out std_logic
);
end entity;
architecture rtl of vdp_background is
signal tile_index : std_logic_vector (8 downto 0);
signal x : unsigned (7 downto 0);
signal tile_y : std_logic_vector (2 downto 0);
signal palette : std_logic;
signal priority_latch: std_logic;
signal flip_x : std_logic;
signal data0 : std_logic_vector(7 downto 0);
signal data1 : std_logic_vector(7 downto 0);
signal data2 : std_logic_vector(7 downto 0);
signal data3 : std_logic_vector(7 downto 0);
signal shift0 : std_logic_vector(7 downto 0);
signal shift1 : std_logic_vector(7 downto 0);
signal shift2 : std_logic_vector(7 downto 0);
signal shift3 : std_logic_vector(7 downto 0);
begin
process (clk) begin
if (rising_edge(clk)) then
if (reset='1') then
if disable_hscroll='0' or y>=16 then
x <= 240-scroll_x;
else
x <= "11110000"; -- 240
end if;
else
x <= x + 1;
end if;
end if;
end process;
process (clk)
variable char_address : std_logic_vector(12 downto 0);
variable data_address : std_logic_vector(11 downto 0);
begin
if (rising_edge(clk)) then
char_address(12 downto 10) := table_address;
char_address(9 downto 5) := std_logic_vector(y(7 downto 3));
char_address(4 downto 0) := std_logic_vector(x(7 downto 3) + 1);
data_address := tile_index & tile_y;
case x(2 downto 0) is
when "000" => vram_A <= char_address & "0";
when "001" => vram_A <= char_address & "1";
when "011" => vram_A <= data_address & "00";
when "100" => vram_A <= data_address & "01";
when "101" => vram_A <= data_address & "10";
when "110" => vram_A <= data_address & "11";
when others =>
end case;
end if;
end process;
process (clk) begin
if (rising_edge(clk)) then
case x(2 downto 0) is
when "001" =>
tile_index(7 downto 0) <= vram_D;
when "010" =>
tile_index(8) <= vram_D(0);
flip_x <= vram_D(1);
tile_y(0) <= y(0) xor vram_D(2);
tile_y(1) <= y(1) xor vram_D(2);
tile_y(2) <= y(2) xor vram_D(2);
palette <= vram_D(3);
priority_latch <= vram_D(4);
when "100" =>
data0 <= vram_D;
when "101" =>
data1 <= vram_D;
when "110" =>
data2 <= vram_D;
-- when "111" =>
-- data3 <= vram_D;
when others =>
end case;
end if;
end process;
process (clk) begin
if (rising_edge(clk)) then
case x(2 downto 0) is
when "111" =>
if flip_x='0' then
shift0 <= data0;
shift1 <= data1;
shift2 <= data2;
shift3 <= vram_D;
else
shift0 <= data0(0)&data0(1)&data0(2)&data0(3)&data0(4)&data0(5)&data0(6)&data0(7);
shift1 <= data1(0)&data1(1)&data1(2)&data1(3)&data1(4)&data1(5)&data1(6)&data1(7);
shift2 <= data2(0)&data2(1)&data2(2)&data2(3)&data2(4)&data2(5)&data2(6)&data2(7);
shift3 <= vram_D(0)&vram_D(1)&vram_D(2)&vram_D(3)&vram_D(4)&vram_D(5)&vram_D(6)&vram_D(7);
end if;
color(4) <= palette;
priority <= priority_latch;
when others =>
shift0(7 downto 1) <= shift0(6 downto 0);
shift1(7 downto 1) <= shift1(6 downto 0);
shift2(7 downto 1) <= shift2(6 downto 0);
shift3(7 downto 1) <= shift3(6 downto 0);
end case;
end if;
end process;
color(0) <= shift0(7);
color(1) <= shift1(7);
color(2) <= shift2(7);
color(3) <= shift3(7);
end architecture;

44
cores/sms/src/vdp_cram.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vdp_cram is
port (
cpu_clk: in STD_LOGIC;
cpu_WE: in STD_LOGIC;
cpu_A: in STD_LOGIC_VECTOR (4 downto 0);
cpu_D: in STD_LOGIC_VECTOR (5 downto 0);
vdp_clk: in STD_LOGIC;
vdp_A: in STD_LOGIC_VECTOR (4 downto 0);
vdp_D: out STD_LOGIC_VECTOR (5 downto 0));
end vdp_cram;
architecture Behavioral of vdp_cram is
type t_ram is array (0 to 31) of std_logic_vector(5 downto 0);
signal ram : t_ram := (others => "111111");
begin
process (cpu_clk)
variable i : integer range 0 to 31;
begin
if rising_edge(cpu_clk) then
if cpu_WE='1'then
i := to_integer(unsigned(cpu_A));
ram(i) <= cpu_D;
end if;
end if;
end process;
process (vdp_clk)
variable i : integer range 0 to 31;
begin
if rising_edge(vdp_clk) then
i := to_integer(unsigned(vdp_A));
vdp_D <= ram(i);
end if;
end process;
end Behavioral;

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cores/sms/src/vdp_main.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vdp_main is
port (
clk: in std_logic;
vram_A: out std_logic_vector(13 downto 0);
vram_D: in std_logic_vector(7 downto 0);
cram_A: out std_logic_vector(4 downto 0);
cram_D: in std_logic_vector(5 downto 0);
x: unsigned(8 downto 0);
y: unsigned(7 downto 0);
color: out std_logic_vector (5 downto 0);
display_on: in std_logic;
mask_column0: in std_logic;
overscan: in std_logic_vector (3 downto 0);
bg_address: in std_logic_vector (2 downto 0);
bg_scroll_x: in unsigned(7 downto 0);
bg_scroll_y: in unsigned(7 downto 0);
disable_hscroll: in std_logic;
spr_address: in std_logic_vector (5 downto 0);
spr_high_bit: in std_logic;
spr_shift: in std_logic;
spr_tall: in std_logic);
end vdp_main;
architecture Behavioral of vdp_main is
component vdp_background is
port (
clk: in std_logic;
reset: in std_logic;
table_address: in std_logic_vector(13 downto 11);
scroll_x: in unsigned(7 downto 0);
disable_hscroll: in std_logic;
y: in unsigned(7 downto 0);
vram_A: out std_logic_vector(13 downto 0);
vram_D: in std_logic_vector(7 downto 0);
color: out std_logic_vector(4 downto 0);
priority: out std_logic);
end component;
component vdp_sprites is
port (
clk: in std_logic;
table_address: in std_logic_vector(13 downto 8);
char_high_bit: in std_logic;
tall: in std_logic;
x: in unsigned(8 downto 0);
y: in unsigned(7 downto 0);
vram_A: out std_logic_vector(13 downto 0);
vram_D: in std_logic_vector(7 downto 0);
color: out std_logic_vector(3 downto 0));
end component;
signal bg_y: unsigned(7 downto 0);
signal bg_vram_A: std_logic_vector(13 downto 0);
signal bg_color: std_logic_vector(4 downto 0);
signal bg_priority: std_logic;
signal spr_vram_A: std_logic_vector(13 downto 0);
signal spr_color: std_logic_vector(3 downto 0);
signal line_reset: std_logic;
begin
process (y,bg_scroll_y)
variable sum: unsigned(8 downto 0);
begin
sum := ('0'&y)+('0'&bg_scroll_y);
if (sum>=224) then
sum := sum-224;
end if;
bg_y <= sum(7 downto 0);
end process;
line_reset <= '1' when x=512-16 else '0';
vdp_bg_inst: vdp_background
port map (
clk => clk,
table_address => bg_address,
reset => line_reset,
disable_hscroll=> disable_hscroll,
scroll_x => bg_scroll_x,
y => bg_y,
vram_A => bg_vram_A,
vram_D => vram_D,
color => bg_color,
priority => bg_priority);
vdp_spr_inst: vdp_sprites
port map (
clk => clk,
table_address => spr_address,
char_high_bit => spr_high_bit,
tall => spr_tall,
x => x,
y => y,
vram_A => spr_vram_A,
vram_D => vram_D,
color => spr_color);
process (x, y, bg_priority, spr_color, bg_color, overscan)
variable spr_active : boolean;
variable bg_active : boolean;
begin
if x<256 and y<192 and (mask_column0='0' or x>=8) then
spr_active := not (spr_color="0000");
bg_active := not (bg_color(3 downto 0)="0000");
if (bg_priority='0' and spr_active) or (bg_priority='1' and not bg_active) then
cram_A <= "1"&spr_color;
else
cram_A <= bg_color;
end if;
else
cram_A <= "1"&overscan;
end if;
end process;
vram_A <= spr_vram_A when x>=256 and x<384 else bg_vram_A;
color <= cram_D;
end Behavioral;

48
cores/sms/src/vdp_sprite_shifter.vhd
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@@ -1,48 +0,0 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vpd_sprite_shifter is
Port( clk : in std_logic;
x : in unsigned (7 downto 0);
spr_x : in unsigned (7 downto 0);
spr_d0: in std_logic_vector (7 downto 0);
spr_d1: in std_logic_vector (7 downto 0);
spr_d2: in std_logic_vector (7 downto 0);
spr_d3: in std_logic_vector (7 downto 0);
color : out std_logic_vector (3 downto 0);
active: out std_logic);
end vpd_sprite_shifter;
architecture Behavioral of vpd_sprite_shifter is
signal count : integer range 0 to 8;
signal shift0 : std_logic_vector (7 downto 0) := (others=>'0');
signal shift1 : std_logic_vector (7 downto 0) := (others=>'0');
signal shift2 : std_logic_vector (7 downto 0) := (others=>'0');
signal shift3 : std_logic_vector (7 downto 0) := (others=>'0');
begin
process (clk)
begin
if rising_edge(clk) then
if spr_x=x then
shift0 <= spr_d0;
shift1 <= spr_d1;
shift2 <= spr_d2;
shift3 <= spr_d3;
else
shift0 <= shift0(6 downto 0)&"0";
shift1 <= shift1(6 downto 0)&"0";
shift2 <= shift2(6 downto 0)&"0";
shift3 <= shift3(6 downto 0)&"0";
end if;
end if;
end process;
color <= shift3(7)&shift2(7)&shift1(7)&shift0(7);
active <= shift3(7) or shift2(7) or shift1(7) or shift0(7);
end Behavioral;

188
cores/sms/src/vdp_sprites.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vdp_sprites is
port (clk : in std_logic;
table_address : in STD_LOGIC_VECTOR (13 downto 8);
char_high_bit : in std_logic;
tall : in std_logic;
vram_A : out STD_LOGIC_VECTOR (13 downto 0);
vram_D : in STD_LOGIC_VECTOR (7 downto 0);
x : in unsigned (8 downto 0);
y : in unsigned (7 downto 0);
color : out STD_LOGIC_VECTOR (3 downto 0));
end vdp_sprites;
architecture Behavioral of vdp_sprites is
component vpd_sprite_shifter is
port( clk : in std_logic;
x : in unsigned (7 downto 0);
spr_x : in unsigned (7 downto 0);
spr_d0: in std_logic_vector (7 downto 0);
spr_d1: in std_logic_vector (7 downto 0);
spr_d2: in std_logic_vector (7 downto 0);
spr_d3: in std_logic_vector (7 downto 0);
color : out std_logic_vector (3 downto 0);
active: out std_logic);
end component;
constant WAITING: integer := 0;
constant COMPARE: integer := 1;
constant LOAD_N: integer := 2;
constant LOAD_X: integer := 3;
constant LOAD_0: integer := 4;
constant LOAD_1: integer := 5;
constant LOAD_2: integer := 6;
constant LOAD_3: integer := 7;
signal state: integer := WAITING;
signal count: integer range 0 to 7;
signal index: unsigned(5 downto 0);
signal data_address: std_logic_vector(13 downto 2);
type tenable is array (0 to 7) of boolean;
type tx is array (0 to 7) of unsigned(7 downto 0);
type tdata is array (0 to 7) of std_logic_vector(7 downto 0);
signal enable: tenable;
signal spr_x: tx;
signal spr_d0: tdata;
signal spr_d1: tdata;
signal spr_d2: tdata;
signal spr_d3: tdata;
type tcolor is array (0 to 7) of std_logic_vector(3 downto 0);
signal spr_color: tcolor;
signal active: std_logic_vector(7 downto 0);
begin
shifters:
for i in 0 to 7 generate
begin
shifter: vpd_sprite_shifter
port map(clk => clk,
x => x(7 downto 0),
spr_x => spr_x(i),
spr_d0=> spr_d0(i),
spr_d1=> spr_d1(i),
spr_d2=> spr_d2(i),
spr_d3=> spr_d3(i),
color => spr_color(i),
active=> active(i));
end generate;
with state select
vram_a <= table_address&"00"&std_logic_vector(index) when COMPARE,
table_address&"1"&std_logic_vector(index)&"1" when LOAD_N,
table_address&"1"&std_logic_vector(index)&"0" when LOAD_X,
data_address&"00" when LOAD_0,
data_address&"01" when LOAD_1,
data_address&"10" when LOAD_2,
data_address&"11" when LOAD_3,
(others=>'0') when others;
process (clk)
variable y9 : unsigned(8 downto 0);
variable d9 : unsigned(8 downto 0);
variable delta : unsigned(8 downto 0);
begin
if rising_edge(clk) then
if x=255 then
count <= 0;
enable <= (others=>false);
state <= COMPARE;
index <= (others=>'0');
else
y9 := "0"&y;
d9 := "0"&unsigned(vram_D);
if d9>=240 then
d9 := d9-256;
end if;
delta := y9-d9;
case state is
when COMPARE =>
if d9=208 then
state <= WAITING; -- stop
elsif 0<=delta and ((delta<8 and tall='0') or (delta<16 and tall='1')) then
enable(count) <= true;
data_address(5 downto 2) <= std_logic_vector(delta(3 downto 0));
state <= LOAD_N;
else
if index<63 then
index <= index+1;
else
state <= WAITING;
end if;
end if;
when LOAD_N =>
data_address(13) <= char_high_bit;
data_address(12 downto 6) <= vram_d(7 downto 1);
if tall='0' then
data_address(5) <= vram_d(0);
end if;
state <= LOAD_X;
when LOAD_X =>
spr_x(count) <= unsigned(vram_d);
state <= LOAD_0;
when LOAD_0 =>
spr_d0(count) <= vram_d;
state <= LOAD_1;
when LOAD_1 =>
spr_d1(count) <= vram_d;
state <= LOAD_2;
when LOAD_2 =>
spr_d2(count) <= vram_d;
state <= LOAD_3;
when LOAD_3 =>
spr_d3(count) <= vram_d;
if (count<7) then
state <= COMPARE;
index <= index+1;
count <= count+1;
else
state <= WAITING;
end if;
when others =>
end case;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if enable(0) and active(0)='1' then
color <= spr_color(0);
elsif enable(1) and active(1)='1' then
color <= spr_color(1);
elsif enable(2) and active(2)='1' then
color <= spr_color(2);
elsif enable(3) and active(3)='1' then
color <= spr_color(3);
elsif enable(4) and active(4)='1' then
color <= spr_color(4);
elsif enable(5) and active(5)='1' then
color <= spr_color(5);
elsif enable(6) and active(6)='1' then
color <= spr_color(6);
elsif enable(7) and active(7)='1' then
color <= spr_color(7);
else
color <= (others=>'0');
end if;
end if;
end process;
end Behavioral;

95
cores/sms/src/vga_video.vhd
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@@ -1,95 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:59:35 01/22/2012
-- Design Name:
-- Module Name: vdp_vga_timing - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_video is
port (
clk16: in std_logic;
pal: in std_logic;
x: out unsigned(8 downto 0);
y: out unsigned(7 downto 0);
color: in std_logic_vector(5 downto 0);
hsync: out std_logic;
vsync: out std_logic;
red: out std_logic_vector(1 downto 0);
green: out std_logic_vector(1 downto 0);
blue: out std_logic_vector(1 downto 0));
end vga_video;
architecture Behavioral of vga_video is
signal hcount: unsigned (8 downto 0) := (others=>'0');
signal vcount: unsigned (9 downto 0) := (others=>'0');
signal visible: boolean;
signal y9: unsigned (8 downto 0);
begin
process (clk16)
begin
if rising_edge(clk16) then
if (pal='0' and hcount=507) or (pal='1' and hcount=511) then
hcount <= (others => '0');
if (pal='0' and vcount=523) or (pal='1' and vcount=625) then
vcount <= (others=>'0');
else
vcount <= vcount + 1;
end if;
else
hcount <= hcount + 1;
end if;
end if;
end process;
-- y counter over 263 (NTSC) or 313 (PAL) lines
-- NTSC 256x192 00-DA, D5-FF
-- PAL 256x192 00-F2, BA-FF
x <= hcount-(91+75);
y9 <= (vcount(9 downto 1)-43) when pal='0' else (vcount(9 downto 1)-70);
y <= y9(7 downto 0);
hsync <= '0' when hcount<61 else '1';
vsync <= '0' when vcount<2 else '1';
visible <=
(vcount>=35 and vcount<35+480 and hcount>=91 and hcount<91+406) when pal='0' else
(vcount>=85 and vcount<85+480 and hcount>=95 and hcount<95+406);
process (clk16)
begin
if rising_edge(clk16) then
if visible then
red <= color(1 downto 0);
green <= color(3 downto 2);
blue <= color(5 downto 4);
else
red <= (others=>'0');
green <= (others=>'0');
blue <= (others=>'0');
end if;
end if;
end process;
end Behavioral;

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cores/sms/src/video.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity video is
Port (
clk8: in std_logic;
pal: in std_logic;
x: out unsigned(8 downto 0);
y: out unsigned(7 downto 0);
color: in std_logic_vector(5 downto 0);
hsync: out std_logic;
vsync: out std_logic;
red: out std_logic_vector(1 downto 0);
green: out std_logic_vector(1 downto 0);
blue: out std_logic_vector(1 downto 0));
end video;
architecture Behavioral of video is
component ntsc_video is
port (
clk8: in std_logic;
x: out unsigned(8 downto 0);
y: out unsigned(7 downto 0);
color: in std_logic_vector(5 downto 0);
hsync: out std_logic;
vsync: out std_logic;
red: out std_logic_vector(1 downto 0);
green: out std_logic_vector(1 downto 0);
blue: out std_logic_vector(1 downto 0));
end component;
component pal_video is
port (
clk8: in std_logic;
x: out unsigned(8 downto 0);
y: out unsigned(7 downto 0);
color: in std_logic_vector(5 downto 0);
hsync: out std_logic;
vsync: out std_logic;
red: out std_logic_vector(1 downto 0);
green: out std_logic_vector(1 downto 0);
blue: out std_logic_vector(1 downto 0));
end component;
signal ntsc_clk: std_logic;
signal ntsc_x: unsigned(8 downto 0);
signal ntsc_y: unsigned(7 downto 0);
signal ntsc_hsync: std_logic;
signal ntsc_vsync: std_logic;
signal ntsc_red: std_logic_vector(1 downto 0);
signal ntsc_green: std_logic_vector(1 downto 0);
signal ntsc_blue: std_logic_vector(1 downto 0);
signal pal_clk: std_logic;
signal pal_x: unsigned(8 downto 0);
signal pal_y: unsigned(7 downto 0);
signal pal_hsync: std_logic;
signal pal_vsync: std_logic;
signal pal_red: std_logic_vector(1 downto 0);
signal pal_green: std_logic_vector(1 downto 0);
signal pal_blue: std_logic_vector(1 downto 0);
begin
ntsc_clk <= '0' when pal='1' else clk8;
pal_clk <= clk8 when pal='1' else '0';
x <= pal_x when pal='1' else ntsc_x;
y <= pal_y when pal='1' else ntsc_y;
hsync <= pal_hsync when pal='1' else ntsc_hsync;
vsync <= pal_vsync when pal='1' else ntsc_vsync;
red <= pal_red when pal='1' else ntsc_red;
green <= pal_green when pal='1' else ntsc_green;
blue <= pal_blue when pal='1' else ntsc_blue;
ntsc_inst: ntsc_video
port map (
clk8 => ntsc_clk,
x => ntsc_x,
y => ntsc_y,
color => color,
hsync => ntsc_hsync,
vsync => ntsc_vsync,
red => ntsc_red,
green => ntsc_green,
blue => ntsc_blue
);
pal_inst: pal_video
port map (
clk8 => pal_clk,
x => pal_x,
y => pal_y,
color => color,
hsync => pal_hsync,
vsync => pal_vsync,
red => pal_red,
green => pal_green,
blue => pal_blue
);
end Behavioral;

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cores/sms/t80/T80.vhd
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351
cores/sms/t80/T80_ALU.vhd
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--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
OverFlow_v <= Carry_v xor Carry7_v;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

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cores/sms/t80/T80_MCode.vhd
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208
cores/sms/t80/T80_Pack.vhd
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--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

105
cores/sms/t80/T80_Reg.vhd
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@@ -1,105 +0,0 @@
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;

184
cores/sms/t80/T80se.vhd
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@@ -1,184 +0,0 @@
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80se is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80se;
architecture rtl of T80se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => Mode,
IOWait => IOWait)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

92
cores/zxgate/t80/trunk/rtl/vhdl/SSRAM.vhd
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@@ -1,92 +0,0 @@
--
-- Inferrable Synchronous SRAM for XST synthesis
--
-- Version : 0220
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
-- 0208 : Initial release
-- 0218 : Fixed data out at write
-- 0220 : Added support for XST
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity SSRAM is
generic(
AddrWidth : integer := 11;
DataWidth : integer := 8
);
port(
Clk : in std_logic;
CE_n : in std_logic;
WE_n : in std_logic;
A : in std_logic_vector(AddrWidth - 1 downto 0);
DIn : in std_logic_vector(DataWidth - 1 downto 0);
DOut : out std_logic_vector(DataWidth - 1 downto 0)
);
end SSRAM;
architecture behaviour of SSRAM is
type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1);
signal A_r : std_logic_vector(AddrWidth - 1 downto 0);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if (CE_n nor WE_n) = '1' then
RAM(to_integer(unsigned(A))) <= DIn;
end if;
A_r <= A;
end if;
end process;
DOut <= RAM(to_integer(unsigned(A_r)))
-- pragma translate_off
when not is_x(A_r) else (others => '-')
-- pragma translate_on
;
end;

1088
cores/zxgate/t80/trunk/rtl/vhdl/T80.vhd
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File diff suppressed because it is too large Load Diff

371
cores/zxgate/t80/trunk/rtl/vhdl/T80_ALU.vhd
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@@ -1,371 +0,0 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

2024
cores/zxgate/t80/trunk/rtl/vhdl/T80_MCode.vhd
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228
cores/zxgate/t80/trunk/rtl/vhdl/T80_Pack.vhd
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@@ -1,228 +0,0 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

114
cores/zxgate/t80/trunk/rtl/vhdl/T80_Reg.vhd
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@@ -1,114 +0,0 @@
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;

190
cores/zxgate/t80/trunk/rtl/vhdl/T80s.vhd
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@@ -1,190 +0,0 @@
--
-- Z80 compatible microprocessor core, synchronous top level
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0210 : Fixed read with wait
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80s is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80s;
architecture rtl of T80s is
signal CEN : std_logic;
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
u0 : T80
generic map(
Mode => Mode,
IOWait => IOWait)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end process;
end;

265
cores/zxgate/zx/ext/ps2me.vhd
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@@ -1,265 +0,0 @@
--
-- ZX81 PS2 to keyboard matrix encoder
-- Author : Daniel Wallner
-- http://www.beyondlogic.org/keyboard/keybrd.htm
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity PS2_MatrixEncoder is
port(
Clk : in std_logic;
Reset_n : in std_logic;
Tick1us : in std_logic;
PS2_Clk : in std_logic;
PS2_Data : in std_logic;
Key_Addr : in std_logic_vector(7 downto 0);
Key_Data : out std_logic_vector(4 downto 0)
);
end PS2_MatrixEncoder;
architecture rtl of PS2_MatrixEncoder is
signal PS2_Sample : std_logic;
signal PS2_Data_s : std_logic;
signal RX_Bit_Cnt : unsigned(3 downto 0);
signal RX_Byte : unsigned(2 downto 0);
signal RX_ShiftReg : std_logic_vector(7 downto 0);
signal RX_Release : std_logic;
signal RX_Received : std_logic;
signal LookUp : std_logic_vector(7 downto 0);
signal Matrix_Set : std_logic;
signal Matrix_Clear : std_logic;
signal Matrix_Wr_Addr : unsigned(7 downto 0);
type Matrix_Image is array (natural range <>) of std_logic_vector(4 downto 0);
signal Matrix : Matrix_Image(0 to 7);
begin
process (Clk, Reset_n)
variable PS2_Data_r : std_logic_vector(1 downto 0);
variable PS2_Clk_r : std_logic_vector(1 downto 0);
variable PS2_Clk_State : std_logic;
begin
if Reset_n = '0' then
PS2_Sample <= '0';
PS2_Data_s <= '0';
PS2_Data_r := "11";
PS2_Clk_r := "11";
PS2_Clk_State := '1';
elsif Clk'event and Clk = '1' then
if Tick1us = '1' then
PS2_Sample <= '0';
-- Deglitch
if PS2_Data_r = "00" then
PS2_Data_s <= '0';
end if;
if PS2_Data_r = "11" then
PS2_Data_s <= '1';
end if;
if PS2_Clk_r = "00" then
if PS2_Clk_State = '1' then
PS2_Sample <= '1';
end if;
PS2_Clk_State := '0';
end if;
if PS2_Clk_r = "11" then
PS2_Clk_State := '1';
end if;
-- Double synchronise
PS2_Data_r(1) := PS2_Data_r(0);
PS2_Clk_r(1) := PS2_Clk_r(0);
PS2_Data_r(0) := PS2_Data;
PS2_Clk_r(0) := PS2_Clk;
end if;
end if;
end process;
process (Clk, Reset_n)
variable Cnt : integer;
begin
if Reset_n = '0' then
RX_Bit_Cnt <= (others => '0');
RX_ShiftReg <= (others => '0');
RX_Received <= '0';
Cnt := 0;
elsif Clk'event and Clk = '1' then
RX_Received <= '0';
if Tick1us = '1' then
if PS2_Sample = '1' then
if RX_Bit_Cnt = "0000" then
if PS2_Data_s = '0' then -- Start bit
RX_Bit_Cnt <= RX_Bit_Cnt + 1;
end if;
elsif RX_Bit_Cnt = "1001" then -- Parity bit
RX_Bit_Cnt <= RX_Bit_Cnt + 1;
-- Ignoring parity
elsif RX_Bit_Cnt = "1010" then -- Stop bit
if PS2_Data_s = '1' then
RX_Received <= '1';
end if;
RX_Bit_Cnt <= "0000";
else
RX_Bit_Cnt <= RX_Bit_Cnt + 1;
RX_ShiftReg(6 downto 0) <= RX_ShiftReg(7 downto 1);
RX_ShiftReg(7) <= PS2_Data_s;
end if;
end if;
-- TimeOut
if PS2_Sample = '1' then
Cnt := 0;
elsif Cnt = 127 then
RX_Bit_Cnt <= "0000";
Cnt := 0;
else
Cnt := Cnt + 1;
end if;
end if;
end if;
end process;
process (Clk, Reset_n)
begin
if Reset_n = '0' then
RX_Byte <= (others => '0');
RX_Release <= '0';
Matrix_Set <= '0';
Matrix_Clear <= '0';
Matrix_Wr_Addr <= (others => '0');
elsif Clk'event and Clk = '1' then
Matrix_Set <= '0';
Matrix_Clear <= '0';
if RX_Received = '1' then
RX_Byte <= RX_Byte + 1;
if RX_ShiftReg = x"F0" then
RX_Release <= '1';
elsif RX_ShiftReg = x"E0" then
else
RX_Release <= '0';
-- Normal key press
if unsigned(LookUp) /= 0 and RX_Release = '0' then
Matrix_Wr_Addr <= unsigned(LookUp);
Matrix_Set <= '1';
end if;
-- Normal key release
if unsigned(LookUp) /= 0 and RX_Release = '1' then
Matrix_Wr_Addr <= unsigned(LookUp);
Matrix_Clear <= '1';
end if;
end if;
end if;
end if;
end process;
-- ZX81 keymap:
-- shift, z, x, c, v
-- a, s, d, f, g
-- q, w, e, r, t
-- 1, 2, 3, 4, 5
-- 0, 9, 8, 7, 6
-- p, o, i, u, y
-- return, l, k, j, h
-- space, ., m, n, b
process (RX_ShiftReg)
begin
case RX_ShiftReg is
when x"12" => LookUp <= "00000001"; -- shift
when x"59" => LookUp <= "00000001"; -- shift
when x"1a" => LookUp <= "00000010"; -- z
when x"22" => LookUp <= "00000100"; -- x
when x"21" => LookUp <= "00001000"; -- c
when x"2a" => LookUp <= "00010000"; -- v
when x"1c" => LookUp <= "00100001"; -- a
when x"1b" => LookUp <= "00100010"; -- s
when x"23" => LookUp <= "00100100"; -- d
when x"2b" => LookUp <= "00101000"; -- f
when x"34" => LookUp <= "00110000"; -- g
when x"15" => LookUp <= "01000001"; -- q
when x"1d" => LookUp <= "01000010"; -- w
when x"24" => LookUp <= "01000100"; -- e
when x"2d" => LookUp <= "01001000"; -- r
when x"2c" => LookUp <= "01010000"; -- t
when x"16" => LookUp <= "01100001"; -- 1
when x"69" => LookUp <= "01100001"; -- 1
when x"1e" => LookUp <= "01100010"; -- 2
when x"72" => LookUp <= "01100010"; -- 2
when x"26" => LookUp <= "01100100"; -- 3
when x"7a" => LookUp <= "01100100"; -- 3
when x"25" => LookUp <= "01101000"; -- 4
when x"6b" => LookUp <= "01101000"; -- 4
when x"2e" => LookUp <= "01110000"; -- 5
when x"73" => LookUp <= "01110000"; -- 5
when x"45" => LookUp <= "10000001"; -- 0
when x"70" => LookUp <= "10000001"; -- 0
when x"46" => LookUp <= "10000010"; -- 9
when x"7d" => LookUp <= "10000010"; -- 9
when x"3e" => LookUp <= "10000100"; -- 8
when x"75" => LookUp <= "10000100"; -- 8
when x"3d" => LookUp <= "10001000"; -- 7
when x"6c" => LookUp <= "10001000"; -- 7
when x"36" => LookUp <= "10010000"; -- 6
when x"74" => LookUp <= "10010000"; -- 6
when x"4d" => LookUp <= "10100001"; -- p
when x"44" => LookUp <= "10100010"; -- o
when x"43" => LookUp <= "10100100"; -- i
when x"3c" => LookUp <= "10101000"; -- u
when x"35" => LookUp <= "10110000"; -- y
when x"5a" => LookUp <= "11000001"; -- return
when x"4b" => LookUp <= "11000010"; -- l
when x"42" => LookUp <= "11000100"; -- k
when x"3b" => LookUp <= "11001000"; -- j
when x"33" => LookUp <= "11010000"; -- h
when x"29" => LookUp <= "11100001"; -- Space
when x"49" => LookUp <= "11100010"; -- .
when x"3a" => LookUp <= "11100100"; -- m
when x"31" => LookUp <= "11101000"; -- n
when x"32" => LookUp <= "11110000"; -- b
when others => LookUp <= "00000000";
end case;
end process;
process (Clk, Reset_n)
begin
if Reset_n = '0' then
Matrix <= (others => (others => '0'));
elsif Clk'event and Clk = '1' then
if RX_ShiftReg = x"aa" and RX_Received = '1' then
Matrix <= (others => (others => '0'));
end if;
if Matrix_Set = '1' then
Matrix(to_integer(Matrix_Wr_Addr(7 downto 5))) <=
Matrix(to_integer(Matrix_Wr_Addr(7 downto 5))) or
std_logic_vector(Matrix_Wr_Addr(4 downto 0));
end if;
if Matrix_Clear = '1' then
Matrix(to_integer(Matrix_Wr_Addr(7 downto 5))) <=
Matrix(to_integer(Matrix_Wr_Addr(7 downto 5))) and
std_logic_vector(not Matrix_Wr_Addr(4 downto 0));
end if;
end if;
end process;
g_out1 : for i in 0 to 4 generate
Key_Data(i) <= not ((Matrix(0)(i) and not Key_Addr(0)) or
(Matrix(1)(i) and not Key_Addr(1)) or
(Matrix(2)(i) and not Key_Addr(2)) or
(Matrix(3)(i) and not Key_Addr(3)) or
(Matrix(4)(i) and not Key_Addr(4)) or
(Matrix(5)(i) and not Key_Addr(5)) or
(Matrix(6)(i) and not Key_Addr(6)) or
(Matrix(7)(i) and not Key_Addr(7)));
end generate;
end;

5
cores/zxgate/zx/zx01/clock.qip
View File

@@ -1,5 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clock.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clock_bb.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clock.ppf"]

320
cores/zxgate/zx/zx01/clock.v
View File

@@ -1,320 +0,0 @@
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clock.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clock (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [4:0] sub_wire1;
wire [0:0] sub_wire5 = 1'h0;
wire locked = sub_wire0;
wire [0:0] sub_wire2 = sub_wire1[0:0];
wire c0 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire4),
.locked (sub_wire0),
.clk (sub_wire1),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 27,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 13,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clock",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "18"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "13.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "85"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "13.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "amigaclk.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "13"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

122
cores/zxgate/zx/zx01/data_io.v
View File

@@ -1,122 +0,0 @@
//
// data_io.v
//
// io controller writable ram for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module data_io (
// io controller spi interface
input sck,
input ss,
input sdi,
output downloading, // signal indicating an active download
output [15:0] size, // number of bytes in input buffer
// cpu ram interface
input clk,
input we,
input [13:0] a,
input [8:0] din,
output [8:0] dout
);
parameter START_ADDR = 16'h0000;
assign size = addr;
// *********************************************************************************
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg [6:0] sbuf;
reg [7:0] cmd /* synthesis noprune */;
reg [7:0] data /* synthesis noprune */;
reg [4:0] cnt /* synthesis noprune */;
reg [15:0] addr /* synthesis noprune */;
reg rclk /* synthesis noprune */;
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
assign downloading = downloading_reg;
reg downloading_reg = 1'b0;
// data_io has its own SPI interface to the io controller
always@(posedge sck, posedge ss) begin
if(ss == 1'b1)
cnt <= 5'd0;
else begin
rclk <= 1'b0;
// don't shift in last bit. It is evaluated directly
// when writing to ram
if(cnt != 15)
sbuf <= { sbuf[5:0], sdi};
// increase target address after write
if(rclk)
addr <= addr + 16'd1;
// count 0-7 8-15 8-15 ...
if(cnt < 15) cnt <= cnt + 4'd1;
else cnt <= 4'd8;
// finished command byte
if(cnt == 7)
cmd <= {sbuf, sdi};
// prepare/end transmission
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(sdi) begin
addr <= START_ADDR;
downloading_reg <= 1'b1;
end else
downloading_reg <= 1'b0;
end
// command 0x54: UIO_FILE_TX
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
data <= {sbuf, sdi};
rclk <= 1'b1;
end
end
end
// include the embedded dual port ram
data_io_ram data_io_ram (
// wire up cpu port
.address_a ( a ),
.clock_a ( clk ),
.data_a ( din ),
.wren_a ( we ),
.q_a ( dout ),
// io controller port
.address_b ( addr[13:0] ),
.clock_b ( rclk ),
.data_b ( {sbuf, sdi} ),
.wren_b ( (cmd == UIO_FILE_TX_DAT) && !ss )
);
endmodule

244
cores/zxgate/zx/zx01/data_io_ram.v
View File

@@ -1,244 +0,0 @@
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: data_io_ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module data_io_ram (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [13:0] address_a;
input [13:0] address_b;
input clock_a;
input clock_b;
input [7:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
altsyncram altsyncram_component (
.clock0 (clock_a),
.wren_a (wren_a),
.address_b (address_b),
.clock1 (clock_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16384,
altsyncram_component.numwords_b = 16384,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 14,
altsyncram_component.widthad_b = 14,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 14 0 INPUT NODEFVAL "address_a[13..0]"
// Retrieval info: USED_PORT: address_b 0 0 14 0 INPUT NODEFVAL "address_b[13..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 14 0 address_a 0 0 14 0
// Retrieval info: CONNECT: @address_b 0 0 14 0 address_b 0 0 14 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL data_io_ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL data_io_ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL data_io_ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL data_io_ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL data_io_ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL data_io_ram_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

182
cores/zxgate/zx/zx01/osd.v
View File

@@ -1,182 +0,0 @@
// A simple OSD implementation. Can be hooked up between a cores
// VGA output and the physical VGA pins
module osd (
// OSDs pixel clock, should be synchronous to cores pixel clock to
// avoid jitter.
input pclk,
// SPI interface
input sck,
input ss,
input sdi,
// VGA signals coming from core
input [5:0] red_in,
input [5:0] green_in,
input [5:0] blue_in,
input hs_in,
input vs_in,
// VGA signals going to video connector
output [5:0] red_out,
output [5:0] green_out,
output [5:0] blue_out,
output hs_out,
output vs_out
);
parameter OSD_X_OFFSET = 10'd0;
parameter OSD_Y_OFFSET = 10'd0;
parameter OSD_COLOR = 3'd0;
localparam OSD_WIDTH = 10'd256;
localparam OSD_HEIGHT = 10'd128;
// *********************************************************************************
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg [7:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [10:0] bcnt;
reg osd_enable;
reg [7:0] osd_buffer [2047:0]; // the OSD buffer itself
// the OSD has its own SPI interface to the io controller
always@(posedge sck, posedge ss) begin
if(ss == 1'b1) begin
cnt <= 5'd0;
bcnt <= 11'd0;
end else begin
sbuf <= { sbuf[6:0], sdi};
// 0:7 is command, rest payload
if(cnt < 15)
cnt <= cnt + 4'd1;
else
cnt <= 4'd8;
if(cnt == 7) begin
cmd <= {sbuf[6:0], sdi};
// lower three command bits are line address
bcnt <= { sbuf[1:0], sdi, 8'h00};
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(sbuf[6:3] == 4'b0100)
osd_enable <= sdi;
end
// command 0x20: OSDCMDWRITE
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
osd_buffer[bcnt] <= {sbuf[6:0], sdi};
bcnt <= bcnt + 11'd1;
end
end
end
// *********************************************************************************
// video timing and sync polarity anaylsis
// *********************************************************************************
// horizontal counter
reg [9:0] h_cnt;
reg hsD, hsD2;
reg [9:0] hs_low, hs_high;
wire hs_pol = hs_high < hs_low;
wire [9:0] h_dsp_width = hs_pol?hs_low:hs_high;
wire [9:0] h_dsp_ctr = { 1'b0, h_dsp_width[9:1] };
always @(posedge pclk) begin
// bring hsync into local clock domain
hsD <= hs_in;
hsD2 <= hsD;
// falling edge of hs_in
if(!hsD && hsD2) begin
h_cnt <= 10'd0;
hs_high <= h_cnt;
end
// rising edge of hs_in
else if(hsD && !hsD2) begin
h_cnt <= 10'd0;
hs_low <= h_cnt;
end
else
h_cnt <= h_cnt + 10'd1;
end
// vertical counter
reg [9:0] v_cnt;
reg vsD, vsD2;
reg [9:0] vs_low, vs_high;
wire vs_pol = vs_high < vs_low;
wire [9:0] v_dsp_width = vs_pol?vs_low:vs_high;
wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_width[9:1] };
always @(posedge hs_in) begin
// bring vsync into local clock domain
vsD <= vs_in;
vsD2 <= vsD;
// falling edge of vs_in
if(!vsD && vsD2) begin
v_cnt <= 10'd0;
vs_high <= v_cnt;
end
// rising edge of vs_in
else if(vsD && !vsD2) begin
v_cnt <= 10'd0;
vs_low <= v_cnt;
end
else
v_cnt <= v_cnt + 10'd1;
end
// area in which OSD is being displayed
wire [9:0] h_osd_start = h_dsp_ctr + OSD_X_OFFSET - (OSD_WIDTH >> 1);
wire [9:0] h_osd_end = h_dsp_ctr + OSD_X_OFFSET + (OSD_WIDTH >> 1) - 1;
wire [9:0] v_osd_start = v_dsp_ctr + OSD_Y_OFFSET - (OSD_HEIGHT >> 1);
wire [9:0] v_osd_end = v_dsp_ctr + OSD_Y_OFFSET + (OSD_HEIGHT >> 1) - 1;
reg h_osd_active, v_osd_active;
always @(posedge pclk) begin
if(hs_in != hs_pol) begin
if(h_cnt == h_osd_start) h_osd_active <= 1'b1;
if(h_cnt == h_osd_end) h_osd_active <= 1'b0;
end
if(vs_in != vs_pol) begin
if(v_cnt == v_osd_start) v_osd_active <= 1'b1;
if(v_cnt == v_osd_end) v_osd_active <= 1'b0;
end
end
wire osd_de = osd_enable && h_osd_active && v_osd_active;
wire [7:0] osd_hcnt = h_cnt - h_osd_start + 7'd1; // one pixel offset for osd_byte register
wire [6:0] osd_vcnt = v_cnt - v_osd_start;
wire osd_pixel = osd_byte[osd_vcnt[3:1]];
reg [7:0] osd_byte;
always @(posedge pclk)
osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt}];
wire [2:0] osd_color = OSD_COLOR;
assign red_out = !osd_de?red_in: {osd_pixel, osd_pixel, osd_color[2], red_in[5:3] };
assign green_out = !osd_de?green_in:{osd_pixel, osd_pixel, osd_color[1], green_in[5:3]};
assign blue_out = !osd_de?blue_in: {osd_pixel, osd_pixel, osd_color[0], blue_in[5:3] };
assign hs_out = hs_in;
assign vs_out = vs_in;
endmodule

23
cores/zxgate/zx/zx01/rom81.cmp
View File

@@ -1,23 +0,0 @@
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component rom81
PORT
(
address : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;

4
cores/zxgate/zx/zx01/rom81.qip
View File

@@ -1,4 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "rom81.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "rom81.cmp"]

143
cores/zxgate/zx/zx01/rom81.vhd
View File

@@ -1,143 +0,0 @@
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: rom81.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY rom81 IS
PORT
(
address : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END rom81;
ARCHITECTURE SYN OF rom81 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "zx81rom.hex",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 8192,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 13,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "zx81rom.hex"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "zx81rom.hex"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom81.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom81.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom81.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom81.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom81_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

212
cores/zxgate/zx/zx01/tape.v
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@@ -1,212 +0,0 @@
//
// tape.v
//
// ZX81 tape implementation for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module tape(
input sck,
input ss,
input sdi,
input clk, // 500kHz
input play, // "press play on tape"
output reg tape_out
);
// create clock to be used for signaltap
reg [7:0] tape_clk /* synthesis noprune */;
always @(posedge clk)
tape_clk <= tape_clk + 8'd1;
// tape bit timing
// 0 bit = /\/\/\/\_________ (4* 150us H + 150us L + 1300us L)
// 1 bit = /\/\/\/\/\/\/\/\/\_____________
// 0 = idle, 1 = 1300us low, 2/4/6/../18 = 150us high, 3/5/7/../19 = 150us L
reg [4:0] pulse_state;
// 150us = 75 cycles @ 500kHz
// 1300us = 650 cycles @ 500kHz
reg [9:0] pulse_cnt; // 10 bit = 1024 max range
reg bit_done;
// generate bit timing
always @(posedge clk) begin
bit_done <= 1'b0;
if(pulse_cnt == 0) begin
// end of idle state, start new bit
if(pulse_state == 0) begin
if(bit_start) begin
tape_out <= 1'b1;
pulse_state <= bit?5'd19:5'd9;
pulse_cnt <= 10'd74;
end
end
// end of 1300us seperator phase
else if(pulse_state == 1) begin
tape_out <= 1'b0;
pulse_state <= 5'd0;
pulse_cnt <= 10'd0;
bit_done <= 1'b1;
end
// end of last high phase
else if(pulse_state == 2) begin
tape_out <= 1'b0;
pulse_state <= 5'd1;
pulse_cnt <= 10'd649;
end
// end of normal pulse hi/lo phase
else if(pulse_state > 2) begin
// tape level is 1 when coming from state 4,6,8,...
tape_out <= !pulse_state[0];
pulse_state <= pulse_state - 5'd1;
pulse_cnt <= 10'd74;
end
end else
pulse_cnt <= pulse_cnt - 10'd1;
end
// bring play signal into local clock domain and
// generate start signal from it
reg start;
reg playD, playD2;
always @(posedge clk) begin
start <= 1'b0;
playD <= play;
playD2 <= playD;
if(playD && !playD2)
start <= 1'b1;
end
// byte transmitter
wire bit = byte[bit_cnt];
// reg [7:0] byte = 8'h55 /* synthesis noprune */;
reg [2:0] bit_cnt;
reg byte_tx_running = 1'b0;
reg bit_in_progress;
reg bit_start;
reg byte_done;
always @(posedge clk) begin
bit_start <= 1'b0;
byte_done <= 1'b0;
// start signal starts a new byte transmission
if(!byte_tx_running) begin
if(byte_start) begin
byte_tx_running <= 1'b1;
bit_in_progress <= 1'b0;
bit_cnt <= 3'd7;
end
end else begin
// byte transmission in progress
if(!bit_in_progress) begin
// start new bit
bit_start <= 1'b1;
bit_in_progress <= 1'b1;
end else begin
// wait for bit transmission to finish
if(bit_done) begin
bit_in_progress <= 1'b0;
if(bit_cnt != 0)
bit_cnt <= bit_cnt - 3'd1;
else begin
byte_tx_running <= 1'b0;
byte_done <= 1'b1;
end
end
end
end
end
// byte tx engine
reg [15:0] byte_count;
// 0=idle, 1=filename, 2=file
reg [1:0] byte_state = 2'd0;
reg byte_start;
always @(posedge clk) begin
byte_start <= 1'b0;
if(byte_state == 0) begin
// start transmission if user presses "play". don't do anything if
// there's no tape data in the buffer
if(start && (file_size != 0)) begin
byte_state <= 2'd1;
// transmit the "file name"
byte_start <= 1'b1;
end
end else if(byte_state == 1) begin
if(byte_done) begin
byte_state <= 2'd2;
byte_start <= 1'b1;
byte_count <= 16'h0000;
end
end else if(byte_state == 2) begin
if(byte_done) begin
if(byte_count != file_size - 16'd1) begin
byte_count <= byte_count + 16'd1;
byte_start <= 1'b1;
end else
byte_state <= 2'd0;
end
end
end
wire [7:0] filename = { 1'b1, 7'h3f}; // 'Z' with end flag
wire [7:0] byte = (byte_state == 1)?filename:ram_data_out;
wire [7:0] ram_data_out;
wire [15:0] file_size;
// include the io controller connected ram
data_io data_io (
.sck ( sck ),
.ss ( ss ),
.sdi ( sdi ),
.downloading ( ),
.size ( file_size ),
// ram interface
.clk ( clk ),
.we ( 1'b0 ),
.a ( byte_count[13:0] ),
.din ( 8'h00 ),
.dout ( ram_data_out )
);
endmodule

196
cores/zxgate/zx/zx01/user_io.v
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@@ -1,196 +0,0 @@
//
// user_io.v
//
// user_io for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// parameter STRLEN and the actual length of conf_str have to match
module user_io #(parameter STRLEN=0) (
input [(8*STRLEN)-1:0] conf_str,
input SPI_CLK,
input SPI_SS_IO,
output reg SPI_MISO,
input SPI_MOSI,
output [5:0] JOY0,
output [5:0] JOY1,
output [1:0] BUTTONS,
output [1:0] SWITCHES,
output scandoubler_disable,
output reg [7:0] status,
input clk,
output ps2_clk,
output reg ps2_data
);
// config string, it is assumed that any core returning a string here
// also supports the OSD
// 0123456789abcdef
//wire [127:0] name = "ZX01;P; ";
reg [6:0] sbuf;
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [5:0] byte_cnt; // counts bytes
reg [5:0] joystick0;
reg [5:0] joystick1;
reg [7:0] but_sw;
assign JOY0 = joystick0;
assign JOY1 = joystick1;
assign BUTTONS = but_sw[1:0];
assign SWITCHES = but_sw[3:2];
assign scandoubler_disable = but_sw[4];
// this variant of user_io is for 8 bit cores (type == a4) only
wire [7:0] core_type = 8'ha4;
// drive MISO only when transmitting core id
always@(negedge SPI_CLK or posedge SPI_SS_IO) begin
if(SPI_SS_IO == 1) begin
SPI_MISO <= 1'bZ;
end else begin
// first byte returned is always core type, further bytes are
// command dependent
if(byte_cnt == 0) begin
SPI_MISO <= core_type[~bit_cnt];
end else begin
// reading config string
if(cmd == 8'h14) begin
// returning a byte from string
if(byte_cnt < STRLEN + 1)
SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
else
SPI_MISO <= 1'b0;
end
end
end
end
// 8 byte fifo to store ps2 bytes
localparam PS2_FIFO_BITS = 3;
reg [7:0] ps2_fifo [(2**PS2_FIFO_BITS)-1:0];
reg [PS2_FIFO_BITS-1:0] ps2_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_tx_state;
reg [7:0] ps2_tx_byte;
reg ps2_parity;
assign ps2_clk = clk || (ps2_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_r_inc;
always@(posedge clk) begin
ps2_r_inc <= 1'b0;
if(ps2_r_inc)
ps2_rptr <= ps2_rptr + 1;
// transmitter is idle?
if(ps2_tx_state == 0) begin
// data in fifo present?
if(ps2_wptr != ps2_rptr) begin
// load tx register from fifo
ps2_tx_byte <= ps2_fifo[ps2_rptr];
ps2_r_inc <= 1'b1;
// reset parity
ps2_parity <= 1'b1;
// start transmitter
ps2_tx_state <= 4'd1;
// put start bit on data line
ps2_data <= 1'b0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_tx_state >= 1)&&(ps2_tx_state < 9)) begin
ps2_data <= ps2_tx_byte[0]; // data bits
ps2_tx_byte[6:0] <= ps2_tx_byte[7:1]; // shift down
if(ps2_tx_byte[0])
ps2_parity <= !ps2_parity;
end
// transmission of parity
if(ps2_tx_state == 9)
ps2_data <= ps2_parity;
// transmission of stop bit
if(ps2_tx_state == 10)
ps2_data <= 1'b1; // stop bit is 1
// advance state machine
if(ps2_tx_state < 11)
ps2_tx_state <= ps2_tx_state + 4'd1;
else
ps2_tx_state <= 4'd0;
end
end
// SPI receiver
always@(posedge SPI_CLK or posedge SPI_SS_IO) begin
if(SPI_SS_IO == 1) begin
bit_cnt <= 3'd0;
byte_cnt <= 5'd0;
end else begin
sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
bit_cnt <= bit_cnt + 3'd1;
if(bit_cnt == 7) byte_cnt <= byte_cnt + 5'd1;
// finished reading command byte
if(bit_cnt == 7) begin
if(byte_cnt == 0)
cmd <= { sbuf, SPI_MOSI};
if(byte_cnt != 0) begin
if(cmd == 8'h01)
but_sw <= { sbuf, SPI_MOSI };
if(cmd == 8'h02)
joystick0 <= { sbuf[4:0], SPI_MOSI };
if(cmd == 8'h03)
joystick1 <= { sbuf[4:0], SPI_MOSI };
if(cmd == 8'h05) begin
// store incoming keyboard bytes in
ps2_fifo[ps2_wptr] <= { sbuf, SPI_MOSI };
ps2_wptr <= ps2_wptr + 1;
end
if(cmd == 8'h15) begin
status <= { sbuf[4:0], SPI_MOSI };
end
end
end
end
end
endmodule

30
cores/zxgate/zx/zx01/zx01.qpf
View File

@@ -1,30 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 21:40:24 May 17, 2014
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "21:40:24 May 17, 2014"
# Revisions
PROJECT_REVISION = "zx01"

318
cores/zxgate/zx/zx01/zx01.qsf
View File

@@ -1,318 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 21:40:24 May 17, 2014
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# zx01_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name TOP_LEVEL_ENTITY zx01_mist
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:40:24 MAY 17, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_22 -to CLOCK_50[0]
set_location_assignment PIN_23 -to CLOCK_50[1]
set_location_assignment PIN_128 -to CLOCK_32[0]
set_location_assignment PIN_129 -to CLOCK_32[1]
set_location_assignment PIN_54 -to CLOCK_27[0]
set_location_assignment PIN_55 -to CLOCK_27[1]
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_46 -to UART_TX
set_location_assignment PIN_31 -to UART_RX
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_90 -to SPI_SS4
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_8
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_128
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SDRAM_CLK
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SPI_SCK
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
set_global_assignment -name VERILOG_FILE tape.v
set_global_assignment -name VERILOG_FILE data_io_ram.v
set_global_assignment -name VERILOG_FILE data_io.v
set_global_assignment -name VERILOG_FILE osd.v
set_global_assignment -name VERILOG_FILE user_io.v
set_global_assignment -name QIP_FILE clock.qip
set_global_assignment -name VHDL_FILE ../ext/ps2me.vhd
set_global_assignment -name VHDL_FILE ../zx97/res_clk.vhd
set_global_assignment -name VHDL_FILE ../zx97/modes97.vhd
set_global_assignment -name VHDL_FILE ../zx97/lcd97.vhd
set_global_assignment -name VHDL_FILE ../zx97/io81.vhd
set_global_assignment -name VHDL_FILE ../zx97/busses.vhd
set_global_assignment -name VHDL_FILE ../zx97/video81.vhd
set_global_assignment -name VHDL_FILE ../zx97/top.vhd
set_global_assignment -name VHDL_FILE ../../t80/trunk/rtl/vhdl/T80_MCode.vhd
set_global_assignment -name VHDL_FILE ../../t80/trunk/rtl/vhdl/T80s.vhd
set_global_assignment -name VHDL_FILE ../../t80/trunk/rtl/vhdl/T80_Reg.vhd
set_global_assignment -name VHDL_FILE ../../t80/trunk/rtl/vhdl/T80_ALU.vhd
set_global_assignment -name VHDL_FILE ../../t80/trunk/rtl/vhdl/T80_Pack.vhd
set_global_assignment -name VHDL_FILE ../../t80/trunk/rtl/vhdl/T80.vhd
set_global_assignment -name VHDL_FILE ../../t80/trunk/rtl/vhdl/SSRAM.vhd
set_global_assignment -name VHDL_FILE zx01.vhd
set_global_assignment -name VERILOG_FILE zx01_mist.v
set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_global_assignment -name QIP_FILE rom81.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

265
cores/zxgate/zx/zx01/zx01.vhd
View File

@@ -1,265 +0,0 @@
----------------------------------------------------------
-- zx01.vhd
-- ZX01 top level
-- ==============
--
-- 12/15/01 Daniel Wallner : Rewrite of Bodo Wenzels zx97 to SOC
-- 02/23/02 Daniel Wallner : Changed to the synchronous t80s
-- 03/04/02 Daniel Wallner : Connected INT_n, synchronized reset and added tape_out
-- 08/14/02 Daniel Wallner : Changed for xilinx XST
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- the pads ----------------------------------------------
entity zx01 is
port (n_reset: in std_ulogic;
clock: in std_ulogic;
kbd_clk: in std_ulogic;
kbd_data: in std_ulogic;
v_inv: in std_ulogic;
usa_uk: in std_ulogic;
mem16k: in std_ulogic;
video: out std_ulogic;
tape_in: in std_ulogic;
tape_out: out std_ulogic;
d_lcd: out std_ulogic_vector(3 downto 0);
s: out std_ulogic;
cp1: out std_ulogic;
cp2: out std_ulogic);
end;
-- the top level ------------------------------
architecture rtl of zx01 is
component PS2_MatrixEncoder
port (Clk: in std_logic;
Reset_n: in std_logic;
Tick1us: in std_logic;
PS2_Clk: in std_logic;
PS2_Data: in std_logic;
Key_Addr: in std_logic_vector(7 downto 0);
Key_Data: out std_logic_vector(4 downto 0));
end component;
component T80s
generic(
Mode : integer := 0);
port (RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0));
end component;
component SSRAM
generic(
AddrWidth: integer := 16;
DataWidth: integer := 8);
port (Clk: in std_logic;
CE_n: in std_logic;
WE_n: in std_logic;
A: in std_logic_vector(AddrWidth - 1 downto 0);
DIn: in std_logic_vector(DataWidth - 1 downto 0);
DOut: out std_logic_vector(DataWidth - 1 downto 0));
end component;
component ROM81
port (clock: in std_logic;
address: in std_logic_vector(12 downto 0);
q: out std_logic_vector(7 downto 0));
end component;
component top
generic (synchronous: boolean := false);
port (clock: in std_ulogic;
clock_2: out std_ulogic;
phi: in std_ulogic;
n_reset: out std_ulogic;
n_modes: out std_ulogic;
a_mem_h: out std_ulogic_vector(14 downto 13);
a_mem_l: out std_ulogic_vector(8 downto 0);
d_mem_i: in std_ulogic_vector(7 downto 0);
a_cpu: in std_ulogic_vector(15 downto 0);
d_cpu_i: in std_ulogic_vector(7 downto 0);
d_cpu_o: out std_ulogic_vector(7 downto 0);
oe_cpu: out boolean;
oe_mem: out boolean;
n_m1: in std_ulogic;
n_mreq: in std_ulogic;
n_iorq: in std_ulogic;
n_wr: in std_ulogic;
n_rd: in std_ulogic;
n_rfsh: in std_ulogic;
n_nmi: out std_ulogic;
n_halt: in std_ulogic;
n_wait: out std_ulogic;
n_romcs: out std_ulogic;
n_ramcs: out std_ulogic;
kbd_col: in std_ulogic_vector(4 downto 0);
usa_uk: in std_ulogic;
video: out std_ulogic;
n_sync: out std_ulogic;
tape_in: in std_ulogic;
d_lcd: out std_ulogic_vector(3 downto 0);
s: out std_ulogic;
cp1: out std_ulogic;
cp2: out std_ulogic);
end component;
signal a_mem_h: std_ulogic_vector(14 downto 13);
signal a_mem_l: std_ulogic_vector(8 downto 0);
signal a_mem: std_logic_vector(14 downto 0);
signal a_ram: std_logic_vector(13 downto 0);
signal d_ram: std_logic_vector(7 downto 0);
signal d_rom: std_logic_vector(7 downto 0);
signal n_romcs: std_ulogic;
signal n_ramcs: std_ulogic;
signal a_cpu: std_logic_vector(15 downto 0);
signal n_m1: std_ulogic;
signal n_mreq: std_ulogic;
signal n_iorq: std_ulogic;
signal n_wr: std_ulogic;
signal n_rd: std_ulogic;
signal n_rfsh: std_ulogic;
signal n_nmi: std_ulogic;
signal n_halt: std_ulogic;
signal n_wait: std_ulogic;
signal clock_2: std_ulogic;
signal i_phi: std_ulogic;
signal i_n_modes: std_ulogic;
signal d_mem_i: std_ulogic_vector(7 downto 0);
signal d_cpu_i: std_logic_vector(7 downto 0);
signal d_cpu_o: std_ulogic_vector(7 downto 0);
signal Tick1us: std_logic;
signal kbd_col: std_logic_vector(4 downto 0);
signal kbd_mode: std_logic_vector(4 downto 0);
signal i_kbd_col: std_logic_vector(4 downto 0);
signal i_video: std_ulogic;
signal i_n_sync: std_ulogic;
signal i_n_reset: std_ulogic;
signal s_n_reset: std_ulogic;
begin
process (n_reset, i_phi)
begin
if n_reset = '0' then
s_n_reset <= '0';
elsif i_phi'event and i_phi = '1' then
s_n_reset <= '1';
end if;
end process;
process (s_n_reset, i_phi)
variable cnt : unsigned(1 downto 0);
begin
if s_n_reset = '0' then
cnt := "00";
Tick1us <= '0';
elsif i_phi'event and i_phi = '1' then
if cnt = "00" then
cnt := "10";
Tick1us <= '1';
else
cnt := cnt - 1;
Tick1us <= '0';
end if;
end if;
end process;
c_PS2_MatrixEncoder: PS2_MatrixEncoder
port map (Clk => i_phi,
Reset_n => i_n_reset,
Tick1us => Tick1us,
PS2_Clk => kbd_clk,
PS2_Data => kbd_data,
Key_Addr => a_cpu(15 downto 8),
Key_Data => kbd_col);
i_kbd_col <= kbd_mode when i_n_modes = '0' else kbd_col;
kbd_mode(3 downto 2) <= "00"; -- PAGE
kbd_mode(4) <= v_inv;
kbd_mode(1 downto 0) <= "00"; -- RAM
c_Z80: T80s
generic map (Mode => 0)
port map (M1_n => n_m1,
MREQ_n => n_mreq,
IORQ_n => n_iorq,
RD_n => n_rd,
WR_n => n_wr,
RFSH_n => n_rfsh,
HALT_n => n_halt,
WAIT_n => n_wait,
INT_n => a_cpu(6),
NMI_n => n_nmi,
RESET_n => s_n_reset,
BUSRQ_n => '1',
BUSAK_n => open,
CLK_n => i_phi,
A => a_cpu,
DI => std_logic_vector(d_cpu_o),
DO => d_cpu_i);
c_SSRAM: SSRAM
generic map (AddrWidth => 14)
port map (Clk => i_phi,
CE_n => n_ramcs,
WE_n => n_wr,
A => a_ram,
DIn => d_cpu_i,
DOut => d_ram);
a_ram <= a_mem(13 downto 0) when mem16k = '1' else "0000" & a_mem(9 downto 0);
c_ROM81: ROM81
port map (clock => i_phi,
address => a_mem(12 downto 0),
q => d_rom);
c_top: top
generic map (true)
port map (clock,clock_2,i_phi,
i_n_reset,i_n_modes,
a_mem_h,a_mem_l,d_mem_i,
std_ulogic_vector(a_cpu),std_ulogic_vector(d_cpu_i),d_cpu_o,
open,open,
n_m1,n_mreq,n_iorq,n_wr,n_rd,n_rfsh,
n_nmi,n_halt,n_wait,n_romcs,n_ramcs,
std_ulogic_vector(i_kbd_col),usa_uk,
i_video,i_n_sync,tape_in,
d_lcd,s,cp1,cp2);
i_phi <= clock_2;
a_mem(14 downto 13) <= std_logic_vector(a_mem_h);
a_mem(12 downto 9) <= a_cpu(12 downto 9);
a_mem(8 downto 0) <= std_logic_vector(a_mem_l);
d_mem_i <= std_ulogic_vector(d_rom) when n_ramcs = '1'
else std_ulogic_vector(d_ram);
tape_out <= i_n_sync;
video <= i_video;
-- video <= '0' when i_n_sync='0'
-- else 'Z' when i_video='0'
-- else '1';
end;
-- end ---------------------------------------------------

369
cores/zxgate/zx/zx01/zx01_mist.v
View File

@@ -1,369 +0,0 @@
//
// zx01_mist.v
//
// zx01/zx81 toplevel for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module zx01_mist (
// clock inputsxque
input wire [ 2-1:0] CLOCK_27, // 27 MHz
// LED outputs
output wire LED, // LED Yellow
// UART
output wire UART_TX, // UART Transmitter (MIDI out)
input wire UART_RX, // UART Receiver (MIDI in)
// VGA
output wire VGA_HS, // VGA H_SYNC
output wire VGA_VS, // VGA V_SYNC
output wire [ 6-1:0] VGA_R, // VGA Red[5:0]
output wire [ 6-1:0] VGA_G, // VGA Green[5:0]
output wire [ 6-1:0] VGA_B, // VGA Blue[5:0]
// SDRAM
inout wire [ 16-1:0] SDRAM_DQ, // SDRAM Data bus 16 Bits
output wire [ 13-1:0] SDRAM_A, // SDRAM Address bus 13 Bits
output wire SDRAM_DQML, // SDRAM Low-byte Data Mask
output wire SDRAM_DQMH, // SDRAM High-byte Data Mask
output wire SDRAM_nWE, // SDRAM Write Enable
output wire SDRAM_nCAS, // SDRAM Column Address Strobe
output wire SDRAM_nRAS, // SDRAM Row Address Strobe
output wire SDRAM_nCS, // SDRAM Chip Select
output wire [ 2-1:0] SDRAM_BA, // SDRAM Bank Address
output wire SDRAM_CLK, // SDRAM Clock
output wire SDRAM_CKE, // SDRAM Clock Enable
// MINIMIG specific
output wire AUDIO_L, // sigma-delta DAC output left
output wire AUDIO_R, // sigma-delta DAC output right
// SPI
inout wire SPI_DO,
input wire SPI_DI,
input wire SPI_SCK,
input wire SPI_SS2, // fpga
input wire SPI_SS3, // OSD
input wire SPI_SS4, // "sniff" mode
input wire CONF_DATA0 // SPI_SS for user_io
);
assign SDRAM_nCS = 1'b1; // disable ram
// reset geenration
reg [7:0] reset_cnt;
reg mem16kD, mem16kD2;
always @(posedge clk) begin
mem16kD <= mem16k;
mem16kD2 <= mem16kD;
// reset on board setup, when io controller signals reset
// or when memory size changes
if(!pll_locked || reset_in || (mem16kD != mem16kD2))
reset_cnt <= 8'h0;
else if(reset_cnt != 8'd255)
reset_cnt <= reset_cnt + 8'd1;
end
wire reset = (reset_cnt != 8'd255);
// pll to generate appropriate clock
wire clk13;
wire pll_locked;
clock clock (
.areset (1'b0 ), // async reset input
.inclk0 (CLOCK_27[0] ), // input clock (27MHz)
.c0 (clk13 ), // output clock c0 (13MHz)
.locked (pll_locked ) // pll locked output
);
// The 13Mhz is required for the scan doubler. The zx01 itself
// runs at 6.5 MHz which is generated from the 13MHz
reg clk;
always @(posedge clk13)
clk <= !clk;
// ------------- interface to arm controller -----------------
wire [1:0] buttons /* synthesis keep */;
wire [1:0] switches /* synthesis keep */;
// devide 6.5MHz clock by 2^9 giving ~12.7kHz
reg [8:0] clk_div;
wire clk_12k = clk_div[8];
always @(posedge clk)
clk_div <= clk_div + 9'd1;
wire ps2_clk;
wire ps2_data;
// the configuration string is returned to the io controller to allow
// it to control the menu on the OSD
parameter CONF_STR = {
"ZX01;P;",
"O1,Video standard,PAL,NTSC;",
"O2,Memory size,16k,1k;"
};
parameter CONF_STR_LEN = 7+27+22;
wire [7:0] status;
wire scandoubler_disable;
user_io #(.STRLEN(CONF_STR_LEN)) user_io(
.conf_str ( CONF_STR ),
// the spi interface
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ), // tristate handling inside user_io
.SPI_MOSI (SPI_DI ),
.scandoubler_disable ( scandoubler_disable ),
.SWITCHES (switches ),
.BUTTONS (buttons ),
// two joysticks supports
.JOY0 ( ),
.JOY1 ( ),
// status byte (bit 0 = io controller reset)
.status ( status ),
// ps2 keyboard interface
.clk (clk_12k ), // should be 10-16kHz for ps2 clock
.ps2_data (ps2_data ),
.ps2_clk (ps2_clk )
);
wire reset_in = status[0];
wire ntsc = !status[1];
wire mem16k = !status[2]; // bit 2 of status register is 0 when 16k is enabled
// ----------------------- Quick'n dirty scan doubler ---------------------------
// This reveals a problem of the zx01: The video timing isn't perfect,
// the hsync jumps in line 1 and in line 32 relative to the end of
// the vsync (top level line_cnt[]).
// This is causing the "shifted" line 32 at the top of the screen on
// a Dell 1908FP. It's unknown how other screens react on this.
// HSync comes 8 pixels late in line 1 and another 8 pixels late in
// line 32
// - ZX81 video basics
// The ZX81 video runs at 6.5Mhz Pixel clock, but most of the video
// state machine incl. the CPU runs at phi = 3.25MHz
// The total display width is 207 phi clocks. At 3.25 Mhz this is 15.7kHz
// Display starts at phi = 40 and ends at phi = 168 giving a total of 256
// pixels horizontally
// route cores vga output through OSD, extra parameters can be given to
// fine tune the OSD position in x and y direction. The third parameter
// adjusts the OSD color (0=dark grey, 1=blue, 2=green, 3=cyan, 4=red,
// 5=purple, 6=yellow, 7=light grey)
wire vga_hsync, vga_vsync;
// ZX81 generates csync already, just use that.
// Scandoubler generates hs from csync.
// Tape loading issues when Signal II Tap settings switched off,
// mystery, possibly due to optimisations breaking the tape
// interface?
wire video_hs = scandoubler_disable?csync:~hs;
// TV SCART has csync on hsync pin and "high" on vsync pin
assign VGA_VS = scandoubler_disable?1'b1:vga_vsync;
assign VGA_HS = scandoubler_disable?csync:vga_hsync;
wire osd_clk = scandoubler_disable?clk:clk13;
osd #(15,0,5) osd (
.pclk ( osd_clk ),
// spi for OSD
.sdi ( SPI_DI ),
.sck ( SPI_SCK ),
.ss ( SPI_SS3 ),
.red_in ( video6 ),
.green_in ( video6 ),
.blue_in ( video6 ),
.hs_in ( video_hs ),
.vs_in ( ~vs ),
.red_out ( VGA_R ),
.green_out ( VGA_G ),
.blue_out ( VGA_B ),
.hs_out ( vga_hsync ),
.vs_out ( vga_vsync )
);
wire [5:0] video6 = { vb, vb, vb, vb, vb, vb};
// "video bit" forced black outside horizontal display enable (h_de)
// and vsync (vs). Also the "transistor inverter" present in the zx01
// is implemented here
// 15khz takes video signal directly from ZX video.
wire vb = v_de && h_de && (scandoubler_disable?~video:~sd_video);
// video and csync output from the zx01
wire video;
wire csync;
// column counter running at 13MHz, twice the zx81 pixel clock
reg [8:0] sd_col;
// column counter running at 13MHz, but counting through a whole zx81 line
reg [9:0] zx_col;
// counter to determine sync lengths in the composity sync signal
// used to differentiate between hsync and vsync
reg [7:0] sync_len;
//reg vs, csD /* synthesis noprune */;
reg vs, csD;
// horizontal display goes from 40 to 168. We add 16 border pixels left and right
wire h_de = (sd_col >= (scandoubler_disable?40:(2*32))) && (sd_col < 2*182); // 176
// vertical display goes from line 32 to 224.We add 16 border pixels top and bottom
wire v_de = (line_cnt >= 16) && (line_cnt < 296); // 240
wire hs = sd_col >= (scandoubler_disable?192:(2*192));
// debug signal indicating that the scandoubler adjusted its hsync phase. This
// signal should only occur once at stargup. The fact that it also triggers in
// line 1 and line 32
reg trigger /* synthesis noprune */;
// line counter also for debug purposes
reg [9:0] line_cnt /* synthesis noprune */;
// enough space for two complete lines (incl. border and sync),
// each being 414 physical pixels wide
reg line_buffer[1023:0];
// toggle bit to switch between both line buffers
reg sd_toggle;
// video output of scan doubler
reg sd_video;
// scan doublers hsync/vsync generator runs on 6.5MHz
always @(posedge osd_clk) begin
trigger <= 1'b0;
csD <= csync;
if(csync) begin
sync_len <= 8'd0;
vs <= 1'b0;
end else begin
// count sync pulse length. Stop counting at 255
if(sync_len < 255)
sync_len <= sync_len + 8'd1;
// if counter passes 80 then we are seeing a vsync
if(sync_len == 80) begin
vs <= 1'b1;
line_cnt <= 10'd0;
end
end
// reset scan doubler column counter on rising edge of csync (end of sync) or
// every 414 pixels
if((sd_col == 413) ||(csync && !csD && sync_len < 80)) begin
// trigger whenever we adjust hsync position. This should happen only once, otherwise
// there are short/long lines
if(sd_col != 413)
trigger <= 1'b1;
sd_col <= 9'd0;
end else
sd_col <= sd_col + 9'd1;
// change toggle bit at the end of each zx line
if(csync && !csD) begin
sd_toggle <= !sd_toggle;
line_cnt <= line_cnt + 10'd1;
end
// zx81 column counter
if((csync && !csD && sync_len < 80)) begin
zx_col <= 10'd0;
end else
zx_col <= zx_col + 10'd1;
// fetch one line at half the scan doubler frequency
if(zx_col[0])
line_buffer[{sd_toggle, zx_col[9:1]}] = video;
// output other line at full scan doubler frequency
sd_video <= line_buffer[{!sd_toggle, sd_col}];
end
wire tape_data;
zx01 zx01 (
.n_reset (~reset ),
.clock (clk ),
.kbd_clk (ps2_clk ),
.kbd_data (ps2_data ),
.v_inv (1'b0 ),
.usa_uk (ntsc ),
.mem16k (mem16k ),
.video (video ),
.tape_in (tape_data ),
.tape_out (csync ),
// ignore LCD interface
.d_lcd ( ),
.s ( ),
.cp1 ( ),
.cp2 ( )
);
// create 500kHz from 13 Mhz
reg [4:0] clk_cnt;
wire clk_500k = clk_cnt < 13;
always @(posedge clk13) begin
clk_cnt <= clk_cnt + 5'd1;
if(clk_cnt == 5'd25)
clk_cnt <= 5'd0;
end
// tape transfers distort video, so we need a different kind
// of feedback
// we thus route type_data to led and to audio
assign LED = !tape_data;
// use a pwm to reduce audio output volume
reg [7:0] aclk;
always @(posedge clk13)
aclk <= aclk + 8'd1;
// limit volume to 1/8 => pwm < 32
wire tape_audio = tape_data && (aclk < 32);
assign AUDIO_L = tape_audio;
assign AUDIO_R = tape_audio;
tape tape (
// spi interface to io controller
.sdi ( SPI_DI ),
.sck ( SPI_SCK ),
.ss ( SPI_SS2 ),
.clk ( clk_500k ),
.play ( buttons[1] ),
.tape_out ( tape_data )
);
endmodule

513
cores/zxgate/zx/zx01/zx81rom.hex
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:101E5000AA55AA550000000000242400000000003C
:101E6000001C227820207E0000083E283E0A3E0802
:101E70000000001000001000003C420408000800B0
:101E800000040808080804000020101010102000AA
:101E900000001008040810000000040810080400E6
:101EA0000000003E003E0000000008083E08080058
:101EB000000000003E000000000014083E0814006E
:101EC0000000020408102000000010000010102084
:101ED00000000000000808100000000000181800B2
:101EE000003C464A52623C000018280808083E00A0
:101EF000003C42023C407E00003C420C02423C005E
:101F000000081828487E0800007E407C02423C0001
:101F1000003C407C42423C00007E0204081010005D
:101F2000003C423C42423C00003C42423E023C00FB
:101F3000003C42427E424200007C427C42427C00A5
:101F4000003C424040423C00007844424244780019
:101F5000007E407C40407E00007E407C404040004F
:101F6000003C42404E423C000042427E424242001F
:101F7000003E080808083E000002020242423C00FF
:101F800000444870484442000040404040407E00C9
:101F90000042665A42424200004262524A464200B1
:101FA000003C424242423C00007C42427C404000B5
:101FB000003C4242524A3C00007C42427C44420087
:101FC000003C403C02423C0000FE1010101010008B
:101FD0000042424242423C00004242424224180037
:101FE00000424242425A240000422418182442006F
:101FF0000082442810101000007E040810207E008B
:00000001FF

111
cores/zxgate/zx/zx97/busses.vhd
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@@ -1,111 +0,0 @@
----------------------------------------------------------
-- busses.vhd
-- Switching the busses
-- ====================
--
-- 04/29/97 Bodo Wenzel Got from old top.vhd
-- 11/17/97 Bodo Wenzel Cut down to ordinary ZX81
-- 12/02/97 Bodo Wenzel ROM select
-- 03/23/98 Bodo Wenzel Paging of memory
-- 01/28/99 Bodo Wenzel New banking
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- the inputs and outputs --------------------------------
entity busses is
port (mode_rom0: in boolean;
mode_romp: in std_ulogic_vector(1 downto 0);
mode_ram: in std_ulogic_vector(1 downto 0);
a_cpu: in std_ulogic_vector(15 downto 0);
video_addr: in std_ulogic_vector(8 downto 0);
video_mem: in boolean;
a_mem_h: out std_ulogic_vector(14 downto 13);
a_mem_l: out std_ulogic_vector(8 downto 0);
fake_cpu: in boolean;
d_kbd: in std_ulogic_vector(7 downto 0);
d_kbd_enable: in boolean;
d_mem_i: in std_ulogic_vector(7 downto 0);
d_cpu_o: out std_ulogic_vector(7 downto 0);
oe_cpu: out boolean;
oe_mem: out boolean;
n_m1: in std_ulogic;
n_mreq: in std_ulogic;
n_iorq: in std_ulogic;
n_wr: in std_ulogic;
n_rd: in std_ulogic;
n_rfsh: in std_ulogic;
n_romcs: out std_ulogic;
n_ramcs: out std_ulogic);
end;
-- the description of the logic --------------------------
architecture beh of busses is
begin
process (a_cpu,n_mreq,n_m1,n_rd,n_rfsh,
mode_romp,mode_rom0,mode_ram)
begin
n_romcs <= '1';
n_ramcs <= '1';
a_mem_h <= a_cpu(14 downto 13);
if n_mreq='0' then
case a_cpu(15 downto 13) is
when "000" =>
if n_rd='0' or n_rfsh='0' then
if mode_rom0 then
n_romcs <= '0';
else
n_ramcs <= '0';
end if;
end if;
a_mem_h <= mode_romp;
when "001" =>
if mode_ram="01" then
n_ramcs <= '0';
end if;
when "010" =>
n_ramcs <= '0';
when "011" =>
n_ramcs <= '0';
when "100" =>
n_ramcs <= '0';
when "101" =>
if mode_ram(1)='1' then
n_ramcs <= '0';
end if;
when "110" =>
if n_m1='0' then
n_ramcs <= '0';
elsif mode_ram="11" then
n_ramcs <= '0';
end if;
when "111" =>
if n_m1='0' then
n_ramcs <= '0';
elsif mode_ram="11" then
n_ramcs <= '0';
end if;
when others =>
null;
end case;
end if;
end process;
a_mem_l <= video_addr when video_mem
else a_cpu(8 downto 0);
d_cpu_o <= (others => '0') when fake_cpu
else d_kbd when d_kbd_enable
else (others => '1') when n_m1='0' and n_iorq='0'
else d_mem_i;
oe_cpu <= n_rd='0' or n_m1='0';
oe_mem <= n_wr='0';
end;
-- end ---------------------------------------------------

72
cores/zxgate/zx/zx97/io81.vhd
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@@ -1,72 +0,0 @@
----------------------------------------------------------
-- io81.vhd
-- ZX81 Input and Output
-- =====================
--
-- 04/28/97 Bodo Wenzel Got from old top.vhd
-- 11/14/97 Bodo Wenzel Some polish
-- 11/25/97 Bodo Wenzel Correcting errors
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- the inputs and outputs --------------------------------
entity io81 is
port (n_reset: in std_ulogic;
addr: in std_ulogic_vector(1 downto 0);
n_iorq: in std_ulogic;
n_wr: in std_ulogic;
n_rd: in std_ulogic;
vsync: out boolean;
nmi_enable: out boolean;
kbd_col: in std_ulogic_vector(4 downto 0);
usa_uk: in std_ulogic;
tape_in: in std_ulogic;
d_kbd: out std_ulogic_vector(7 downto 0);
d_kbd_enable: out boolean);
end;
-- the description of the logic --------------------------
architecture beh of io81 is
signal iowr: std_ulogic;
signal iord: std_ulogic;
signal i_nmi_enable: boolean;
begin
iowr <= not n_iorq and not n_wr;
iord <= not n_iorq and not n_rd;
process (n_reset,iowr)
begin
if n_reset='0' then
i_nmi_enable <= FALSE;
elsif rising_edge(iowr) then
if addr(0)='0' then
i_nmi_enable <= TRUE;
elsif addr(1)='0' then
i_nmi_enable <= FALSE;
end if;
end if;
end process;
nmi_enable <= i_nmi_enable;
process (iowr,iord)
begin
if iowr='1' then
vsync <= FALSE;
elsif rising_edge(iord) then
if addr(0)='0' and not i_nmi_enable then
vsync <= TRUE;
end if;
end if;
end process;
d_kbd <= tape_in & usa_uk & '0' & kbd_col;
d_kbd_enable <= n_iorq='0' and n_rd='0' and addr(0)='0';
end;
-- end ---------------------------------------------------

135
cores/zxgate/zx/zx97/lcd97.vhd
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@@ -1,135 +0,0 @@
----------------------------------------------------------
-- lcd97.vhd
-- LCD logic of ZX97
-- =================
--
-- 12/03/97 Bodo Wenzel Creation
-- 03/20/98 Bodo Wenzel Enhanced clocked processes
-- 02/08/99 Bodo Wenzel Reduce needed logic
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- the inputs and outputs --------------------------------
entity lcd97 is
port (clock: in std_ulogic;
n_sync: in std_ulogic;
video: in std_ulogic;
d_lcd: out std_ulogic_vector(3 downto 0);
s: out std_ulogic;
cp1: out std_ulogic;
cp2: out std_ulogic);
end;
-- the description of the logic --------------------------
architecture beh of lcd97 is
constant LINE_VSYNC: natural := 64;
constant LINE_PRE: natural := 48;
constant LINE_DISPLAY: natural := 80;
constant LINE_MAX: natural := 127;
constant HSYNC_PRE: natural := 24;
type LINE_STATE is (SYNC,PRE,DISPLAY,POST);
signal state: LINE_STATE;
signal line_cnt: natural range 0 to LINE_MAX;
signal vsync: boolean;
signal sync_1: boolean;
signal hsync_cnt: natural range 0 to HSYNC_PRE;
signal hsync_1: boolean;
signal pixel: std_ulogic_vector(4 downto 0);
begin
process (clock)
begin
if rising_edge(clock) then
case state is
when SYNC =>
if n_sync='1' then
state <= PRE;
line_cnt <= 0;
elsif not vsync then
line_cnt <= line_cnt+1;
end if;
vsync <= line_cnt>=LINE_VSYNC;
when PRE =>
if n_sync='0' then
state <= SYNC;
line_cnt <= 0;
elsif line_cnt>=LINE_PRE then
state <= DISPLAY;
line_cnt <= 0;
else
line_cnt <= line_cnt+1;
end if;
when DISPLAY =>
if n_sync='0' then
state <= SYNC;
line_cnt <= 0;
elsif line_cnt>=LINE_DISPLAY then
state <= POST;
elsif pixel(4)='0' then
line_cnt <= line_cnt+1;
end if;
when others =>
if n_sync='0' then
state <= SYNC;
line_cnt <= 0;
end if;
end case;
end if;
end process;
cp1 <= not n_sync;
process (vsync,clock)
begin
if vsync then
s <= '0';
hsync_cnt <= 0;
sync_1 <= FALSE;
elsif rising_edge(clock) then
if not sync_1 and state=SYNC then
if (not hsync_1) and hsync_cnt>=HSYNC_PRE then
s <= '1';
else
s <= '0';
end if;
if hsync_cnt<HSYNC_PRE then
hsync_cnt <= hsync_cnt+1;
end if;
hsync_1 <= hsync_cnt>=HSYNC_PRE;
end if;
sync_1 <= state=SYNC;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if pixel(4)='0' or state/=DISPLAY then
pixel <= "1110" & video;
else
pixel <= pixel(3 downto 0) & video;
end if;
end if;
end process;
d_lcd <= pixel(3 downto 0);
process (clock)
begin
if falling_edge(clock) then
cp2 <= pixel(4);
end if;
end process;
end;
-- end ---------------------------------------------------

87
cores/zxgate/zx/zx97/modes97.vhd
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@@ -1,87 +0,0 @@
----------------------------------------------------------
-- modes97.vhd
-- Modes for ZX97
-- ==============
--
-- 04/29/97 Bodo Wenzel Got from old top.vhd
-- 11/14/97 Bodo Wenzel Changed to POKE
-- 11/26/97 Bodo Wenzel ROM select
-- 03/20/98 Bodo Wenzel Paging of memory
-- and reading initial modes
-- 03/23/98 Bodo Wenzel Video inversion
-- 01/28/99 Bodo Wenzel New modes
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- the inputs and outputs --------------------------------
entity modes97 is
port (n_reset: in std_ulogic;
n_modes: in std_ulogic;
phi: in std_ulogic;
kbd_col: in std_ulogic_vector(4 downto 0);
addr: in std_ulogic_vector(15 downto 0);
data: in std_ulogic_vector(7 downto 0);
n_mreq: in std_ulogic;
n_wr: in std_ulogic;
mode_reset: out boolean;
mode_v_inv: out boolean;
mode_chr13: out std_ulogic;
mode_rom0: out boolean;
mode_romp: out std_ulogic_vector(1 downto 0);
mode_ram: out std_ulogic_vector(1 downto 0));
end;
-- the description of the logic --------------------------
architecture beh of modes97 is
constant POKE: std_ulogic_vector(15 downto 0)
:= "0000000000000111";
signal poke7: boolean;
begin
poke7 <= n_mreq='0' and n_wr='0' and addr=POKE;
process (n_reset,phi)
begin
if n_reset='0' then
mode_reset <= FALSE;
elsif rising_edge(phi) then
if poke7 then
mode_reset <= data(7)='1';
end if;
end if;
end process;
process (n_modes,phi)
begin
if n_modes='0' then
mode_chr13 <= '0';
mode_rom0 <= TRUE;
elsif rising_edge(phi) then
if poke7 then
mode_chr13 <= data(2);
mode_rom0 <= data(6)='1';
end if;
end if;
end process;
process (phi)
begin
if rising_edge(phi) then
if n_modes='0' then
mode_romp <= kbd_col(3 downto 2);
mode_v_inv <= kbd_col(4)='0';
mode_ram <= kbd_col(1 downto 0);
elsif poke7 then
mode_romp <= data(5 downto 4);
mode_v_inv <= data(3)='0';
mode_ram <= data(1 downto 0);
end if;
end if;
end process;
end;
-- end ---------------------------------------------------

72
cores/zxgate/zx/zx97/res_clk.vhd
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@@ -1,72 +0,0 @@
----------------------------------------------------------
-- res_clk.vhd
-- Reset and Clock
-- ===============
--
-- 04/28/97 Bodo Wenzel Got from old top.vhd
-- 11/27/97 Bodo Wenzel Some polish
-- 03/20/98 Bodo Wenzel Reset per software and
-- reading of initial modes
-- 01/26/99 Bodo Wenzel Reduced clock
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- the inputs and outputs --------------------------------
entity res_clk is
port (clock: in std_ulogic;
phi: in std_ulogic;
mode_reset: in boolean;
n_reset: out std_ulogic;
n_modes: out std_ulogic;
clock_2: out std_ulogic);
end;
-- the description of the logic --------------------------
architecture beh of res_clk is
constant RES_READ: natural := 4;
constant RES_MAX: natural := 8-1;
signal timer: natural range 0 to RES_MAX := 0;
-- The initialization is important!
signal i_reset: boolean;
signal i_phi: bit;
begin
n_modes <= '0' when (timer<RES_READ)
else '1';
i_reset <= (timer/=RES_MAX);
process (phi)
begin
if rising_edge(phi) then
if mode_reset then
timer <= RES_READ;
elsif i_reset then
timer <= timer+1;
end if;
end if;
end process;
n_reset <= '0' when i_reset
else '1';
process (clock)
begin
if rising_edge(clock) then
if i_phi='0' then
i_phi <= '1';
else
i_phi <= '0';
end if;
end if;
end process;
clock_2 <= '1' when i_phi='1'
else '0';
end;
-- end ---------------------------------------------------

229
cores/zxgate/zx/zx97/top.vhd
View File

@@ -1,229 +0,0 @@
----------------------------------------------------------
-- top.vhd
-- Top level of the ZX97
-- =====================
--
-- 04/10/97 Bodo Wenzel Dummy creation
-- 04/16/97 Bodo Wenzel Filling with "life"
-- 04/29/97 Bodo Wenzel Dividing into modules
-- 11/14/97 Bodo Wenzel Knowledge from ZX81VID
-- 11/25/97 Bodo Wenzel Correcting errors
-- 12/03/97 Bodo Wenzel Additional LCD output
-- 03/18/98 Bodo Wenzel HRG
-- 03/20/98 Bodo Wenzel Paging of memory and
-- reading of initial modes
-- 01/28/99 Bodo Wenzel Improvements
-- 04/10/02 Daniel Wallner Added synchronous bus support
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- the inputs and outputs --------------------------------
entity top is
generic (synchronous: boolean := false);
port (clock: in std_ulogic;
clock_2: out std_ulogic;
phi: in std_ulogic;
n_reset: out std_ulogic;
n_modes: out std_ulogic;
a_mem_h: out std_ulogic_vector(14 downto 13);
a_mem_l: out std_ulogic_vector(8 downto 0);
d_mem_i: in std_ulogic_vector(7 downto 0);
a_cpu: in std_ulogic_vector(15 downto 0);
d_cpu_i: in std_ulogic_vector(7 downto 0);
d_cpu_o: out std_ulogic_vector(7 downto 0);
oe_cpu: out boolean;
oe_mem: out boolean;
n_m1: in std_ulogic;
n_mreq: in std_ulogic;
n_iorq: in std_ulogic;
n_wr: in std_ulogic;
n_rd: in std_ulogic;
n_rfsh: in std_ulogic;
n_nmi: out std_ulogic;
n_halt: in std_ulogic;
n_wait: out std_ulogic;
n_romcs: out std_ulogic;
n_ramcs: out std_ulogic;
kbd_col: in std_ulogic_vector(4 downto 0);
usa_uk: in std_ulogic;
video: out std_ulogic;
n_sync: out std_ulogic;
tape_in: in std_ulogic;
d_lcd: out std_ulogic_vector(3 downto 0);
s: out std_ulogic;
cp1: out std_ulogic;
cp2: out std_ulogic);
end;
-- the description of the logic --------------------------
architecture beh of top is
component res_clk
port (clock: in std_ulogic;
phi: in std_ulogic;
mode_reset: in boolean;
n_reset: out std_ulogic;
n_modes: out std_ulogic;
clock_2: out std_ulogic);
end component;
component modes97
port (n_reset: in std_ulogic;
n_modes: in std_ulogic;
phi: in std_ulogic;
kbd_col: in std_ulogic_vector(4 downto 0);
addr: in std_ulogic_vector(15 downto 0);
data: in std_ulogic_vector(7 downto 0);
n_mreq: in std_ulogic;
n_wr: in std_ulogic;
mode_reset: out boolean;
mode_v_inv: out boolean;
mode_chr13: out std_ulogic;
mode_rom0: out boolean;
mode_romp: out std_ulogic_vector(1 downto 0);
mode_ram: out std_ulogic_vector(1 downto 0));
end component;
component video81
generic (synchronous: boolean := false);
port (clock: in std_ulogic;
phi: in std_ulogic;
nmi_enable: in boolean;
n_nmi: out std_ulogic;
n_halt: in std_ulogic;
n_wait: out std_ulogic;
n_m1: in std_ulogic;
n_mreq: in std_ulogic;
n_iorq: in std_ulogic;
vsync: in boolean;
a_cpu: in std_ulogic_vector(15 downto 13);
d_mem: in std_ulogic_vector(7 downto 0);
fake_cpu: out boolean;
mode_chr13: in std_ulogic;
video_addr: out std_ulogic_vector(8 downto 0);
video_mem: out boolean;
mode_v_inv: in boolean;
video: out std_ulogic;
n_sync: out std_ulogic);
end component;
component lcd97
port (clock: in std_ulogic;
n_sync: in std_ulogic;
video: in std_ulogic;
d_lcd: out std_ulogic_vector(3 downto 0);
s: out std_ulogic;
cp1: out std_ulogic;
cp2: out std_ulogic);
end component;
component io81
port (n_reset: in std_ulogic;
addr: in std_ulogic_vector(1 downto 0);
n_iorq: in std_ulogic;
n_wr: in std_ulogic;
n_rd: in std_ulogic;
vsync: out boolean;
nmi_enable: out boolean;
kbd_col: in std_ulogic_vector(4 downto 0);
usa_uk: in std_ulogic;
tape_in: in std_ulogic;
d_kbd: out std_ulogic_vector(7 downto 0);
d_kbd_enable: out boolean);
end component;
component busses
port (mode_rom0: in boolean;
mode_romp: in std_ulogic_vector(1 downto 0);
mode_ram: in std_ulogic_vector(1 downto 0);
a_cpu: in std_ulogic_vector(15 downto 0);
video_addr: in std_ulogic_vector(8 downto 0);
video_mem: in boolean;
a_mem_h: out std_ulogic_vector(14 downto 13);
a_mem_l: out std_ulogic_vector(8 downto 0);
fake_cpu: in boolean;
d_kbd: in std_ulogic_vector(7 downto 0);
d_kbd_enable: in boolean;
d_mem_i: in std_ulogic_vector(7 downto 0);
d_cpu_o: out std_ulogic_vector(7 downto 0);
oe_cpu: out boolean;
oe_mem: out boolean;
n_m1: in std_ulogic;
n_mreq: in std_ulogic;
n_iorq: in std_ulogic;
n_wr: in std_ulogic;
n_rd: in std_ulogic;
n_rfsh: in std_ulogic;
n_romcs: out std_ulogic;
n_ramcs: out std_ulogic);
end component;
signal i_n_reset: std_ulogic;
signal i_n_modes: std_ulogic;
signal mode_reset: boolean;
signal mode_v_inv: boolean;
signal mode_chr13: std_ulogic;
signal mode_rom0: boolean;
signal mode_romp: std_ulogic_vector(1 downto 0);
signal mode_ram: std_ulogic_vector(1 downto 0);
signal vsync: boolean;
signal nmi_enable: boolean;
signal fake_cpu: boolean;
signal video_addr: std_ulogic_vector(8 downto 0);
signal video_mem: boolean;
signal i_video: std_ulogic;
signal i_n_sync: std_ulogic;
signal d_kbd: std_ulogic_vector(7 downto 0);
signal d_kbd_enable: boolean;
begin
c_res_clk: res_clk
port map (clock,phi,mode_reset,
i_n_reset,i_n_modes,clock_2);
c_modes97: modes97
port map (i_n_reset,i_n_modes,phi,
kbd_col,a_cpu,d_cpu_i,n_mreq,n_wr,
mode_reset,mode_v_inv,mode_chr13,
mode_rom0,mode_romp,mode_ram);
c_video81: video81
generic map (synchronous)
port map (clock,phi,
nmi_enable,n_nmi,n_halt,n_wait,
n_m1,n_mreq,n_iorq,
vsync,
a_cpu(15 downto 13),d_mem_i,
fake_cpu,mode_chr13,
video_addr,video_mem,
mode_v_inv,i_video,i_n_sync);
c_lcd97: lcd97
port map (clock,
i_n_sync,i_video,
d_lcd,s,cp1,cp2);
c_io81: io81
port map (i_n_reset,
a_cpu(1 downto 0),n_iorq,n_wr,n_rd,
vsync,nmi_enable,
kbd_col,usa_uk,tape_in,d_kbd,d_kbd_enable);
c_busses: busses
port map (mode_rom0,mode_romp,mode_ram,
a_cpu,video_addr,video_mem,a_mem_h,a_mem_l,
fake_cpu,d_kbd,d_kbd_enable,d_mem_i,d_cpu_o,
oe_cpu,oe_mem,
n_m1,n_mreq,n_iorq,n_wr,n_rd,n_rfsh,
n_romcs,n_ramcs);
n_reset <= i_n_reset;
n_modes <= i_n_modes;
video <= i_video;
n_sync <= i_n_sync;
end;
-- end ---------------------------------------------------

171
cores/zxgate/zx/zx97/video81.vhd
View File

@@ -1,171 +0,0 @@
----------------------------------------------------------
-- video81.vhd
-- Videologic of ZX81
-- ==================
--
-- 04/29/97 Bodo Wenzel Got from old top.vhd
-- 11/18/97 Bodo Wenzel Knowledge from ZX81VID
-- 11/21/97 Bodo Wenzel Correcting errors
-- 12/03/97 Bodo Wenzel Additional LCD output
-- 03/18/98 Bodo Wenzel HRG, if refresh >= 4000H
-- 03/19/98 Bodo Wenzel Added mode_v_inv
-- 03/23/98 Bodo Wenzel Faking only if >=0C000H
-- 01/26/99 Bodo Wenzel Reduce needed logic
-- 04/10/02 Daniel Wallner Added synchronous bus support
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- the inputs and outputs --------------------------------
entity video81 is
generic (synchronous: boolean := false);
port (clock: in std_ulogic;
phi: in std_ulogic;
nmi_enable: in boolean;
n_nmi: out std_ulogic;
n_halt: in std_ulogic;
n_wait: out std_ulogic;
n_m1: in std_ulogic;
n_mreq: in std_ulogic;
n_iorq: in std_ulogic;
vsync: in boolean;
a_cpu: in std_ulogic_vector(15 downto 13);
d_mem: in std_ulogic_vector(7 downto 0);
fake_cpu: out boolean;
mode_chr13: in std_ulogic;
video_addr: out std_ulogic_vector(8 downto 0);
video_mem: out boolean;
mode_v_inv: in boolean;
video: out std_ulogic;
n_sync: out std_ulogic);
end;
-- the description of the logic --------------------------
architecture beh of video81 is
constant HSYNC_BEGIN: natural := 192;
constant HSYNC_GAP: natural := 16;
constant LINE_LEN: natural := 207-1;
signal line_cnt: natural range 0 to LINE_LEN;
signal hsync: boolean;
signal hsync2: boolean;
signal nmi_out: boolean;
signal faking: boolean;
signal row_count: unsigned(2 downto 0);
signal chr_inv: std_ulogic;
signal chr_addr: std_ulogic_vector(5 downto 0);
signal video_pixel: std_ulogic_vector(7 downto 0);
signal video_read: boolean;
begin
process (vsync,phi)
begin
if vsync then
line_cnt <= 0;
elsif rising_edge(phi) then
if n_iorq='0' and n_m1='0' then
line_cnt <= HSYNC_BEGIN-HSYNC_GAP;
elsif line_cnt>=LINE_LEN then
line_cnt <= 0;
else
line_cnt <= line_cnt+1;
end if;
end if;
end process;
hsync <= (line_cnt>=HSYNC_BEGIN);
nmi_out <= (hsync and nmi_enable);
n_nmi <= '0' when nmi_out
else '1';
n_wait <= '0' when nmi_out and n_halt='1'
else '1';
n_sync <= '0' when hsync or vsync
else '1';
process (phi)
begin
if falling_edge(phi) then
if n_m1='0' and n_mreq='0' and
a_cpu(15)='1' and a_cpu(14)='1' and
d_mem(6)='0' and n_halt='1' then
chr_inv <= d_mem(7);
chr_addr <= d_mem(5 downto 0);
faking <= TRUE;
elsif n_mreq='0' then
faking <= FALSE;
end if;
end if;
end process;
fake_cpu <= faking and n_m1='0';
process (vsync,clock)
begin
if vsync then
row_count <= (others=>'0');
elsif rising_edge(clock) then
if hsync and not hsync2 then
row_count <= row_count+1;
end if;
hsync2 <= hsync;
end if;
end process;
video_mem <= faking and n_m1='1' and
a_cpu(15)='0' and a_cpu(14)='0' and
(a_cpu(13)='0' or mode_chr13='1');
video_addr <= chr_addr & std_ulogic_vector(row_count);
g_synct : if synchronous generate
process (clock)
begin
if rising_edge(clock) then
if faking and n_mreq='0' and n_m1='1' and not video_read then
video_read <= true;
else
video_read <= false;
end if;
end if;
end process;
end generate;
g_syncf : if not synchronous generate
process (n_mreq,phi)
begin
if n_mreq='1' then
video_read <= FALSE;
elsif rising_edge(phi) then
video_read <= faking;
end if;
end process;
end generate;
process (clock)
begin
if rising_edge(clock) then
if video_read then
if chr_inv='0' then
video_pixel <= d_mem;
else
video_pixel <= not d_mem;
end if;
else
for i in 7 downto 1 loop
video_pixel(i) <= video_pixel(i-1);
end loop;
video_pixel(0) <= '0';
end if;
end if;
end process;
video <= video_pixel(7) when mode_v_inv
else not video_pixel(7);
end;
-- end ---------------------------------------------------

166
cores/zxgate/zx/zx97/zx97.vhd
View File

@@ -1,166 +0,0 @@
----------------------------------------------------------
-- zx97.vhd
-- Pad bindings of the ZX97 FPGA
-- =============================
--
-- 04/25/97 Bodo Wenzel Creation
-- 11/17/97 Bodo Wenzel Some polish
-- 11/25/97 Bodo Wenzel Single video output
-- 12/03/97 Bodo Wenzel Additional LCD output
-- 03/20/98 Bodo Wenzel Reading of initial modes
-- 02/08/99 Bodo Wenzel Improvements
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;
-- the pads ----------------------------------------------
entity zx97 is
port (n_reset: out std_ulogic;
phi: out std_ulogic;
n_modes: out std_ulogic;
a_mem_h: out std_ulogic_vector(14 downto 13);
a_mem_l: out std_ulogic_vector(8 downto 0);
d_mem: inout std_logic_vector(7 downto 0);
a_cpu: in std_ulogic_vector(15 downto 0);
d_cpu: inout std_logic_vector(7 downto 0);
n_m1: in std_ulogic;
n_mreq: in std_ulogic;
n_iorq: in std_ulogic;
n_wr: in std_ulogic;
n_rd: in std_ulogic;
n_rfsh: in std_ulogic;
n_nmi: out std_ulogic;
n_halt: in std_ulogic;
n_wait: out std_ulogic;
n_romcs: out std_ulogic;
n_ramcs: out std_ulogic;
kbd_col: inout std_logic_vector(4 downto 0);
usa_uk: inout std_logic;
video: out std_ulogic;
tape_in: in std_ulogic;
d_lcd: out std_ulogic_vector(3 downto 0);
s: out std_ulogic;
cp1: out std_ulogic;
cp2: out std_ulogic);
end;
-- the input/output-buffers ------------------------------
architecture iopads of zx97 is
component gxtl
port (o: out std_ulogic);
end component;
component gclk
port (i: in std_logic;
o: out std_ulogic);
end component;
component pullup
port (o: out std_logic);
end component;
component ibuf
port (i: inout std_logic;
o: out std_ulogic);
end component;
component top
port (clock: in std_ulogic;
clock_2: out std_ulogic;
phi: in std_ulogic;
n_reset: out std_ulogic;
n_modes: out std_ulogic;
a_mem_h: out std_ulogic_vector(14 downto 13);
a_mem_l: out std_ulogic_vector(8 downto 0);
d_mem_i: in std_ulogic_vector(7 downto 0);
a_cpu: in std_ulogic_vector(15 downto 0);
d_cpu_i: in std_ulogic_vector(7 downto 0);
d_cpu_o: out std_ulogic_vector(7 downto 0);
oe_cpu: out boolean;
oe_mem: out boolean;
n_m1: in std_ulogic;
n_mreq: in std_ulogic;
n_iorq: in std_ulogic;
n_wr: in std_ulogic;
n_rd: in std_ulogic;
n_rfsh: in std_ulogic;
n_nmi: out std_ulogic;
n_halt: in std_ulogic;
n_wait: out std_ulogic;
n_romcs: out std_ulogic;
n_ramcs: out std_ulogic;
kbd_col: in std_ulogic_vector(4 downto 0);
usa_uk: in std_ulogic;
video: out std_ulogic;
n_sync: out std_ulogic;
tape_in: in std_ulogic;
d_lcd: out std_ulogic_vector(3 downto 0);
s: out std_ulogic;
cp1: out std_ulogic;
cp2: out std_ulogic);
end component;
signal clock: std_ulogic;
signal clock_2: std_ulogic;
signal i_phi: std_ulogic;
signal i_n_modes: std_ulogic;
signal oe_cpu: boolean;
signal oe_mem: boolean;
signal d_mem_i: std_ulogic_vector(7 downto 0);
signal d_cpu_i: std_ulogic_vector(7 downto 0);
signal d_cpu_o: std_ulogic_vector(7 downto 0);
signal i_kbd_col: std_ulogic_vector(4 downto 0);
signal i_usa_uk: std_ulogic;
signal i_video: std_ulogic;
signal i_n_sync: std_ulogic;
begin
c_top: top
port map (clock,clock_2,i_phi,
n_reset,i_n_modes,
a_mem_h,a_mem_l,d_mem_i,
a_cpu,d_cpu_i,d_cpu_o,
oe_cpu,oe_mem,
n_m1,n_mreq,n_iorq,n_wr,n_rd,n_rfsh,
n_nmi,n_halt,n_wait,n_romcs,n_ramcs,
i_kbd_col,i_usa_uk,
i_video,i_n_sync,tape_in,
d_lcd,s,cp1,cp2);
c_clock: gxtl port map (o=>clock);
c_clock2: gclk port map (i=>clock_2,o=>i_phi);
phi <= clock_2;
n_modes <= '0' when i_n_modes='0'
else 'Z';
d_mem_i <= std_ulogic_vector(d_mem);
d_mem <= std_logic_vector(d_cpu_i) when oe_mem
else (others => 'Z');
d_cpu_i <= std_ulogic_vector(d_cpu);
d_cpu <= std_logic_vector(d_cpu_o) when oe_cpu
else (others => 'Z');
g_kbd_col:
for i in kbd_col'range generate
r_kbd_col: pullup port map (o=>kbd_col(i));
p_kbd_col: ibuf port map (i=>kbd_col(i),
o=>i_kbd_col(i));
end generate;
r_usa_uk: pullup port map (o=>usa_uk);
p_usa_uk: ibuf port map (i=>usa_uk,o=>i_usa_uk);
video <= '0' when i_n_sync='0'
else 'Z' when i_video='0'
else '1';
end;
-- end ---------------------------------------------------