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Code Issues Releases Wiki Activity

C64: better handling of AEC signal

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This commit is contained in:
Gyorgy Szombathelyi
2020-04-07 22:49:13 +02:00
parent 87f9d2ebe4
commit 7030db2db0
2 changed files with 10 additions and 7 deletions
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9
cores/c64/rtl/fpga64_buslogic_roms_mmu.vhd
View File

@@ -28,6 +28,7 @@ entity fpga64_buslogic is
reset : in std_logic;
cpuHasBus : in std_logic;
aec : in std_logic;
ramData: in unsigned(7 downto 0);
@@ -265,8 +266,12 @@ begin
systemWe <= cpuWe;
else
-- The VIC-II has the bus.
currentAddr <= vicAddr;
-- The VIC-II has the bus, but only when aec is asserted
if aec = '1' then
currentAddr <= vicAddr;
else
currentAddr <= cpuAddr;
end if;
if ultimax = '0' and vicAddr(14 downto 12)="001" then
vicCharReg <= '1';

8
cores/c64/rtl/fpga64_sid_iec.vhd
View File

@@ -164,7 +164,6 @@ architecture rtl of fpga64_sid_iec is
signal phi0_cpu : std_logic;
signal phi0_vic : std_logic;
signal cpuHasBus : std_logic;
signal cpuHasBusLoc : std_logic;
signal cycleRestart : std_logic;
signal cycleRestartReg1 : std_logic;
@@ -379,12 +378,12 @@ begin
if sysCycle = sysCycleDef'pred(CYCLE_CPU0) then
phi0_cpu <= '1';
if baLoc = '1' or cpuWe = '1' then
cpuHasBusLoc <= '1';
cpuHasBus <= '1';
end if;
end if;
if sysCycle = sysCycleDef'high then
phi0_cpu <= '0';
cpuHasBusLoc <= '0';
cpuHasBus <= '0';
end if;
if sysCycle = sysCycleDef'pred(CYCLE_VIC0) then
phi0_vic <= '1';
@@ -395,8 +394,6 @@ begin
end if;
end process;
cpuHasBus <= cpuHasBusLoc or not aec;
process(clk32)
begin
if rising_edge(clk32) then
@@ -463,6 +460,7 @@ begin
clk => clk32,
reset => reset,
cpuHasBus => cpuHasBus,
aec => aec,
bankSwitch => cpuIO(2 downto 0),