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[C64] CIA: fix serial port

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Passes VICE tests
This commit is contained in:
Gyorgy Szombathelyi
2019-01-29 00:20:13 +01:00
parent c0ac7958a3
commit 7123b3fb50
1 changed files with 47 additions and 38 deletions
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85
cores/c64/rtl/mos6526.v
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@@ -409,40 +409,48 @@ always @(posedge clk) begin
sp_shiftreg <= 8'h00;
icr[3] <= 1'b0;
end
else if (!cs_n && !rw)
case (rs)
4'hc: sdr <= db_in;
default: sdr <= sdr;
endcase
if (!cra[6]) begin
if (sp_received) begin
sdr <= sp_shiftreg;
icr[3] <= 1'b1;
sp_received <= 1'b0;
sp_shiftreg <= 8'h00;
end
else if (cnt_in && !cnt_in_prev) begin
sp_shiftreg <= {sp_shiftreg[6:0], sp_in};
sp_received <= (cnt_pulsecnt == 3'h7) ? 1'b1 : sp_received;
end
end
else if (cra[6] && !cra[3] && cra[0]) begin
if (!cs_n && !rw && rs == 8'hc) sp_pending <= 1'b1;
if (sp_pending && !sp_transmit) begin
sp_pending <= 1'b0;
sp_transmit <= 1'b1;
sp_shiftreg <= sdr;
end
else if (!cnt_out && cnt_out_prev) begin
if (cnt_pulsecnt == 3'h7) begin
icr[3] <= 1'b1;
sp_transmit <= 1'b0;
else begin
if (!cs_n && !rw)
case (rs)
4'hc:
begin
sdr <= db_in;
sp_pending <= 1;
end
endcase
if (phi2) begin
if (int_reset) icr[3] <= 1'b0;
if (!cra[6]) begin // input
if (sp_received) begin
sdr <= sp_shiftreg;
icr[3] <= 1'b1;
sp_received <= 1'b0;
sp_shiftreg <= 8'h00;
end
else if (cnt_in && !cnt_in_prev) begin
sp_shiftreg <= {sp_shiftreg[6:0], sp_in};
sp_received <= (cnt_pulsecnt == 3'h7) ? 1'b1 : sp_received;
end
end
else if (cra[6]) begin // output
if (sp_pending && !sp_transmit) begin
sp_pending <= 1'b0;
sp_transmit <= 1'b1;
sp_shiftreg <= sdr;
end
else if (!cnt_out && cnt_out_prev) begin
if (cnt_pulsecnt == 3'h7) begin
icr[3] <= 1'b1;
sp_transmit <= 1'b0;
end
sp_out <= sp_shiftreg[7];
sp_shiftreg <= {sp_shiftreg[6:0], 1'b0};
end
end
sp_out <= sp_shiftreg[7];
sp_shiftreg <= {sp_shiftreg[6:0], 1'b0};
end
end
if (int_reset) icr[3] <= 1'b0;
end
// CNT Input/Output
@@ -455,14 +463,15 @@ always @(posedge clk) begin
else if (phi2) begin
cnt_in_prev <= cnt_in;
cnt_out_prev <= cnt_out;
end
if (!cra[6] && cnt_in && !cnt_in_prev) cnt_pulsecnt <= cnt_pulsecnt + 1'b1;
else if (cra[6] && !cra[3] && cra[0]) begin
if (sp_transmit) begin
cnt_out <= timerAoverflow ? ~cnt_out : cnt_out;
if (!cnt_out && cnt_out_prev) cnt_pulsecnt <= cnt_pulsecnt + 1'b1;
if (!cra[6] && cnt_in && !cnt_in_prev) cnt_pulsecnt <= cnt_pulsecnt + 1'b1;
else if (cra[6]) begin
if (sp_transmit) begin
cnt_out <= timerAoverflow ? ~cnt_out : cnt_out;
if (!cnt_out && cnt_out_prev) cnt_pulsecnt <= cnt_pulsecnt + 1'b1;
end
else cnt_out <= timerAoverflow ? 1'b1 : cnt_out;
end
else cnt_out <= timerAoverflow ? 1'b1 : cnt_out;
end
end