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Merge pull request #93 from gyurco/c64

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C64 tap support
This commit is contained in:
gyurco
2019-04-10 23:23:19 +02:00
committed by GitHub
parent f4bde270c0 4e01b7df47
commit 7e0dbf9360
6 changed files with 526 additions and 40 deletions
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21
cores/c64/C64_mist.qsf
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@@ -138,9 +138,9 @@ set_global_assignment -name SAVE_DISK_SPACE OFF
# ==================
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
@@ -166,7 +166,7 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/pll.stp
set_global_assignment -name USE_SIGNALTAP_FILE output_files/ioctl.stp
# Power Estimation Assignments
# ============================
@@ -337,6 +337,13 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
set_location_assignment PIN_46 -to UART_TX
set_location_assignment PIN_31 -to UART_RX
set_location_assignment PLL_1 -to pll|altpll_component|auto_generated|pll1
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to UART_TX
set_global_assignment -name VHDL_FILE rtl/tap_fifo.vhd
set_global_assignment -name VHDL_FILE rtl/c1530.vhd
set_global_assignment -name VERILOG_FILE rtl/sid8580/sid_voice.v
set_global_assignment -name VERILOG_FILE rtl/sid8580/sid_filters.v
set_global_assignment -name VERILOG_FILE rtl/sid8580/sid_envelope.v
@@ -399,9 +406,5 @@ set_global_assignment -name QIP_FILE rtl/mist/pll_c64_reconfig.qip
set_global_assignment -name QIP_FILE rtl/mist/rom_reconfig_pal.qip
set_global_assignment -name QIP_FILE rtl/mist/rom_reconfig_ntsc.qip
set_global_assignment -name SIGNALTAP_FILE output_files/pll.stp
set_location_assignment PIN_46 -to UART_TX
set_location_assignment PIN_31 -to UART_RX
set_location_assignment PLL_1 -to pll|altpll_component|auto_generated|pll1
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to UART_TX
set_global_assignment -name SIGNALTAP_FILE output_files/ioctl.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

4
cores/c64/C64_mist.sdc
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@@ -52,8 +52,8 @@ set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|cl
set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_CLK}]
set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_CLK}]
set_multicycle_path -from {video_mixer:vmixer|scandoubler:scandoubler|Hq2x:Hq2x|*} -to {VGA_*[*]} -setup 4
set_multicycle_path -from {video_mixer:vmixer|scandoubler:scandoubler|Hq2x:Hq2x|*} -to {VGA_*[*]} -hold 3
set_multicycle_path -from {video_mixer:vmixer|scandoubler:scandoubler|Hq2x:Hq2x|*} -setup 4
set_multicycle_path -from {video_mixer:vmixer|scandoubler:scandoubler|Hq2x:Hq2x|*} -hold 3
set_multicycle_path -to {VGA_*[*]} -setup 4
set_multicycle_path -to {VGA_*[*]} -hold 3

194
cores/c64/rtl/c1530.vhd Normal file
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@@ -0,0 +1,194 @@
---------------------------------------------------------------------------------
-- Commodore 1530 to SD card host (read only) by Dar (darfpga@aol.fr) 25-Mars-2019
-- http://darfpga.blogspot.fr
-- also darfpga on sourceforge
--
-- tap/wav player
-- Converted to 8 bit FIFO - Slingshot
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity c1530 is
port(
clk32 : in std_logic;
restart_tape : in std_logic; -- keep to 1 to long enough to clear fifo
-- reset tap header bytes skip counter
wav_mode : in std_logic; -- 1 for wav mode, 0 for tap mode
tap_mode1 : in std_logic; -- 1 for tap version 1, 0 for tap version 0
host_tap_in : in std_logic_vector(7 downto 0); -- 8bits fifo input
host_tap_wrreq : in std_logic; -- set to 1 for 1 clk32 to write 1 word
tap_fifo_wrfull : out std_logic; -- do not write when fifo tap_fifo_full = 1
tap_fifo_error : out std_logic; -- fifo fall empty (unrecoverable error)
play : in std_logic; -- 1 = read tape, 0 = stop reading
do : out std_logic -- tape signal out
);
end c1530;
architecture struct of c1530 is
signal tap_player_tick_cnt : std_logic_vector( 5 downto 0);
signal wav_player_tick_cnt : std_logic_vector(11 downto 0);
signal tap_dword : std_logic_vector(31 downto 0);
signal wave_cnt : std_logic_vector(23 downto 0);
signal wave_len : std_logic_vector(23 downto 0);
signal tap_fifo_do : std_logic_vector(7 downto 0);
signal tap_fifo_rdreq : std_logic;
signal tap_fifo_empty : std_logic;
signal get_24bits_len : std_logic;
signal start_bytes : std_logic_vector(7 downto 0);
signal skip_bytes : std_logic;
signal playing : std_logic;
begin
-- for wav mode use large depth fifo (eg 512 x 32bits)
-- for tap mode fifo may be smaller (eg 16 x 32bits)
tap_fifo_inst : entity work.tap_fifo
port map(
aclr => restart_tape,
data => host_tap_in,
clock => clk32,
rdreq => tap_fifo_rdreq,
wrreq => host_tap_wrreq,
q => tap_fifo_do,
empty => tap_fifo_empty,
full => tap_fifo_wrfull
);
process(clk32, restart_tape)
begin
if restart_tape = '1' then
start_bytes <= X"00";
skip_bytes <= '1';
tap_player_tick_cnt <= (others => '0');
wav_player_tick_cnt <= (others => '0');
wave_len <= (others => '0');
wave_cnt <= (others => '0');
get_24bits_len <= '0';
playing <= '0';
tap_fifo_rdreq <='0';
tap_fifo_error <='0'; -- run out of data
elsif rising_edge(clk32) then
tap_fifo_rdreq <= '0';
if playing = '0' then
tap_fifo_error <= '0';
wave_cnt <= (others => '0');
wave_len <= (others => '0');
tap_player_tick_cnt <= (others => '0');
wav_player_tick_cnt <= (others => '0');
end if;
if play = '1' then playing <= '1'; end if;
if ((playing = '1') and (wav_mode = '1')) then
-- Wav player required a large depth fifo to give chance
-- fifo not falling empty while host go reading next sd card sector
-- (fifo is read every ~22µs, host have to be faster than 11ms to read sd sector)
wav_player_tick_cnt <= wav_player_tick_cnt + '1';
if wav_player_tick_cnt = x"2F0" then -- ~33MHz/44.1KHz
wav_player_tick_cnt <= (others => '0');
-- check for empty fifo (unrecoverable error)
if tap_fifo_empty = '1' then
tap_fifo_error <= '1';
else
tap_fifo_rdreq <= '1';
end if;
end if;
do <= not tap_fifo_do(7); -- only use msb (wav data is either xFF or x00/x01)
end if; -- play wav mode
-- tap player
if ((playing = '1') and (wav_mode = '0')) then
tap_player_tick_cnt <= tap_player_tick_cnt + '1';
-- if ((tap_player_tick_cnt = "100000") and (skip_bytes = '0')) then -- divide by 33
if ((tap_player_tick_cnt = "011111") and (skip_bytes = '0')) then -- divide by 32
-- square wave period (1/2 duty cycle not mendatory, only falling edge matter)
if wave_cnt > '0'&wave_len(10 downto 1) then
do <= '1';
else
do <= '0';
end if;
tap_player_tick_cnt <= "000000";
wave_cnt <= wave_cnt + 1;
if wave_cnt >= wave_len then
wave_cnt <= (others => '0');
if play = '0' then
playing <= '0';
do <= '0';
else
if tap_fifo_empty = '1' then
tap_fifo_error <= '1';
else
tap_fifo_rdreq <= '1';
if tap_fifo_do = x"00" then
wave_len <= x"000100"; -- interpret data x00 for mode 0
get_24bits_len <= tap_mode1;
else
wave_len <= '0'&x"000" & tap_fifo_do & "000";
end if;
end if;
end if;
end if;
end if; -- tap_player_tick_cnt = "100000"
-- catch 24bits wave_len for data x00 in tap mode 1
if (get_24bits_len = '1' ) and (skip_bytes = '0') and (tap_player_tick_cnt(0) = '1') then
if tap_player_tick_cnt = "000101" then
get_24bits_len <= '0';
end if;
if tap_fifo_empty = '1' then
tap_fifo_error <= '1';
else
tap_fifo_rdreq <= '1';
wave_len <= tap_fifo_do & wave_len(23 downto 8);
end if;
do <= '1';
end if;
-- skip tap header bytes
if (skip_bytes = '1' and tap_fifo_empty = '0') then
tap_fifo_rdreq <= '1';
do <= '1';
if start_bytes < X"1A" then -- little more than x14
start_bytes <= start_bytes + X"01";
else
skip_bytes <= '0';
end if;
end if;
end if; -- play tap mode
end if; -- clk32
end process;
end struct;

11
cores/c64/rtl/fpga64_sid_iec.vhd
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@@ -131,6 +131,11 @@ entity fpga64_sid_iec is
cia_mode : in std_logic;
todclk : in std_logic;
cass_motor : out std_logic;
cass_write : out std_logic;
cass_sense : in std_logic;
cass_do : in std_logic;
disk_num : out std_logic_vector(7 downto 0);
c64rom_addr : in std_logic_vector(13 downto 0);
@@ -697,7 +702,7 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID)
pb_in => std_logic_vector(cia1_pbi),
unsigned(pb_out) => cia1_pbo,
flag_n => flag2_n,
flag_n => cass_do,
sp_in => sp1_in,
sp_out => sp1_out,
cnt_in => cnt1_in,
@@ -757,10 +762,12 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID)
do => cpuDo,
we => cpuWe,
diIO => cpuIO(7) & cpuIO(6) & "01" & cpuIO(3) & "111",
diIO => cpuIO(7) & cpuIO(6) & cpuIO(5) & cass_sense & cpuIO(3) & "111",
doIO => cpuIO
);
cass_motor <= cpuIO(5);
cass_write <= cpuIO(3);
-- -----------------------------------------------------------------------
-- Keyboard
-- -----------------------------------------------------------------------

146
cores/c64/rtl/mist/c64_mist.vhd
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@@ -130,11 +130,11 @@ end component;
constant CONF_STR : string :=
"C64;;"&
"S,D64,Mount Disk;"&
"F,PRG,Load File;"&
"F,CRT,Load Cartridge;" &--3
"F,ROM,Load Kernal;"&
-- "F,TAP,Load File;"&--5
"F,PRGTAPCRT,Load;"& --2
"F,ROM,Load Kernal;"& --3
-- "F,T64,Load File;"&--6
"TH,Play/Stop TAP;"&
"OI,Tape sound,Off,On;"&
"OG,Disk Write,Enable,Disable;"&
"O2,Video standard,PAL,NTSC;"&
"O8A,Scandoubler Fx,None,HQ2x-320,HQ2x-160,CRT 25%,CRT 50%;"&
@@ -327,6 +327,7 @@ end component cartridge;
signal ces: std_logic_vector(3 downto 0);
signal iec_cycle: std_logic;
signal iec_cycleD: std_logic;
signal iec_cycle_rD: std_logic;
signal buttons: std_logic_vector(1 downto 0);
-- signals to connect "data_io" for direct PRG injection
@@ -494,7 +495,26 @@ end component cartridge;
signal audio_data_l : std_logic_vector(17 downto 0);
signal audio_data_r : std_logic_vector(17 downto 0);
signal audio_data_l_mix : std_logic_vector(17 downto 0);
signal cass_motor : std_logic;
signal cass_write : std_logic;
signal cass_sense : std_logic;
signal cass_do : std_logic;
signal tap_mem_ce : std_logic;
signal tap_play_addr : std_logic_vector(24 downto 0);
signal tap_last_addr : std_logic_vector(24 downto 0);
signal tap_in : std_logic_vector(7 downto 0);
signal tap_reset : std_logic;
signal tap_wrreq : std_logic;
signal tap_wrfull : std_logic;
signal tap_fifo_error : std_logic;
signal tap_loaded : std_logic;
signal tap_mode : std_logic;
signal tap_play : std_logic;
signal tap_play_btn: std_logic;
signal tap_play_btnD: std_logic;
signal reset_counter : integer;
signal reset_n : std_logic;
signal led_disk : std_logic;
@@ -511,8 +531,8 @@ end component cartridge;
signal mem_ce : std_logic;
begin
-- 1541 activity led
LED <= not ioctl_download and not led_disk;
-- 1541/tape activity led
LED <= not ioctl_download and not led_disk and cass_motor;
iec_cycle <= '1' when ces = "1011" else '0';
@@ -577,7 +597,7 @@ begin
ioctl_dout => ioctl_data
);
cart_loading <= '1' when ioctl_download = '1' and ioctl_index = 3 else '0';
cart_loading <= '1' when ioctl_download = '1' and ioctl_index = x"82" else '0';
cart : cartridge
port map (
@@ -632,12 +652,12 @@ begin
joyA_c64 <= joyB_int when status(3)='1' else joyA_int;
joyB_c64 <= joyA_int when status(3)='1' else joyB_int;
sdram_addr <= c64_addr_temp when iec_cycle='0' else ioctl_ram_addr;
sdram_addr <= c64_addr_temp when iec_cycle='0' else ioctl_ram_addr when ioctl_download = '1' else tap_play_addr;
sdram_data_out <= c64_data_out when iec_cycle='0' else ioctl_ram_data;
-- ram_we and ce are active low
sdram_ce <= mem_ce when iec_cycle='0' else ioctl_iec_cycle_used;
sdram_we <= not ram_we when iec_cycle='0' else ioctl_iec_cycle_used;
sdram_ce <= mem_ce when iec_cycle='0' else ioctl_iec_cycle_used or tap_mem_ce;
sdram_we <= not ram_we when iec_cycle='0' else ioctl_iec_cycle_used when ioctl_download = '1' else '0';
process(clk_c64)
begin
@@ -664,7 +684,7 @@ begin
end if;
if ioctl_wr='1' then
if ioctl_index = 2 then--prg
if ioctl_index = x"02" then--prg
if ioctl_addr = 0 then
ioctl_load_addr(7 downto 0) <= ioctl_data;
elsif(ioctl_addr = 1) then
@@ -674,7 +694,7 @@ begin
end if;
end if;
if ioctl_index = 3 then--CRT, e0(MAX)
if ioctl_index = x"82" then--CRT, e0(MAX)
if ioctl_addr = 0 then
ioctl_load_addr <= '0' & X"100000";
cart_blk_len <= (others => '0');
@@ -714,23 +734,28 @@ begin
ioctl_ram_wr <= '1';
end if;
end if;
if ioctl_index = 5 then
if ioctl_addr = 0 then
ioctl_load_addr <= '0' & X"200000";
ioctl_ram_data <= ioctl_data;
else
ioctl_ram_wr <= '1';
end if;
end if;
if ioctl_index = x"42" then -- TAP
if ioctl_addr = 0 then
ioctl_load_addr <= '0' & X"200000";
ioctl_ram_data <= ioctl_data;
else
ioctl_ram_wr <= '1';
end if;
end if;
end if;
if old_download /= ioctl_download and ioctl_index = 3 then
if old_download /= ioctl_download and ioctl_index = x"82" then
cart_attached <= old_download;
erase_cram <= '1';
end if;
if old_download /= ioctl_download and ioctl_index = x"42" then
tap_loaded <= old_download;
end if;
if status(5)='1' or buttons(1)='1' then
cart_attached <= '0';
end if;
@@ -754,7 +779,7 @@ begin
end if;
end process;
c64rom_wr <= ioctl_wr when (((ioctl_index = 0) and (ioctl_addr(14) = '0')) or (ioctl_index = 4)) and (ioctl_download = '1') else '0';
c64rom_wr <= ioctl_wr when (((ioctl_index = 0) and (ioctl_addr(14) = '0')) or (ioctl_index = 3)) and (ioctl_download = '1') else '0';
c64rom_addr <= ioctl_addr(13 downto 0) when ioctl_index = 0 else '1' & ioctl_addr(12 downto 0);
c1541rom_wr <= ioctl_wr when (ioctl_index = 0) and (ioctl_addr(14) = '1') and (ioctl_download = '1') else '0';
@@ -891,7 +916,7 @@ begin
reset_counter <= 1000000;
reset_n <= '0';
elsif buttons(1)='1' or status(5)='1' or reset_key = '1' or reset_crt='1' or
(ioctl_download='1' and (ioctl_index = 3 or ioctl_index = 4)) then
(ioctl_download='1' and (ioctl_index = 3 or ioctl_index = x"82")) then -- kernal or crt
reset_counter <= 255;
reset_n <= '0';
elsif ioctl_download ='1' then
@@ -935,16 +960,19 @@ begin
ce => sdram_ce
);
audio_data_l_mix <= audio_data_l when status(18) = '0' else
audio_data_l + (cass_do & "00000000000000");
-- (cass_do & "00000000000000000");
dac : sigma_delta_dac
port map (
clk => clk_c64,
ldatasum => audio_data_l(17 downto 3),
ldatasum => audio_data_l_mix(17 downto 3),
rdatasum => audio_data_r(17 downto 3),
aleft => AUDIO_L,
aright => AUDIO_R
);
fpga64 : entity work.fpga64_sid_iec
port map(
clk32 => clk_c64,
@@ -1009,6 +1037,12 @@ begin
todclk => todclk,
cia_mode => status(4),
disk_num => open,
cass_motor => cass_motor,
cass_write => cass_write,
cass_sense => cass_sense,
cass_do => cass_do,
c64rom_addr => c64rom_addr,
c64rom_data => ioctl_data,
c64rom_wr => c64rom_wr,
@@ -1153,6 +1187,64 @@ begin
led => led_disk
);
-- TAP playback controller
cass_sense <= not tap_play;
tap_play_btn <= status(17);
process(clk_c64, reset_n)
begin
if reset_n = '0' then
tap_play_addr <= '0' & X"200000";
tap_last_addr <= '0' & X"200000";
tap_play <= '0';
tap_reset <= '1';
tap_mem_ce <= '0';
elsif rising_edge(clk_c64) then
tap_reset <= '0';
if ioctl_download = '1' and ioctl_index = x"42" then
tap_play <= '0';
tap_play_addr <= '0' & X"200000";
tap_last_addr <= ioctl_load_addr;
tap_reset <= '1';
if ioctl_addr = x"00000C" and ioctl_wr = '1' then
tap_mode <= ioctl_data(0);
end if;
end if;
tap_play_btnD <= tap_play_btn;
if tap_loaded = '1' and tap_play_btnD = '0' and tap_play_btn = '1' then
tap_play <= not tap_play;
end if;
if tap_fifo_error = '1' or tap_play_addr = tap_last_addr then tap_play <= '0'; end if;
iec_cycle_rD <= iec_cycle;
tap_wrreq <= '0';
if iec_cycle = '0' and iec_cycle_rD = '1' and tap_play = '1' and tap_wrfull = '0' then
tap_play_addr <= tap_play_addr + 1;
tap_mem_ce <= '1';
end if;
if iec_cycle = '1' and iec_cycle_rD = '1' and tap_mem_ce = '1' then
tap_mem_ce <= '0';
tap_wrreq <= '1';
end if;
end if;
end process;
c1530 : entity work.c1530
port map(
clk32 => clk_c64,
restart_tape => tap_reset,
wav_mode => '0',
tap_mode1 => tap_mode,
host_tap_in => c64_data_in,
host_tap_wrreq => tap_wrreq,
tap_fifo_wrfull => tap_wrfull,
tap_fifo_error => tap_fifo_error,
play => not cass_motor and not tap_reset,
do => cass_do
);
comp_sync : entity work.composite_sync
port map(
clk32 => clk_c64,

190
cores/c64/rtl/tap_fifo.vhd Normal file
View File

@@ -0,0 +1,190 @@
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: tap_fifo.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY tap_fifo IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END tap_fifo;
ARCHITECTURE SYN OF tap_fifo IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wrreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
empty <= sub_wire0;
full <= sub_wire1;
q <= sub_wire2(7 DOWNTO 0);
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "Cyclone III",
lpm_numwords => 64,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => 8,
lpm_widthu => 6,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
aclr => aclr,
clock => clock,
data => data,
rdreq => rdreq,
wrreq => wrreq,
empty => sub_wire0,
full => sub_wire1,
q => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "64"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
-- Retrieval info: PRIVATE: Width NUMERIC "8"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL tap_fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL tap_fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL tap_fifo.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL tap_fifo.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL tap_fifo_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf