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Merge pull request #75 from gyurco/c64

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C64 T65+CIA fixes, stereo 8580
This commit is contained in:
gyurco
2019-02-06 23:38:40 +01:00
committed by GitHub
parent d5c781f37e 0b88f46b05
commit 7fb9a3ef70
10 changed files with 354 additions and 940 deletions
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4
cores/c64/C64_mist.sdc
View File

@@ -48,9 +48,9 @@ set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|cl
set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_multicycle_path -from {video_mixer:vmixer|scandoubler:scandoubler|Hq2x:Hq2x|*} -to {VGA_*[*]} -setup 4
set_multicycle_path -from {video_mixer:vmixer|scandoubler:scandoubler|Hq2x:Hq2x|*} -to {VGA_*[*]} -hold 4
set_multicycle_path -from {video_mixer:vmixer|scandoubler:scandoubler|Hq2x:Hq2x|*} -to {VGA_*[*]} -hold 3
set_multicycle_path -to {VGA_*[*]} -setup 3
set_multicycle_path -to {VGA_*[*]} -setup 4
set_multicycle_path -to {VGA_*[*]} -hold 3
set_false_path -to [get_ports {AUDIO_L}]

33
cores/c64/rtl/c1541/gcr_floppy.vhd
View File

@@ -158,14 +158,14 @@ with gcr_nibble_out select
X"D" when "11101",--"10111",
X"E" when "11110",--"01111",
X"F" when others; --"10101",
process (clk32)
variable bit_clk_cnt : std_logic_vector(7 downto 0) := (others => '0');
begin
if rising_edge(clk32) then
mode_r1 <= mode;
if (mode_r1 xor mode) = '1' then -- read <-> write change
bit_clk_cnt := (others => '0');
byte_n <= '1';
@@ -178,7 +178,7 @@ begin
else
bit_clk_cnt := bit_clk_cnt + '1';
end if;
byte_n <= '1';
if byte_in_n = '0' and mtr = '1' and ram_ready = '1' then
if bit_clk_cnt > X"10" then
@@ -187,9 +187,7 @@ begin
end if;
end if;
end if;
end if;
end if;
end process;
@@ -201,11 +199,11 @@ begin
if old_track /= track_num then
sector <= (others => '0'); --reset sector number on track change
else if bit_clk_en = '1' then
elsif bit_clk_en = '1' then
mode_r2 <= mode;
if mode = '1' then autorise_write <= '0'; end if;
if (mode xor mode_r2) = '1' then
if mode = '1' then -- leaving write mode
sync_in_n <= '0';
@@ -220,9 +218,9 @@ begin
data_cks <= (others => '0');
end if;
end if;
if sync_in_n = '0' and mode = '1' then
byte_cnt <= (others => '0');
nibble <= '0';
gcr_bit_cnt <= (others => '0');
@@ -230,18 +228,18 @@ begin
c1541_logic_din <= (others => '0');
gcr_byte <= (others => '0');
data_cks <= (others => '0');
if sync_cnt = X"31" then
sync_cnt <= (others => '0');
sync_in_n <= '1';
else
sync_cnt <= sync_cnt + '1';
end if;
end if;
if sync_in_n = '1' or mode = '0' then
gcr_bit_cnt <= gcr_bit_cnt + '1';
if gcr_bit_cnt = X"4" then
gcr_bit_cnt <= (others => '0');
@@ -292,17 +290,17 @@ begin
end if;
end if;
end if;
-- demux byte from floppy (ram)
gcr_byte <= gcr_byte(6 downto 0) & gcr_bit;
if bit_cnt = X"7" then
c1541_logic_din <= gcr_byte(6 downto 0) & gcr_bit;
end if;
-- serialise/convert byte to floppy (ram)
gcr_nibble_out <= gcr_nibble_out(3 downto 0) & gcr_bit_out;
if gcr_bit_cnt = X"0" then
if nibble = '0' then
ram_di(3 downto 0) <= nibble_out;
@@ -318,11 +316,10 @@ begin
else
ram_we <= '0';
end if;
end if;
end if;
end if;
end if;
end process;
end struct;

18
cores/c64/rtl/cpu_6510.vhd
View File

@@ -94,15 +94,17 @@ begin
end if;
end process;
process(ioDir, ioData, diIO)
process(clk)
begin
for i in 0 to 7 loop
if ioDir(i) = '0' then
currentIO(i) <= std_logic(diIO(i));
else
currentIO(i) <= ioData(i);
end if;
end loop;
if rising_edge(clk) then
for i in 0 to 7 loop
if ioDir(i) = '0' then
currentIO(i) <= std_logic(diIO(i));
else
currentIO(i) <= ioData(i);
end if;
end loop;
end if;
end process;
-- Cunnect zee wires

65
cores/c64/rtl/fpga64_sid_iec.vhd
View File

@@ -100,7 +100,7 @@ entity fpga64_sid_iec is
audio_data_l: out std_logic_vector(17 downto 0);
audio_data_r: out std_logic_vector(17 downto 0);
extfilter_en: in std_logic;
sid_mode : in std_logic_vector(1 downto 0);
sid_mode : in std_logic_vector(2 downto 0);
-- IEC
iec_data_o : out std_logic;
@@ -189,11 +189,13 @@ architecture rtl of fpga64_sid_iec is
-- SID signals
signal sid_do : std_logic_vector(7 downto 0);
signal sid_do6581 : std_logic_vector(7 downto 0);
signal sid_do8580 : std_logic_vector(7 downto 0);
signal sid_do8580_l : std_logic_vector(7 downto 0);
signal sid_do8580_r : std_logic_vector(7 downto 0);
signal second_sid_en: std_logic;
-- CIA signals
signal enableCia : std_logic;
signal enableCia_p : std_logic;
signal enableCia_n : std_logic;
signal cia1Do: unsigned(7 downto 0);
signal cia2Do: unsigned(7 downto 0);
@@ -268,7 +270,8 @@ architecture rtl of fpga64_sid_iec is
signal voice_r : signed(17 downto 0);
signal pot_x : std_logic_vector(7 downto 0);
signal pot_y : std_logic_vector(7 downto 0);
signal audio_8580 : std_logic_vector(15 downto 0);
signal audio_8580_l : std_logic_vector(15 downto 0);
signal audio_8580_r : std_logic_vector(15 downto 0);
component sid8580
port (
@@ -368,7 +371,8 @@ begin
begin
if rising_edge(clk32) then
enableVic <= '0';
enableCia <= '0';
enableCia_n <= '0';
enableCia_p <= '0';
enableCpu <= '0';
case sysCycle is
@@ -377,14 +381,16 @@ begin
when CYCLE_CPUE =>
enableVic <= '1';
enableCpu <= '1';
when CYCLE_CPUC =>
enableCia_n <= '1';
when CYCLE_CPUF =>
enableCia <= '1';
enableCia_p <= '1';
when others =>
null;
end case;
end if;
end process;
hSync <= vicHSync;
vSync <= vicVSync;
@@ -575,11 +581,14 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID)
end process;
audio_data_l <= std_logic_vector(voice_l) when sid_mode(1)='0' else
(audio_8580 & "00");
audio_data_r <= std_logic_vector(voice_l) when sid_mode="00" else
std_logic_vector(voice_r) when sid_mode="01" else
(audio_8580 & "00");
sid_do <= sid_do6581 when sid_mode(1)='0' else sid_do8580;
(audio_8580_l & "00");
audio_data_r <= std_logic_vector(voice_l) when sid_mode="000" else
std_logic_vector(voice_r) when sid_mode="001" else
(audio_8580_r & "00") when sid_mode="011" else
(audio_8580_l & "00");
sid_do <= sid_do6581 when sid_mode(1)='0' else
sid_do8580_l when second_sid_en='0' else
sid_do8580_r;
pot_x <= X"FF" when ((cia1_pao(7) and JoyA(5)) or (cia1_pao(6) and JoyB(5))) = '0' else X"00";
pot_y <= X"FF" when ((cia1_pao(7) and JoyA(6)) or (cia1_pao(6) and JoyB(6))) = '0' else X"00";
@@ -590,7 +599,7 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID)
sid_6581: entity work.sid_top
generic map (
g_num_voices => 16
g_num_voices => 11
)
port map (
clock => clk32,
@@ -614,19 +623,35 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID)
sample_right => voice_r
);
sid_8580 : sid8580
sid_8580_l : sid8580
port map (
reset => reset,
clk32 => clk32,
clk_1MHz => clk_1MHz(31),
cs => cs_sid,
cs => cs_sid and not second_sid_en,
we => pulseWrRam and phi0_cpu,
addr => std_logic_vector(cpuAddr(4 downto 0)),
data_in => std_logic_vector(cpuDo),
data_out => sid_do8580,
data_out => sid_do8580_l,
pot_x => pot_x,
pot_y => pot_y,
audio_data => audio_8580,
audio_data => audio_8580_l,
extfilter_en => extfilter_en
);
sid_8580_r : sid8580
port map (
reset => reset,
clk32 => clk32,
clk_1MHz => clk_1MHz(31),
cs => cs_sid and second_sid_en,
we => pulseWrRam and phi0_cpu,
addr => std_logic_vector(cpuAddr(4 downto 0)),
data_in => std_logic_vector(cpuDo),
data_out => sid_do8580_r,
pot_x => pot_x,
pot_y => pot_y,
audio_data => audio_8580_r,
extfilter_en => extfilter_en
);
@@ -637,7 +662,8 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID)
port map (
mode => cia_mode,
clk => clk32,
phi2 => enableCia,
phi2_p => enableCia_p,
phi2_n => enableCia_n,
res_n => not reset,
cs_n => not cs_cia1,
rw => not cpuWe,
@@ -664,7 +690,8 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID)
port map (
mode => cia_mode,
clk => clk32,
phi2 => enableCia,
phi2_p => enableCia_p,
phi2_n => enableCia_n,
res_n => not reset,
cs_n => not cs_cia2,
rw => not cpuWe,

8
cores/c64/rtl/mist/c64_mist.vhd
View File

@@ -128,10 +128,10 @@ constant CONF_STR : string :=
"F,CRT,Load Cartridge;" &--3
-- "F,TAP,Load File;"&--4
-- "F,T64,Load File;"&--5
"OF,Disk Write,Enable,Disable;"&
"OG,Disk Write,Enable,Disable;"&
"O2,Video standard,PAL,NTSC;"&
"O8A,Scandoubler Fx,None,HQ2x-320,HQ2x-160,CRT 25%,CRT 50%;"&
"ODE,SID,6581 Mono,6581 Stereo,8580;"&
"ODF,SID,6581 Mono,6581 Stereo,8580 Mono,8580 Stereo,Pseudo Stereo;"&
"O3,Joysticks,normal,swapped;"&
"O6,Audio filter,On,Off;"&
"O4,CIA Model,6256,8521;"&
@@ -838,7 +838,7 @@ begin
audio_data_l => audio_data_l,
audio_data_r => audio_data_r,
extfilter_en => not status(6),
sid_mode => status(14 downto 13),
sid_mode => status(15 downto 13),
iec_data_o => c64_iec_data_o,
iec_atn_o => c64_iec_atn_o,
iec_clk_o => c64_iec_clk_o,
@@ -854,7 +854,7 @@ begin
reset_key => reset_key
);
disk_readonly <= status(15);
disk_readonly <= status(16);
c64_iec_data_i <= c1541_iec_data_o;
c64_iec_clk_i <= c1541_iec_clk_o;

58
cores/c64/rtl/mos6526.v
View File

@@ -5,9 +5,10 @@
// TODO: check if Flag and Serial port interrupts are still working
module mos6526 (
input wire mode, // 0 - 6526 "old", 1 - 8521 "new"
input wire mode, // 0 - 6526 "old", 1 - 8521 "new"
input wire clk,
input wire phi2,
input wire phi2_p, // Phi 2 positive edge
input wire phi2_n, // Phi 2 negative edge
input wire res_n,
input wire cs_n,
input wire rw,
@@ -83,10 +84,13 @@ reg [ 2:0] cnt_pulsecnt;
reg int_reset;
wire rd = phi2_n & !cs_n & rw;
wire wr = phi2_n & !cs_n & !rw;
// Register Decoding
always @(posedge clk) begin
if (!res_n) db_out <= 8'h00;
else if (!cs_n && rw)
else if (rd)
case (rs)
4'h0: db_out <= pa_in;
4'h1: db_out <= pb_in;
@@ -113,7 +117,7 @@ always @(posedge clk) begin
pra <= 8'h00;
ddra <= 8'h00;
end
else if (!cs_n && !rw)
else if (wr)
case (rs)
4'h0: pra <= db_in;
4'h2: ddra <= db_in;
@@ -122,7 +126,7 @@ always @(posedge clk) begin
ddra <= ddra;
end
endcase
if (phi2) pa_out <= pra | ~ddra;
if (phi2_p) pa_out <= pra | ~ddra;
end
// Port B Output
@@ -131,7 +135,7 @@ always @(posedge clk) begin
prb <= 8'h00;
ddrb <= 8'h00;
end
else if (!cs_n && !rw)
else if (wr)
case (rs)
4'h1: prb <= db_in;
4'h3: ddrb <= db_in;
@@ -140,7 +144,7 @@ always @(posedge clk) begin
ddrb <= ddrb;
end
endcase
if (phi2) begin
if (phi2_p) begin
pb_out[7] <= crb[1] ? (crb[2] ? timerBff ^ timerBoverflow : timerBoverflow) : prb[7] | ~ddrb[7];
pb_out[6] <= cra[1] ? (cra[2] ? timerAff ^ timerAoverflow : timerAoverflow) : prb[6] | ~ddrb[6];
pb_out[5:0] <= prb[5:0] | ~ddrb[5:0];
@@ -151,13 +155,13 @@ end
always @(posedge clk) begin
if (!res_n || int_reset) icr[4] <= 1'b0;
else if (!flag_n && flag_n_prev) icr[4] <= 1'b1;
if (phi2) flag_n_prev <= flag_n;
if (phi2_p) flag_n_prev <= flag_n;
end
// Port Control Output
always @(posedge clk) begin
if (!cs_n && rs == 4'h1) pc_n <= 1'b0;
else pc_n <= phi2 ? 1'b1 : pc_n;
else pc_n <= phi2_p ? 1'b1 : pc_n;
end
// Timer A
@@ -178,7 +182,7 @@ always @(posedge clk) begin
icr[0] <= 1'b0;
end
else begin
if (phi2) begin
if (phi2_p) begin
if (int_reset) icr[0] <= 0;
countA0 <= cnt_in && ~cnt_in_prev;
countA1 <= countA0;
@@ -205,7 +209,7 @@ always @(posedge clk) begin
end
end
if (!cs_n && !rw)
if (wr)
case (rs)
4'h4: ta_lo <= db_in;
4'h5:
@@ -244,7 +248,7 @@ always @(posedge clk) begin
icr[1] <= 1'b0;
end
else begin
if (phi2) begin
if (phi2_p) begin
if (int_reset) icr[1] <= 0;
countB0 <= cnt_in && ~cnt_in_prev;
countB1 <= countB0;
@@ -271,7 +275,7 @@ always @(posedge clk) begin
end
end
if (!cs_n && !rw)
if (wr)
case (rs)
4'h6: tb_lo <= db_in;
4'h7:
@@ -305,13 +309,13 @@ always @(posedge clk) begin
tod_latched <= 1'b0;
icr[2] <= 1'b0;
end
else if (!cs_n && rw)
else if (rd)
case (rs)
4'h8: tod_latched <= 1'b0;
4'hb: tod_latched <= 1'b1;
default: tod_latched <= tod_latched;
endcase
else if (!cs_n && !rw)
else if (wr)
case (rs)
4'h8: if (crb[7]) tod_alarm[3:0] <= db_in[3:0];
else begin
@@ -377,7 +381,7 @@ always @(posedge clk) begin
end
else tod_count <= 3'h0;
if (phi2) begin
if (phi2_p) begin
if (!tod_latched) tod_latch <= {tod_hr, tod_min, tod_sec, tod_10ths};
if ({tod_hr, tod_min, tod_sec, tod_10ths} == tod_alarm) begin
tod_alarm_reg <= 1'b1;
@@ -400,7 +404,7 @@ always @(posedge clk) begin
icr[3] <= 1'b0;
end
else begin
if (!cs_n && !rw)
if (wr)
case (rs)
4'hc:
begin
@@ -409,7 +413,7 @@ always @(posedge clk) begin
end
endcase
if (phi2) begin
if (phi2_p) begin
if (int_reset) icr[3] <= 1'b0;
if (!cra[6]) begin // input
@@ -450,7 +454,7 @@ always @(posedge clk) begin
cnt_out_prev <= 1'b1;
cnt_pulsecnt <= 3'h0;
end
else if (phi2) begin
else if (phi2_p) begin
cnt_in_prev <= cnt_in;
cnt_out_prev <= cnt_out;
@@ -474,19 +478,17 @@ always @(posedge clk) begin
int_reset <= 0;
end
else begin
if (!cs_n && !rw)
case (rs)
4'hd: imr_reg <= db_in;
endcase
if (wr && rs == 4'hd) imr_reg <= db_in;
if (rd && rs == 4'hd) int_reset <= 1;
int_reset <= 0;
if (!cs_n && rw && rs == 4'hd) int_reset <= 1;
if (phi2 | mode) begin
if (phi2_p | mode) begin
imr <= imr_reg[7] ? imr | imr_reg[4:0] : imr & ~imr_reg[4:0];
irq_n <= irq_n ? ~|(imr & icr) : irq_n;
end
if (phi2 & int_reset) irq_n <= 1;
if (phi2_p & int_reset) begin
irq_n <= 1;
int_reset <= 0;
end
end
end

3
cores/c64/rtl/mos6526.vhd
View File

@@ -6,7 +6,8 @@ component mos6526
PORT (
mode : in std_logic; -- '0' - 6256, '1' - 8521
clk : in std_logic;
phi2 : in std_logic;
phi2_p : in std_logic;
phi2_n : in std_logic;
res_n : in std_logic;
cs_n : in std_logic;
rw : in std_logic; -- '1' - read, '0' - write

14
cores/c64/rtl/sid/sid_regs.vhd
View File

@@ -98,7 +98,7 @@ architecture gideon of sid_regs is
signal sust_rel : byte_array_t(0 to 15) := (others => (others => '0'));
signal do_write : std_logic;
signal wdata_d : std_logic_vector(7 downto 0);
signal last_write : std_logic_vector(7 downto 0);
signal bus_value: std_logic_vector(7 downto 0);
signal filt_en_i: std_logic_vector(15 downto 0) := (others => '0');
constant address_remap : byte_array_t(0 to 255) := (
@@ -160,7 +160,7 @@ begin
wdata_d <= wdata;
if do_write='0' and wren='1' then
last_write <= wdata_d;
bus_value <= wdata_d;
if address(3)='0' then -- Voice register
case address(2 downto 0) is
when "000" => freq_lo(to_integer(address(7 downto 4))) <= wdata_d;
@@ -207,11 +207,11 @@ begin
-- Readback (unmapped address)
case addr is
when "00011001" => rdata <= potx;
when "00011010" => rdata <= poty;
when "00011011" => rdata <= osc3;
when "00011100" => rdata <= env3;
when others => rdata <= last_write;
when "00011001" => rdata <= potx; bus_value <= potx;
when "00011010" => rdata <= poty; bus_value <= poty;
when "00011011" => rdata <= osc3; bus_value <= osc3;
when "00011100" => rdata <= env3; bus_value <= env3;
when others => rdata <= bus_value;
end case;
if reset='1' then

1089
cores/c64/rtl/sid8580/sid_voice.v
View File

File diff suppressed because it is too large Load Diff

2
cores/c64/rtl/t65/T65.vhd
View File

@@ -511,8 +511,8 @@ begin
DL <= (others => '0');
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
NMI_entered <= '0';
if (really_rdy = '1') then
NMI_entered <= '0';
BusA_r <= BusA;
BusB <= DI;