Small Viking, MIDI and Ethernec fixes

cores/mist/io_fifo.v

@@ -1,93 +0,0 @@
-//
-// io_fifo.v
-// 
-// Atari ST(E) io controller FIFO for the MiST board
-// http://code.google.com/p/mist-board/
-// 
-// Copyright (c) 2013 Till Harbaum <till@harbaum.org> 
-// Modified by Juan Carlos González Amestoy.
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-module io_fifo #(
- parameter DATA_WIDTH = 8,
- parameter DEPTH = 4
-)(
-	input reset,
-	
-	input [DATA_WIDTH-1:0] in,
-	input in_clk,
-	input in_strobe,
-	input in_enable,
-	
-	input out_clk,
-	output [DATA_WIDTH-1:0] out,
-	input out_strobe,
-	input out_enable,
-
-	output empty,
-	output data_available,
-	output full
-);
-
-localparam FIFO_ADDR_BITS = DEPTH;
-localparam FIFO_DEPTH = (1 << FIFO_ADDR_BITS);
-
-reg [DATA_WIDTH-1:0] fifo [FIFO_DEPTH-1:0];
-reg [FIFO_ADDR_BITS-1:0] writeP, readP;
-
-assign full = (readP == (writeP + 1));
-assign empty = (readP == writeP);
-assign data_available = (readP != writeP);
-
-// the strobes may not be in the right clock domain, so bring them into the 
-// local clock domain
-reg in_strobeD, in_strobeD2;
-reg out_strobeD, out_strobeD2;
-
-// present current value. If fifo is empty show last value
-assign out = data_available?fifo[readP]:fifo[readP-1];
-
-always @(posedge out_clk) begin
-	// bring strobes in local clock domain
-	out_strobeD <= out_strobe;
-	out_strobeD2 <= out_strobeD;
-	
-	if(reset)
-		readP <= 0;
-	else begin
-		// rising edge on fifo read strobe from io controller
-		if((out_strobeD && !out_strobeD2) || out_enable)
-			readP <= readP + 1;
-	end
-end
-
-always @(posedge in_clk) begin
-	// bring strobes in local clock domain
-	in_strobeD <= in_strobe;
-	in_strobeD2 <= in_strobeD;
-	
-	if(reset)
-		writeP <= 0;
-	else begin
-		// rising edge on strobe signal causes write
-		// or in_enable being true
-		if((in_strobeD && !in_strobeD2) || in_enable) begin
-			fifo[writeP] <= in;
-			writeP <= writeP + 1;
-		end
-	end
-end	
-
-endmodule

cores/mist/mfp.v

@@ -1,3 +1,22 @@
+// mfp.v
+//
+// Atari ST multi function peripheral (MFP) for the MiST board
+// http://code.google.com/p/mist-board/
+//
+// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
 module mfp (
@@ -309,7 +328,15 @@ always @(negedge clk) begin
 
 		// input port irqs are edge sensitive
 		if(!iD[3] && iD2[3] && ier[ 3]) ipr[ 3] <= 1'b1;   // blitter
-      if(!iD[4] && iD2[4] && ier[ 6]) ipr[ 6] <= 1'b1;   // acia
+		
+		// HACK WARNING:
+		// The acia irq handling is somewhat broken. It should be edge sensitive like
+		// all others (and a real mfp can't do different). But this causes the
+		// acia irq to get stuck in cubase. Making it level sensitive cures this.
+		// But this is obviously not the correct solution ...
+//      if(!iD[4] && iD2[4] && ier[ 6]) ipr[ 6] <= 1'b1;   // edge sensitive acia
+      if(!i[4] && ier[ 6]) ipr[ 6] <= 1'b1;   // level sensitive acia
+		
 		if(!iD[5] && iD2[5] && ier[ 7]) ipr[ 7] <= 1'b1;   // dma
 		if(!iD[7] && iD2[7] && ier[15]) ipr[15] <= 1'b1;   // mono detect
 

cores/mist/mist_top.v

@@ -222,18 +222,23 @@ wire viking_mem_ok = MEM512K || MEM1M || MEM2M || MEM4M || MEM8M;
 wire viking_enable    = system_ctrl[28] && viking_mem_ok;
 
 // check for cpu access to 0xcxxxxx with viking enabled to switch video
-// output once the driver loads
-reg viking_in_use;
+// output once the driver loads. 256 accesses to the viking memory range
+// are considered a valid sign that the driver is working. Without driver
+// others may also probe that area which is why we want to see 256 accesses
+reg [7:0] viking_in_use;
+
 always @(negedge clk_128) begin
-	if(reset)
-		viking_in_use <= 1'b0;
+	if(peripheral_reset)
+		viking_in_use <= 8'h00;
 	else
-		if(clkena && viking_enable && (tg68_adr[23:18] == 6'b110000))
-			viking_in_use <= 1'b1;
+		// cpu writes to $c0xxxx
+		if(clkena && !br && (tg68_busstate == 2'b11) && viking_enable && 
+			(tg68_adr[23:18] == 6'b110000) && (viking_in_use != 8'hff))
+			viking_in_use <= viking_in_use + 8'h01;
 end
 
 // video output multiplexer to switch between shifter and viking
-wire viking_active = viking_in_use && !osd_enable;
+wire viking_active = (viking_in_use == 8'hff) && !osd_enable;
 assign VGA_HS = viking_active?viking_hs:shifter_hs;
 assign VGA_VS = viking_active?viking_vs:shifter_vs;
 assign VGA_R = viking_active?viking_r:shifter_r;
@@ -247,7 +252,6 @@ wire [22:0] viking_address;
 wire viking_read;
 
 viking viking (
-	.reset        	(reset    	),
 	.pclk         	(clk_128    ),    // pixel 
 	.bus_cycle   	(bus_cycle  ),
 	
@@ -778,9 +782,14 @@ wire [2:0]  tg68_fc_S;
 wire        tg68_uds_S;
 wire        tg68_lds_S;
 wire        tg68_rw_S;
+
 reg         tg68_as;
 reg         cpu_fast_cycle;  // signal indicating that the cpu runs from cache, used to calm berr
 
+// the tg68 can itself generate a reset signal
+wire tg68_reset;  
+wire peripheral_reset = reset || !tg68_reset;
+
 // the CPU throttle counter limits the CPU speed to a rate the tg68 core can
 // handle. With a throttle of "4" the core will run effectively at 32MHz which
 // is equivalent to ~64MHz on a real 68000. This speed will never be achieved 
@@ -908,6 +917,7 @@ wire [1:0] tg68_busstate;
 wire [15:0] cache_data_out = data_cache_hit?data_cache_data_out:inst_cache_data_out;
 wire [15:0] cpu_data_in = cacheRead?cache_data_out:system_data_out;
 
+
 TG68KdotC_Kernel #(2,2,2,2,2,2) tg68k (
 	.clk          	(clk_128 		),
 	.nReset       	(~reset			),
@@ -924,7 +934,7 @@ TG68KdotC_Kernel #(2,2,2,2,2,2) tg68k (
 	.nLDS          (tg68_lds_S    ),
 	.nWr           (tg68_rw_S     ),
 	.busstate	 	(tg68_busstate ), // 00-> fetch code 10->read data 11->write data 01->no memaccess
-	.nResetOut	   (              ),
+	.nResetOut	   (tg68_reset    ),
 	.FC            (tg68_fc_S     )
 );
 

cores/mist/viking.v

@@ -25,7 +25,6 @@
 // it on screen.
 
 module viking (
-		input 				reset,
 	   input 				pclk,     	// 128 MHz pixel clock
 
 		// memory interface