ACSI and ikbd improvements

cores/mist/data_io.v

@@ -4,7 +4,7 @@ module data_io (
 	input clk_8,
 	input reset,
 	input [1:0] bus_cycle,
-	output reg [15:0] ctrl_out,
+	output reg [31:0] ctrl_out,
  
 	// spi interface
 	input sdi,
@@ -17,11 +17,6 @@ module data_io (
 	input [7:0] dma_data,
 	output reg dma_ack,
 
-	// acsi data interface
-	input acsi_out_available,
-	output reg acsi_out_strobe,
-	input [9:0] acsi_out_data,
-	
 	// ram interface
 	output reg [2:0] state, // state bits required to drive the sdram host
 	output [22:0] addr,
@@ -87,19 +82,6 @@ always@(negedge sck) begin
 		else
 			txData[15:1] <= txData[14:0];
 	end
-	
-	// acsi daza read
-	// send alternating "data available flag + address" and "data"
-	if(cmd == 7) begin
-	   if(cnt == 8) begin
-			txData[15:8] <= { 5'd0, acsi_out_data[9:8], acsi_out_available };
-			acsi_out_strobe <= 1'b0;
-	   end else if(cnt == 16) begin
-			txData[15:8] <= acsi_out_data[7:0];
-			acsi_out_strobe <= 1'b1;
-		end else
-			txData[15:1] <= txData[14:0];
-	end
 end
 
 always@(posedge sck, posedge ss) begin
@@ -165,9 +147,13 @@ always@(posedge sck, posedge ss) begin
 				end				
 			end
 
-			// set control register
-			if((cmd == 4) && (cnt == 5'd23))
-				ctrl_out <= { sbuf, sdi };
+			// set control register (32 bits written in 2 * 16 bits)
+			if((cmd == 4) && (cnt == 5'd23)) begin
+			        if(bcnt < 2)
+			                ctrl_out[31:16] <= { sbuf, sdi };
+		                else
+			                ctrl_out[15:0] <= { sbuf, sdi };
+			end
 		end
 	end
 end

cores/mist/dma.v

@@ -16,17 +16,13 @@ module dma (
 	
 	// input from system config
 	input fdc_wr_prot,
+	input [7:0] acsi_enable,
 	
 	// connection to data_io (arm controller spi interface)
 	input [4:0] dio_idx,
 	output reg [7:0] dio_data,
 	input dio_ack,
 	
-	// interface to fifo for acsi commands
-   output acsi_data_out_available,
-   input acsi_strobe_out,
-   output [9:0] acsi_data_out,  // 2 bit a0/a1 + 8 bit data
-	
 	// input from psg
 	input drv_side,
 	input [1:0] drv_sel
@@ -147,27 +143,6 @@ always @(sel, rw, addr, mode, base, fdc_data, fdc_sector, fdc_status, fdc_track,
    end
 end
 
-// -------------- fifo to send acsi data to io controller -------------
-assign acsi_data_out_available = (readPout != writePout);
-assign acsi_data_out = fifoOut[readPout];
-
-localparam FIFO_ADDR_BITS = 8;
-localparam FIFO_DEPTH = (1 << FIFO_ADDR_BITS);
-reg [9:0] fifoOut [FIFO_DEPTH-1:0];
-reg [FIFO_ADDR_BITS-1:0] writePout, readPout;
-
-reg acsi_strobe_outD, acsi_strobe_outD2;
-always @(posedge clk) begin
-	acsi_strobe_outD <= acsi_strobe_out;
-	acsi_strobe_outD2 <= acsi_strobe_outD;
-
-	if(reset)
-		readPout <= 0;
-	else
-		if(acsi_strobe_outD && !acsi_strobe_outD2)
-			readPout <= readPout + 8'd1;
-end
-
 // --------------- acsi handling --------------------
 reg [2:0] acsi_target;
 reg [4:0] acsi_cmd;
@@ -194,7 +169,6 @@ always @(negedge clk) begin
 		scnt <= 8'h00;
 		fdc_busy <= 2'd0;
 		motor_on <= 16'd0;
-		writePout <= 0;
 		fdc_irq <= 1'b0;
 		acsi_target <= 3'd0;
 		acsi_cmd <= 5'd0;
@@ -281,12 +255,16 @@ always @(negedge clk) begin
 						end
 
 						// ------------- TYPE II commands -------------
-						if(din[7:5] == 3'b100)         // read sector
+						if(din[7:5] == 3'b100) begin         // read sector
+							br <= 1'b1;         // request bus
 							fdc_busy <= 2'd3;
+						end
 							
 						if(din[7:5] == 3'b101)         // write sector
-							if(!fdc_wr_prot)
+							if(!fdc_wr_prot) begin
+							   br <= 1'b1;         // request bus
 								fdc_busy <= 2'd3;
+							end
 
 						// ------------- TYPE III commands ------------
 	
@@ -319,16 +297,16 @@ always @(negedge clk) begin
 						acsi_cmd <= din[4:0];
 						acsi_byte_counter <= 3'd0;
 
-						// only acsi 0 is supported
-						if(din[7:5] == 3'd0)
+						// check if this acsi device is enabled
+						if(acsi_enable[din[7:5]] == 1'b1)
 							acsi_irq <= 1'b1;
 					end else begin
 						// further bytes
 						acsi_cmd_parms[acsi_byte_counter] <= din[7:0];
 						acsi_byte_counter <= acsi_byte_counter + 3'd1;
 						
-						// only acsi 0 is supported
-						if(acsi_target == 3'd0) begin
+						// check if this acsi device is enabled
+						if(acsi_enable[acsi_target] == 1'b1) begin
 							// auto-ack first 5 bytes
 							if(acsi_byte_counter < 4)
 								acsi_irq <= 1'b1;
@@ -338,10 +316,6 @@ always @(negedge clk) begin
 							end
 						end
 					end
-	
-					// acsi: write data in output buffer
-					fifoOut[writePout] <= { mode[2:1], din[7:0] };
-					writePout <= writePout + 8'd1;
 				end
 			end
 			

cores/mist/mist_top.v

@@ -141,7 +141,7 @@ wire vreg_sel = io_sel && ({tg68_adr[15:7], 7'd0} == 16'h8200);
 wire [15:0] vreg_data_out;
 
 // mfp 8 bit interface at $fffa00 - $fffa3f
-wire mfp_sel  = io_sel && ({tg68_adr[15:8], 8'd0} == 16'hfa00);
+wire mfp_sel  = io_sel && ({tg68_adr[15:6], 6'd0} == 16'hfa00);
 wire [7:0] mfp_data_out;
 
 // acia 8 bit interface at $fffc00 - $fffc07
@@ -318,11 +318,6 @@ wire [7:0 ]dma_dio_data;
 // floppy_sel is active low
 wire wr_prot = (floppy_sel == 2'b01)?system_ctrl[7]:system_ctrl[6];
 
-// acsi interface
-wire data_from_acsi_available;
-wire strobe_from_acsi;
-wire [9:0] data_from_acsi;
-
 dma dma (
 	// cpu interface
 	.clk      (clk_8       ),
@@ -340,17 +335,13 @@ dma dma (
 
 	// system control interface
 	.fdc_wr_prot (wr_prot),
+	.acsi_enable (system_ctrl[17:10]),
 	
 	// data_io (arm controller imterface)
 	.dio_idx  (dma_dio_idx ),
 	.dio_data (dma_dio_data),
 	.dio_ack  (dma_dio_ack ),
 
-	// acsi interface
-	.acsi_data_out_available 	(data_from_acsi_available),
-	.acsi_strobe_out 				(strobe_from_acsi),
-	.acsi_data_out 	   		(data_from_acsi),
-
 	// floppy interface
 	.drv_sel  (floppy_sel  ),
 	.drv_side (floppy_side )
@@ -652,7 +643,7 @@ wire user_io_sdo;
 assign SPI_DO = (CONF_DATA0 == 1'b0)?user_io_sdo:
 	((SPI_SS2 == 1'b0)?data_io_sdo:1'bZ);
 
-wire [15:0] system_ctrl;
+wire [31:0] system_ctrl;
 
 // connection to transfer ikbd data from io controller to acia
 wire [7:0] ikbd_data_to_acia;
@@ -709,11 +700,6 @@ data_io data_io (
 		.dma_data   (dma_dio_data  ),
 		.dma_ack    (dma_dio_ack   ),
 
-		// acsi interface
-		.acsi_out_available  (data_from_acsi_available	),
-		.acsi_out_strobe		(strobe_from_acsi				),
-		.acsi_out_data			(data_from_acsi				),
-
 		// ram interface
 		.state 	 	(host_state		),
 		.addr		 	(host_addr		),

cores/mist/video.v

@@ -301,7 +301,7 @@ wire [9:0] v_offset = mono?10'd0:10'd2;
 wire de = (hcnt >= H_PRE) && (hcnt < H_ACT+H_PRE) && (vcnt >= v_offset && vcnt < V_ACT+v_offset);
 
 // a fake de signal for timer a for color modes with half the hsync frequency
-wire deC = (((hcnt >= H_PRE) && !vcnt[0]) || ((hcnt < H_ACT+H_PRE) && vcnt[0])) && 
+wire deC = (((hcnt >= H_PRE) && !vcnt[0]) || ((hcnt < H_ACT+H_PRE-10'd96) && vcnt[0])) && 
 	(vcnt >= (v_offset-10'd0) && vcnt < (V_ACT+v_offset-10'd0));
 
 // a fake hsync pulse for the scan doubled color modes