Merge pull request #81 from gyurco/archie

Archie updates
2026-02-06 08:04:41 +00:00 · 2019-02-24 00:24:15 +01:00
parent 14643d1ac1 d95c05a143
commit 98b213bb26
24 changed files with 3248 additions and 339 deletions
--- a/cores/archie/fpga/mist/archimedes_mist_top.qsf
+++ b/cores/archie/fpga/mist/archimedes_mist_top.qsf
@@ -136,7 +136,7 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
 set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_*

 set_global_assignment -name ENABLE_SIGNALTAP OFF
-set_global_assignment -name USE_SIGNALTAP_FILE signal_tap.stp
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/vidc.stp
 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
 set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
 set_global_assignment -name ENABLE_NCE_PIN OFF
@@ -161,7 +161,7 @@ set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
 set_location_assignment PIN_7 -to LED
 set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
 set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
 set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
 set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
 set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
@@ -172,6 +172,10 @@ set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
 set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
 set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
 set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[*]
+set_global_assignment -name SEED 2
+set_global_assignment -name ENABLE_DRC_SETTINGS OFF
 set_global_assignment -name VERILOG_FILE archimedes_mist_top.v
 set_global_assignment -name SYSTEMVERILOG_FILE rgb2ypbpr.sv
 set_global_assignment -name VERILOG_FILE sigma_delta_dac.v
@@ -218,6 +222,11 @@ set_global_assignment -name VERILOG_FILE ../../rtl/amber/a23_alu.v
 set_global_assignment -name VERILOG_FILE ../../rtl/archimedes_top.v
 set_global_assignment -name VERILOG_FILE ../../rtl/sdram/sdram_top.v
 set_global_assignment -name VERILOG_FILE ../../rtl/sdram/sdram_init.v
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*]
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[*]
+set_global_assignment -name QIP_FILE rom_reconfig_24.qip
+set_global_assignment -name QIP_FILE rom_reconfig_25.qip
+set_global_assignment -name QIP_FILE pll_reconfig.qip
+set_location_assignment PLL_1 -to CLOCKS|altpll_component|auto_generated|pll1
+set_global_assignment -name QIP_FILE rom_reconfig_36.qip
+set_global_assignment -name QIP_FILE pll_vidc.qip
+set_global_assignment -name SIGNALTAP_FILE output_files/vidc.stp
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
--- a/cores/archie/fpga/mist/archimedes_mist_top.sdc
+++ b/cores/archie/fpga/mist/archimedes_mist_top.sdc
@@ -75,16 +75,16 @@ set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1
 set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[3]}] -max 1.5 [get_ports DRAM_CLK]
 set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[3]}] -min -0.8 [get_ports DRAM_CLK]

-set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[2]}] -max 0 [get_ports {VGA_*}]
-set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[2]}] -min -5 [get_ports {VGA_*}]
+set_output_delay -clock [get_clocks {CLOCKS_VIDC|altpll_component|auto_generated|pll1|clk[0]}] -max 0 [get_ports {VGA_*}]
+set_output_delay -clock [get_clocks {CLOCKS_VIDC|altpll_component|auto_generated|pll1|clk[0]}] -min -5 [get_ports {VGA_*}]

 #**************************************************************
 # Set Clock Groups
 #**************************************************************

 set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {CLOCKS|*}]
-set_clock_groups -asynchronous -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[2]}]
-set_clock_groups -asynchronous -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[2]}]
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {CLOCKS_VIDC|*}]
+set_clock_groups -asynchronous -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -group [get_clocks {CLOCKS_VIDC|altpll_component|auto_generated|pll1|clk[0]}]

 #**************************************************************
 # Set False Path
@@ -103,8 +103,8 @@ set_false_path -to [get_ports {LED}]
 set_multicycle_path -from [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -setup 4
 set_multicycle_path -from [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -hold 3

-set_multicycle_path -to {VGA_*[*]} -setup 2
-set_multicycle_path -to {VGA_*[*]} -hold 1
+set_multicycle_path -to {VGA_*[*]} -setup 4
+set_multicycle_path -to {VGA_*[*]} -hold 3

 #**************************************************************
 # Set Maximum Delay
--- a/cores/archie/fpga/mist/archimedes_mist_top.v
+++ b/cores/archie/fpga/mist/archimedes_mist_top.v
@@ -65,14 +65,14 @@ wire [7:0] kbd_in_data;
 wire kbd_in_strobe;

 // generated clocks
-wire clk_pix = clk_50m;
+wire clk_pix;
 wire ce_pix;
 wire clk_32m /* synthesis keep */ ;
 wire clk_128m /* synthesis keep */ ;
-wire clk_50m /* synthesis keep */ ;
 //wire clk_8m  /* synthesis keep */ ;

 wire pll_ready;
+wire pll_vidc_ready;
 wire ram_ready;

 // core's raw video 
@@ -97,6 +97,7 @@ wire [7:0] joyA;
 wire [7:0] joyB;
 wire [1:0] buttons;
 wire [1:0] switches;
+wire       scandoubler_disable;
 wire       ypbpr;

 // the top file should generate the correct clocks for the machine
@@ -104,12 +105,134 @@ wire       ypbpr;
 clockgen CLOCKS(
 	.inclk0	(CLOCK_27[0]),
 	.c0		(clk_32m),
-	.c1		(clk_128m), 
-	.c2 	(clk_50m),
+	.c1		(clk_128m),
+//	.c2     (clk_50m),
 	.c3		(DRAM_CLK),
 	.locked	(pll_ready)  // pll locked output
 );

+pll_vidc CLOCKS_VIDC(
+	.inclk0	(CLOCK_27[0]),
+	.c0		(clk_pix),
+	.areset(pll_areset),
+	.scanclk(pll_scanclk),
+	.scandata(pll_scandata),
+	.scanclkena(pll_scanclkena),
+	.configupdate(pll_configupdate),
+	.scandataout(pll_scandataout),
+	.scandone(pll_scandone),
+	.locked	(pll_vidc_ready)  // pll locked output
+);
+
+wire       pll_reconfig_busy;
+wire       pll_areset;
+wire       pll_configupdate;
+wire       pll_scanclk;
+wire       pll_scanclkena;
+wire       pll_scandata;
+wire       pll_scandataout;
+wire       pll_scandone;
+reg        pll_reconfig_reset;
+wire [7:0] pll_rom_address;
+wire       pll_rom_q;
+reg        pll_write_from_rom;
+wire       pll_write_rom_ena;
+reg        pll_reconfig;
+wire       q_reconfig_25;
+wire       q_reconfig_24;
+wire       q_reconfig_36;
+
+rom_reconfig_25 rom_reconfig_25
+(
+	.address(pll_rom_address),
+	.clock(CLOCK_27[0]),
+	.rden(pll_write_rom_ena),
+	.q(q_reconfig_25)
+);
+
+rom_reconfig_24 rom_reconfig_24
+(
+	.address(pll_rom_address),
+	.clock(CLOCK_27[0]),
+	.rden(pll_write_rom_ena),
+	.q(q_reconfig_24)
+);
+
+rom_reconfig_36 rom_reconfig_36
+(
+	.address(pll_rom_address),
+	.clock(CLOCK_27[0]),
+	.rden(pll_write_rom_ena),
+	.q(q_reconfig_36)
+);
+
+assign pll_rom_q = pixbaseclk_select == 2'b01 ? q_reconfig_25 :
+                   pixbaseclk_select == 2'b10 ? q_reconfig_36 : q_reconfig_24;
+
+pll_reconfig pll_reconfig_inst
+(
+    .busy(pll_reconfig_busy),
+    .clock(CLOCK_27[0]),
+    .counter_param(0),
+    .counter_type(0),
+    .data_in(0),
+    .pll_areset(pll_areset),
+    .pll_areset_in(0),
+    .pll_configupdate(pll_configupdate),
+    .pll_scanclk(pll_scanclk),
+    .pll_scanclkena(pll_scanclkena),
+    .pll_scandata(pll_scandata),
+    .pll_scandataout(pll_scandataout),
+    .pll_scandone(pll_scandone),
+    .read_param(0),
+    .reconfig(pll_reconfig),
+    .reset(pll_reconfig_reset),
+    .reset_rom_address(0),
+    .rom_address_out(pll_rom_address),
+    .rom_data_in(pll_rom_q),
+    .write_from_rom(pll_write_from_rom),
+    .write_param(0),
+    .write_rom_ena(pll_write_rom_ena)
+);
+
+always @(posedge CLOCK_27[0]) begin
+    reg [1:0] pixbaseclk_select_d;
+    reg [1:0] pll_reconfig_state = 0;
+    reg [9:0] pll_reconfig_timeout;
+
+    pll_write_from_rom <= 0;
+    pll_reconfig <= 0;
+    pll_reconfig_reset <= 0;
+    case (pll_reconfig_state)
+    2'b00:
+    begin
+        pixbaseclk_select_d <= pixbaseclk_select;
+        if (pixbaseclk_select_d != pixbaseclk_select) begin
+            pll_write_from_rom <= 1;
+            pll_reconfig_state <= 2'b01;
+        end
+    end
+    2'b01: pll_reconfig_state <= 2'b10;
+    2'b10:
+        if (~pll_reconfig_busy) begin
+            pll_reconfig <= 1;
+            pll_reconfig_state <= 2'b11;
+            pll_reconfig_timeout <= 10'd1000;
+        end
+    2'b11:
+    begin
+        pll_reconfig_timeout <= pll_reconfig_timeout - 1'd1;
+        if (pll_reconfig_timeout == 10'd1) begin
+            // pll_reconfig stuck in busy state
+            pll_reconfig_reset <= 1;
+            pll_reconfig_state <= 2'b00;
+        end
+        if (~pll_reconfig & ~pll_reconfig_busy) pll_reconfig_state <= 2'b00;
+    end
+    default: ;
+    endcase
+end
+
 wire [5:0] osd_r_o, osd_g_o, osd_b_o;

 osd #(0,0,4) OSD (
@@ -147,8 +270,9 @@ assign VGA_R = ypbpr?Pr:osd_r_o;
 assign VGA_G = ypbpr? Y:osd_g_o;
 assign VGA_B = ypbpr?Pb:osd_b_o;
 wire   CSync = ~(core_hs ^ core_vs);
-assign VGA_HS = ypbpr ? CSync : core_hs;
-assign VGA_VS = ypbpr? 1'b1 : core_vs;
+//24 MHz modes get composite sync automatically
+assign VGA_HS = ((pixbaseclk_select[0] == pixbaseclk_select[1]) | ypbpr) ? CSync : core_hs;
+assign VGA_VS = ((pixbaseclk_select[0] == pixbaseclk_select[1]) | ypbpr) ? 1'b1 : core_vs;

 // de-multiplex spi outputs from user_io and data_io
 assign SPI_DO = (CONF_DATA0==0)?user_io_sdo:(SPI_SS2==0)?data_io_sdo:1'bZ;
@@ -162,12 +286,13 @@ user_io user_io(
   .SPI_MISO      (user_io_sdo           ),   // tristate handling inside user_io
   .SPI_MOSI      (SPI_DI           ),

-   .SWITCHES      (switches         ),
-   .BUTTONS       (buttons          ),
-   .ypbpr         (ypbpr            ),
+	.SWITCHES      (switches         ),
+	.BUTTONS       (buttons          ),
+	.scandoubler_disable(scandoubler_disable),
+	.ypbpr         (ypbpr            ),

-   .JOY0          (joyA             ),
-   .JOY1          (joyB             ),
+	.JOY0          (joyA             ),
+	.JOY1          (joyB             ),

 	.kbd_out_data   ( kbd_out_data   ),
 	.kbd_out_strobe ( kbd_out_strobe ),
--- a/cores/archie/fpga/mist/clockgen.ppf
+++ b/cores/archie/fpga/mist/clockgen.ppf
@@ -2,10 +2,10 @@
 <!DOCTYPE pinplan>
 <pinplan intended_family="Cyclone III" variation_name="clockgen" megafunction_name="ALTPLL" specifies="all_ports">
 <global>
+<pin name="areset" direction="input" scope="external"  />
 <pin name="inclk0" direction="input" scope="external" source="clock"  />
 <pin name="c0" direction="output" scope="external" source="clock"  />
 <pin name="c1" direction="output" scope="external" source="clock"  />
-<pin name="c2" direction="output" scope="external" source="clock"  />
 <pin name="c3" direction="output" scope="external" source="clock"  />
 <pin name="locked" direction="output" scope="external"  />

--- a/cores/archie/fpga/mist/clockgen.qip
+++ b/cores/archie/fpga/mist/clockgen.qip
@@ -1,5 +1,4 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
 set_global_assignment -name IP_TOOL_VERSION "13.1"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clockgen.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clockgen_bb.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clockgen.ppf"]
--- a/cores/archie/fpga/mist/clockgen.v
+++ b/cores/archie/fpga/mist/clockgen.v
@@ -37,24 +37,30 @@
 `timescale 1 ps / 1 ps
 // synopsys translate_on
 module clockgen (
+	areset,
 	inclk0,
 	c0,
 	c1,
-	c2,
 	c3,
 	locked);

+	input	  areset;
 	input	  inclk0;
 	output	  c0;
 	output	  c1;
-	output	  c2;
 	output	  c3;
 	output	  locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif

 	wire [4:0] sub_wire0;
 	wire  sub_wire3;
-	wire [0:0] sub_wire8 = 1'h0;
-	wire [2:2] sub_wire5 = sub_wire0[2:2];
+	wire [0:0] sub_wire7 = 1'h0;
 	wire [0:0] sub_wire4 = sub_wire0[0:0];
 	wire [3:3] sub_wire2 = sub_wire0[3:3];
 	wire [1:1] sub_wire1 = sub_wire0[1:1];
@@ -62,16 +68,15 @@ module clockgen (
 	wire  c3 = sub_wire2;
 	wire  locked = sub_wire3;
 	wire  c0 = sub_wire4;
-	wire  c2 = sub_wire5;
-	wire  sub_wire6 = inclk0;
-	wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
+	wire  sub_wire5 = inclk0;
+	wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};

 	altpll	altpll_component (
-				.inclk (sub_wire7),
+				.areset (areset),
+				.inclk (sub_wire6),
 				.clk (sub_wire0),
 				.locked (sub_wire3),
 				.activeclock (),
-				.areset (1'b0),
 				.clkbad (),
 				.clkena ({6{1'b1}}),
 				.clkloss (),
@@ -105,7 +110,7 @@ module clockgen (
 				.vcooverrange (),
 				.vcounderrange ());
 	defparam
-		altpll_component.bandwidth_type = "LOW",
+		altpll_component.bandwidth_type = "AUTO",
 		altpll_component.clk0_divide_by = 27,
 		altpll_component.clk0_duty_cycle = 50,
 		altpll_component.clk0_multiply_by = 32,
@@ -114,14 +119,10 @@ module clockgen (
 		altpll_component.clk1_duty_cycle = 50,
 		altpll_component.clk1_multiply_by = 128,
 		altpll_component.clk1_phase_shift = "0",
-		altpll_component.clk2_divide_by = 90,
-		altpll_component.clk2_duty_cycle = 50,
-		altpll_component.clk2_multiply_by = 167,
-		altpll_component.clk2_phase_shift = "0",
 		altpll_component.clk3_divide_by = 27,
 		altpll_component.clk3_duty_cycle = 50,
 		altpll_component.clk3_multiply_by = 128,
-		altpll_component.clk3_phase_shift = "-3700",
+		altpll_component.clk3_phase_shift = "-1845",
 		altpll_component.compensate_clock = "CLK0",
 		altpll_component.inclk0_input_frequency = 37037,
 		altpll_component.intended_device_family = "Cyclone III",
@@ -130,7 +131,7 @@ module clockgen (
 		altpll_component.operation_mode = "NORMAL",
 		altpll_component.pll_type = "AUTO",
 		altpll_component.port_activeclock = "PORT_UNUSED",
-		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_USED",
 		altpll_component.port_clkbad0 = "PORT_UNUSED",
 		altpll_component.port_clkbad1 = "PORT_UNUSED",
 		altpll_component.port_clkloss = "PORT_UNUSED",
@@ -156,7 +157,7 @@ module clockgen (
 		altpll_component.port_scanwrite = "PORT_UNUSED",
 		altpll_component.port_clk0 = "PORT_USED",
 		altpll_component.port_clk1 = "PORT_USED",
-		altpll_component.port_clk2 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
 		altpll_component.port_clk3 = "PORT_USED",
 		altpll_component.port_clk4 = "PORT_UNUSED",
 		altpll_component.port_clk5 = "PORT_UNUSED",
@@ -184,8 +185,8 @@ endmodule
 // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
 // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
 // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
 // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
 // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
@@ -197,15 +198,12 @@ endmodule
 // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
 // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
 // Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "128.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "50.099998"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "128.000000"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
@@ -228,43 +226,35 @@ endmodule
 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
 // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 // Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
 // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
 // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
 // Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "128.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "50.10000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "128.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-3700.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-1844.61000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
 // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
 // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
 // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
@@ -273,7 +263,6 @@ endmodule
 // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
 // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
 // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clockgen.mif"
 // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
 // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
@@ -286,23 +275,20 @@ endmodule
 // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
 // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
 // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
 // Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
 // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 // Retrieval info: PRIVATE: USE_CLK0 STRING "1"
 // Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
 // Retrieval info: PRIVATE: USE_CLK3 STRING "1"
 // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
 // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
 // Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
 // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
 // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32"
@@ -311,14 +297,10 @@ endmodule
 // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "128"
 // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "90"
-// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "167"
-// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "27"
 // Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "128"
-// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-3700"
+// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-1845"
 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -326,7 +308,7 @@ endmodule
 // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
 // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
 // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
@@ -352,7 +334,7 @@ endmodule
 // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
@@ -369,17 +351,17 @@ endmodule
 // Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
 // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
 // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
 // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
 // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
 // Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
 // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
 // Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
 // Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.v TRUE
@@ -388,6 +370,7 @@ endmodule
 // Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.cmp FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.bsf FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL clockgen_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.mif FALSE
 // Retrieval info: LIB_FILE: altera_mf
 // Retrieval info: CBX_MODULE_PREFIX: ON
--- a/cores/archie/fpga/mist/data_io.v
+++ b/cores/archie/fpga/mist/data_io.v
@@ -30,15 +30,15 @@ module data_io #(parameter ADDR_WIDTH=24, START_ADDR = 0) (
 	input 			    sdi,
 	output reg 		    sdo,

-	output 			    downloading, // signal indicating an active download
+	output reg downloading, // signal indicating an active download
 	output [ADDR_WIDTH-1:0]     size, // number of bytes in input buffer

-        // additional signals for floppy emulation
+	// additional signals for floppy emulation
 	input [31:0] 		    fdc_status_out,
 	output reg [31:0] 	    fdc_status_in,
 	output reg 		    fdc_data_in_strobe,
-	output [7:0] 		    fdc_data_in,
-							   
+	output reg [7:0] 	    fdc_data_in,
+
 	// external ram interface
 	input 			    clk,
 	output reg 		    wr,
@@ -47,12 +47,6 @@ module data_io #(parameter ADDR_WIDTH=24, START_ADDR = 0) (
 	output [31:0] 		    d
 );

-// filter spi clock. the 8 bit gate delay is ~2.5ns in total
-wire [7:0] spi_sck_D = { spi_sck_D[6:0], sck } /* synthesis keep */;
-wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff);
-
-assign fdc_data_in = { sbuf, sdi };
-   
 (*KEEP="TRUE"*)assign sel = a[1:0] == 	2'b00 ? 4'b0001 :
 								a[1:0] == 	2'b01 ? 4'b0010 :
 								a[1:0] == 	2'b10 ? 4'b0100 : 4'b1000;
@@ -69,11 +63,10 @@ assign size = addr - START_ADDR;
 reg [6:0]      sbuf;
 reg [7:0]      cmd;
 reg [7:0]      data;
-reg [4:0]      cnt;
+reg [2:0]      bit_cnt;
 reg [2:0]      byte_cnt;

 reg [ADDR_WIDTH-1:0] addr;
-reg rclk;

 localparam UIO_FILE_TX         = 8'h53;
 localparam UIO_FILE_TX_DAT     = 8'h54;
@@ -81,92 +74,127 @@ localparam UIO_FDC_GET_STATUS  = 8'h55;
 localparam UIO_FDC_TX_DATA     = 8'h56;
 localparam UIO_FDC_SET_STATUS  = 8'h57;

-assign downloading = downloading_reg;
-reg downloading_reg = 1'b0;
-
 // data_io has its own SPI interface to the io controller
-always@(posedge spi_sck, posedge ss) begin
-	if(ss == 1'b1) begin
-		cnt <= 5'd0;
-		byte_cnt <= 3'd0;
-		fdc_data_in_strobe <= 1'b0;
+
+// SPI bit and byte counters
+always@(posedge sck or posedge ss) begin
+	if(ss == 1) begin
+		bit_cnt <= 0;
+		byte_cnt <= 0;
+		cmd <= 0;
 	end else begin
-		rclk <= 1'b0;
-		fdc_data_in_strobe <= 1'b0;
-
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15)
-			sbuf <= { sbuf[5:0], sdi};
-
-		// increase target address after write
-		if(rclk)
-			addr <= addr + 1;
-	 
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) 	
-			cnt <= cnt + 4'd1;
-		else begin	
-			cnt <= 5'd8;
-			if(byte_cnt != 7)
-				byte_cnt <= byte_cnt + 3'd1;
+		if((&bit_cnt)&&(~&byte_cnt)) begin
+			byte_cnt <= byte_cnt + 1'd1;
+			if (!byte_cnt) cmd <= {sbuf, sdi};
 		end
-		
-		// finished command byte
-      if(cnt == 7)
-			cmd <= {sbuf, sdi};
+		bit_cnt <= bit_cnt + 1'd1;
+	end
+end

-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare
-			if(sdi) begin
-				addr <= START_ADDR;
-				downloading_reg <= 1'b1; 
-			end else
-				downloading_reg <= 1'b0; 
-		end
-		
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			data <= {sbuf, sdi};
-			rclk <= 1'b1;
-			a <= addr;
-		end
-		
-		// command 0x56: UIO_FDC_TX_DATA
-		if((cmd == UIO_FDC_TX_DATA) && (cnt == 15))
-			fdc_data_in_strobe <= 1'b1;
-	   
-		// command 0x57: UIO_FDC_SET_STATUS
-		if((cmd == UIO_FDC_SET_STATUS) && (cnt == 15)) begin
-		   if(byte_cnt == 0) fdc_status_in[31:24] <= { sbuf, sdi};
-		   if(byte_cnt == 1) fdc_status_in[23:16] <= { sbuf, sdi};
-		   if(byte_cnt == 2) fdc_status_in[15:8]  <= { sbuf, sdi};
-		   if(byte_cnt == 3) fdc_status_in[7:0]   <= { sbuf, sdi};
+always@(negedge sck or posedge ss) begin
+	if(ss == 1) begin
+		sdo <= 1'bZ;
+	end else begin
+		if(cmd == UIO_FDC_GET_STATUS)
+			sdo <= fdc_status_out[{4-byte_cnt,~bit_cnt}];
+		else
+			sdo <= 1'b0;
+	end
+end
+
+// SPI receiver IO -> FPGA
+
+reg       spi_receiver_strobe_r = 0;
+reg       spi_transfer_end_r = 1;
+reg [7:0] spi_byte_in;
+
+// Read at spi_sck clock domain, assemble bytes for transferring to clk_sys
+always@(posedge sck or posedge ss) begin
+
+	if(ss == 1) begin
+		spi_transfer_end_r <= 1;
+	end else begin
+		spi_transfer_end_r <= 0;
+
+		if(&bit_cnt) begin
+			// finished reading a byte, prepare to transfer to clk_sys
+			spi_byte_in <= { sbuf, sdi};
+			spi_receiver_strobe_r <= ~spi_receiver_strobe_r;
+		end else
+			sbuf[6:0] <= { sbuf[5:0], sdi };
+	end
+end
+
+// Process bytes from SPI at the clk_sys domain
+always @(posedge clk) begin
+
+	reg       spi_receiver_strobe;
+	reg       spi_transfer_end;
+	reg       spi_receiver_strobeD;
+	reg       spi_transfer_endD;
+	reg [7:0] acmd;
+	reg [3:0] abyte_cnt;   // counts bytes
+
+	fdc_data_in_strobe <= 0;
+	wr <= 0;
+
+	//synchronize between SPI and sys clock domains
+	spi_receiver_strobeD <= spi_receiver_strobe_r;
+	spi_receiver_strobe <= spi_receiver_strobeD;
+	spi_transfer_endD       <= spi_transfer_end_r;
+	spi_transfer_end        <= spi_transfer_endD;
+
+	// strobe is set whenever a valid byte has been received
+	if (~spi_transfer_endD & spi_transfer_end) begin
+		abyte_cnt <= 8'd0;
+	end else if (spi_receiver_strobeD ^ spi_receiver_strobe) begin
+
+		if(~&abyte_cnt)
+			abyte_cnt <= abyte_cnt + 8'd1;
+
+		if(!abyte_cnt) begin
+			acmd <= spi_byte_in;
+		end else begin
+			case(acmd)
+			UIO_FILE_TX:
+			begin
+				// prepare 
+				if(spi_byte_in) begin
+					addr <= START_ADDR;
+					downloading <= 1; 
+				end else begin
+					a <= addr;
+					downloading <= 0;
+				end
+			end
+
+			// transfer
+			UIO_FILE_TX_DAT:
+			begin
+				a <= addr;
+				addr <= addr + 1'd1;
+				data <= spi_byte_in;
+				wr <= 1;
+			end
+
+			// command 0x56: UIO_FDC_TX_DATA
+			UIO_FDC_TX_DATA:
+			begin
+				fdc_data_in_strobe <= 1'b1;
+				fdc_data_in <= spi_byte_in;
+			end
+
+			// command 0x57: UIO_FDC_SET_STATUS
+			UIO_FDC_SET_STATUS:
+			begin
+				if (abyte_cnt == 1) fdc_status_in[31:24] <= spi_byte_in;
+				if (abyte_cnt == 2) fdc_status_in[23:16] <= spi_byte_in;
+				if (abyte_cnt == 3) fdc_status_in[15: 8] <= spi_byte_in;
+				if (abyte_cnt == 4) fdc_status_in[ 7: 0] <= spi_byte_in;
+			end
+			endcase
 		end
 	end
 end
-   
-always@(negedge spi_sck or posedge ss) begin
-   if(ss == 1) begin
-      sdo <= 1'bZ;
-   end else begin
-		if(cmd == UIO_FDC_GET_STATUS)
-			sdo <= fdc_status_out[{~byte_cnt[1:0],~(cnt[2:0])}];
-		else
-			sdo <= 1'b0;
-   end
-end
-
-reg rclkD, rclkD2;
-always@(posedge clk) begin
-	// bring rclk from spi clock domain into core clock domain
-	rclkD <= rclk;
-	rclkD2 <= rclkD;
-	wr <= 1'b0;
-	
-	if(rclkD && !rclkD2) 
-		wr <= 1'b1;
-end

 endmodule
--- a/cores/archie/fpga/mist/pll_reconfig.qip
+++ b/cores/archie/fpga/mist/pll_reconfig.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_reconfig.v"]
--- a/cores/archie/fpga/mist/pll_reconfig.v
+++ b/cores/archie/fpga/mist/pll_reconfig.v
--- a/cores/archie/fpga/mist/pll_vidc.ppf
+++ b/cores/archie/fpga/mist/pll_vidc.ppf
@@ -0,0 +1,17 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll_vidc" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="configupdate" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="scanclk" direction="input" scope="external" source="clock"  />
+<pin name="scanclkena" direction="input" scope="external"  />
+<pin name="scandata" direction="input" scope="external"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+<pin name="scandataout" direction="output" scope="external"  />
+<pin name="scandone" direction="output" scope="external"  />
+
+</global>
+</pinplan>
--- a/cores/archie/fpga/mist/pll_vidc.qip
+++ b/cores/archie/fpga/mist/pll_vidc.qip
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_vidc.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_vidc.ppf"]
--- a/cores/archie/fpga/mist/clockgen_bb.v
+++ b/cores/archie/fpga/mist/clockgen_bb.v
@@ -1,10 +1,10 @@
-// megafunction wizard: %ALTPLL%VBB%
+// megafunction wizard: %ALTPLL%
 // GENERATION: STANDARD
 // VERSION: WM1.0
 // MODULE: altpll 

 // ============================================================
-// File Name: clockgen.v
+// File Name: pll_vidc.v
 // Megafunction Name(s):
 // 			altpll
 //
@@ -17,6 +17,7 @@
 // 13.1.4 Build 182 03/12/2014 SJ Web Edition
 // ************************************************************

+
 //Copyright (C) 1991-2014 Altera Corporation
 //Your use of Altera Corporation's design tools, logic functions 
 //and other software and tools, and its AMPP partner logic 
@@ -31,20 +32,152 @@
 //Altera or its authorized distributors.  Please refer to the 
 //applicable agreement for further details.

-module clockgen (
-	inclk0,
-	c0,
-	c1,
-	c2,
-	c3,
-	locked);

+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll_vidc (
+	areset,
+	configupdate,
+	inclk0,
+	scanclk,
+	scanclkena,
+	scandata,
+	c0,
+	locked,
+	scandataout,
+	scandone);
+
+	input	  areset;
+	input	  configupdate;
 	input	  inclk0;
+	input	  scanclk;
+	input	  scanclkena;
+	input	  scandata;
 	output	  c0;
-	output	  c1;
-	output	  c2;
-	output	  c3;
 	output	  locked;
+	output	  scandataout;
+	output	  scandone;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  areset;
+	tri0	  configupdate;
+	tri0	  scanclkena;
+	tri0	  scandata;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [4:0] sub_wire0;
+	wire  sub_wire2;
+	wire  sub_wire3;
+	wire  sub_wire4;
+	wire [0:0] sub_wire7 = 1'h0;
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  scandataout = sub_wire2;
+	wire  scandone = sub_wire3;
+	wire  locked = sub_wire4;
+	wire  sub_wire5 = inclk0;
+	wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
+
+	altpll	altpll_component (
+				.areset (areset),
+				.configupdate (configupdate),
+				.inclk (sub_wire6),
+				.scanclk (scanclk),
+				.scanclkena (scanclkena),
+				.scandata (scandata),
+				.clk (sub_wire0),
+				.scandataout (sub_wire2),
+				.scandone (sub_wire3),
+				.locked (sub_wire4),
+				.activeclock (),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "LOW",
+		altpll_component.clk0_divide_by = 3,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 8,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 37037,
+		altpll_component.intended_device_family = "Cyclone III",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_vidc",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_USED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_USED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_USED",
+		altpll_component.port_scanclkena = "PORT_USED",
+		altpll_component.port_scandata = "PORT_USED",
+		altpll_component.port_scandataout = "PORT_USED",
+		altpll_component.port_scandone = "PORT_USED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_UNUSED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.self_reset_on_loss_lock = "ON",
+		altpll_component.width_clock = 5,
+		altpll_component.scan_chain_mif_file = "pll_vidc_36.mif";
+

 endmodule

@@ -66,19 +199,10 @@ endmodule
 // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
 // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "128.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "50.099998"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "128.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "72.000000"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -99,44 +223,20 @@ endmodule
 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
 // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
 // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "128.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "50.10000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "128.00000000"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "72.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-3700.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
 // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
 // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
 // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
@@ -145,8 +245,8 @@ endmodule
 // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
 // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
 // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clockgen.mif"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_vidc_36.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
 // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
 // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
@@ -155,55 +255,34 @@ endmodule
 // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
 // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
 // Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
 // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
 // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 // Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
 // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
 // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
 // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
-// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "128"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "90"
-// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "167"
-// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "27"
-// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "128"
-// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-3700"
 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
 // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
 // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
@@ -215,17 +294,17 @@ endmodule
 // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
@@ -240,26 +319,40 @@ endmodule
 // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
 // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: CONSTANT: scan_chain_mif_file STRING "pll_vidc_36.mif"
 // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
 // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+// Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate"
 // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
+// Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena"
+// Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
+// Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
+// Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
+// Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
+// Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen_bb.v TRUE
+// Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
+// Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc.mif FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL .mif FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc_24.mif TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc_25.mif TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_vidc_36.mif TRUE
 // Retrieval info: LIB_FILE: altera_mf
 // Retrieval info: CBX_MODULE_PREFIX: ON
--- a/cores/archie/fpga/mist/pll_vidc_24.mif
+++ b/cores/archie/fpga/mist/pll_vidc_24.mif
@@ -0,0 +1,174 @@
+-- Copyright (C) 1991-2014 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- MIF file representing initial state of PLL Scan Chain
+--    Device Family: Cyclone III
+--    Device Part: -
+--    Device Speed Grade: 8
+--    PLL Scan Chain: Fast PLL (144 bits)
+--    File Name: /home/gyuri/git/mist-board/cores/archie/fpga/mist/pll_vidc_24.mif
+--    Generated: Fri Feb 22 22:07:56 2019
+
+WIDTH=1;
+DEPTH=144;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+	0    :   0; -- Reserved Bits = 0 (1 bit(s))
+	1    :   0; -- Reserved Bits = 0 (1 bit(s))
+	2    :   0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
+	3    :   0;
+	4    :   1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27)
+	5    :   1;
+	6    :   0;
+	7    :   1;
+	8    :   1;
+	9    :   0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
+	10   :   0; -- Reserved Bits = 0 (5 bit(s))
+	11   :   0;
+	12   :   0;
+	13   :   0;
+	14   :   0;
+	15   :   0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
+	16   :   0;
+	17   :   1;
+	18   :   1; -- N counter: Bypass = 1 (1 bit(s))
+	19   :   0; -- N counter: High Count = 0 (8 bit(s))
+	20   :   0;
+	21   :   0;
+	22   :   0;
+	23   :   0;
+	24   :   0;
+	25   :   0;
+	26   :   0;
+	27   :   0; -- N counter: Odd Division = 0 (1 bit(s))
+	28   :   0; -- N counter: Low Count = 0 (8 bit(s))
+	29   :   0;
+	30   :   0;
+	31   :   0;
+	32   :   0;
+	33   :   0;
+	34   :   0;
+	35   :   0;
+	36   :   0; -- M counter: Bypass = 0 (1 bit(s))
+	37   :   0; -- M counter: High Count = 8 (8 bit(s))
+	38   :   0;
+	39   :   0;
+	40   :   0;
+	41   :   1;
+	42   :   0;
+	43   :   0;
+	44   :   0;
+	45   :   0; -- M counter: Odd Division = 0 (1 bit(s))
+	46   :   0; -- M counter: Low Count = 8 (8 bit(s))
+	47   :   0;
+	48   :   0;
+	49   :   0;
+	50   :   1;
+	51   :   0;
+	52   :   0;
+	53   :   0;
+	54   :   0; -- clk0 counter: Bypass = 0 (1 bit(s))
+	55   :   0; -- clk0 counter: High Count = 5 (8 bit(s))
+	56   :   0;
+	57   :   0;
+	58   :   0;
+	59   :   0;
+	60   :   1;
+	61   :   0;
+	62   :   1;
+	63   :   1; -- clk0 counter: Odd Division = 1 (1 bit(s))
+	64   :   0; -- clk0 counter: Low Count = 4 (8 bit(s))
+	65   :   0;
+	66   :   0;
+	67   :   0;
+	68   :   0;
+	69   :   1;
+	70   :   0;
+	71   :   0;
+	72   :   1; -- clk1 counter: Bypass = 1 (1 bit(s))
+	73   :   0; -- clk1 counter: High Count = 0 (8 bit(s))
+	74   :   0;
+	75   :   0;
+	76   :   0;
+	77   :   0;
+	78   :   0;
+	79   :   0;
+	80   :   0;
+	81   :   0; -- clk1 counter: Odd Division = 0 (1 bit(s))
+	82   :   0; -- clk1 counter: Low Count = 0 (8 bit(s))
+	83   :   0;
+	84   :   0;
+	85   :   0;
+	86   :   0;
+	87   :   0;
+	88   :   0;
+	89   :   0;
+	90   :   1; -- clk2 counter: Bypass = 1 (1 bit(s))
+	91   :   0; -- clk2 counter: High Count = 0 (8 bit(s))
+	92   :   0;
+	93   :   0;
+	94   :   0;
+	95   :   0;
+	96   :   0;
+	97   :   0;
+	98   :   0;
+	99   :   0; -- clk2 counter: Odd Division = 0 (1 bit(s))
+	100  :   0; -- clk2 counter: Low Count = 0 (8 bit(s))
+	101  :   0;
+	102  :   0;
+	103  :   0;
+	104  :   0;
+	105  :   0;
+	106  :   0;
+	107  :   0;
+	108  :   1; -- clk3 counter: Bypass = 1 (1 bit(s))
+	109  :   0; -- clk3 counter: High Count = 0 (8 bit(s))
+	110  :   0;
+	111  :   0;
+	112  :   0;
+	113  :   0;
+	114  :   0;
+	115  :   0;
+	116  :   0;
+	117  :   0; -- clk3 counter: Odd Division = 0 (1 bit(s))
+	118  :   0; -- clk3 counter: Low Count = 0 (8 bit(s))
+	119  :   0;
+	120  :   0;
+	121  :   0;
+	122  :   0;
+	123  :   0;
+	124  :   0;
+	125  :   0;
+	126  :   1; -- clk4 counter: Bypass = 1 (1 bit(s))
+	127  :   0; -- clk4 counter: High Count = 0 (8 bit(s))
+	128  :   0;
+	129  :   0;
+	130  :   0;
+	131  :   0;
+	132  :   0;
+	133  :   0;
+	134  :   0;
+	135  :   0; -- clk4 counter: Odd Division = 0 (1 bit(s))
+	136  :   0; -- clk4 counter: Low Count = 0 (8 bit(s))
+	137  :   0;
+	138  :   0;
+	139  :   0;
+	140  :   0;
+	141  :   0;
+	142  :   0;
+	143  :   0;
+END;
--- a/cores/archie/fpga/mist/pll_vidc_25.mif
+++ b/cores/archie/fpga/mist/pll_vidc_25.mif
@@ -0,0 +1,174 @@
+-- Copyright (C) 1991-2014 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- MIF file representing initial state of PLL Scan Chain
+--    Device Family: Cyclone III
+--    Device Part: -
+--    Device Speed Grade: 8
+--    PLL Scan Chain: Fast PLL (144 bits)
+--    File Name: /home/gyuri/git/mist-board/cores/archie/fpga/mist/pll_vidc_25.mif
+--    Generated: Sat Feb 23 00:00:38 2019
+
+WIDTH=1;
+DEPTH=144;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+	0    :   0; -- Reserved Bits = 0 (1 bit(s))
+	1    :   0; -- Reserved Bits = 0 (1 bit(s))
+	2    :   0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
+	3    :   0;
+	4    :   0; -- Loop Filter Resistance = 8 (5 bit(s)) (Setting 8)
+	5    :   1;
+	6    :   0;
+	7    :   0;
+	8    :   0;
+	9    :   0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
+	10   :   0; -- Reserved Bits = 0 (5 bit(s))
+	11   :   0;
+	12   :   0;
+	13   :   0;
+	14   :   0;
+	15   :   0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
+	16   :   0;
+	17   :   1;
+	18   :   0; -- N counter: Bypass = 0 (1 bit(s))
+	19   :   0; -- N counter: High Count = 3 (8 bit(s))
+	20   :   0;
+	21   :   0;
+	22   :   0;
+	23   :   0;
+	24   :   0;
+	25   :   1;
+	26   :   1;
+	27   :   1; -- N counter: Odd Division = 1 (1 bit(s))
+	28   :   0; -- N counter: Low Count = 2 (8 bit(s))
+	29   :   0;
+	30   :   0;
+	31   :   0;
+	32   :   0;
+	33   :   0;
+	34   :   1;
+	35   :   0;
+	36   :   0; -- M counter: Bypass = 0 (1 bit(s))
+	37   :   0; -- M counter: High Count = 56 (8 bit(s))
+	38   :   0;
+	39   :   1;
+	40   :   1;
+	41   :   1;
+	42   :   0;
+	43   :   0;
+	44   :   0;
+	45   :   0; -- M counter: Odd Division = 0 (1 bit(s))
+	46   :   0; -- M counter: Low Count = 56 (8 bit(s))
+	47   :   0;
+	48   :   1;
+	49   :   1;
+	50   :   1;
+	51   :   0;
+	52   :   0;
+	53   :   0;
+	54   :   0; -- clk0 counter: Bypass = 0 (1 bit(s))
+	55   :   0; -- clk0 counter: High Count = 6 (8 bit(s))
+	56   :   0;
+	57   :   0;
+	58   :   0;
+	59   :   0;
+	60   :   1;
+	61   :   1;
+	62   :   0;
+	63   :   0; -- clk0 counter: Odd Division = 0 (1 bit(s))
+	64   :   0; -- clk0 counter: Low Count = 6 (8 bit(s))
+	65   :   0;
+	66   :   0;
+	67   :   0;
+	68   :   0;
+	69   :   1;
+	70   :   1;
+	71   :   0;
+	72   :   1; -- clk1 counter: Bypass = 1 (1 bit(s))
+	73   :   0; -- clk1 counter: High Count = 0 (8 bit(s))
+	74   :   0;
+	75   :   0;
+	76   :   0;
+	77   :   0;
+	78   :   0;
+	79   :   0;
+	80   :   0;
+	81   :   0; -- clk1 counter: Odd Division = 0 (1 bit(s))
+	82   :   0; -- clk1 counter: Low Count = 0 (8 bit(s))
+	83   :   0;
+	84   :   0;
+	85   :   0;
+	86   :   0;
+	87   :   0;
+	88   :   0;
+	89   :   0;
+	90   :   1; -- clk2 counter: Bypass = 1 (1 bit(s))
+	91   :   0; -- clk2 counter: High Count = 0 (8 bit(s))
+	92   :   0;
+	93   :   0;
+	94   :   0;
+	95   :   0;
+	96   :   0;
+	97   :   0;
+	98   :   0;
+	99   :   0; -- clk2 counter: Odd Division = 0 (1 bit(s))
+	100  :   0; -- clk2 counter: Low Count = 0 (8 bit(s))
+	101  :   0;
+	102  :   0;
+	103  :   0;
+	104  :   0;
+	105  :   0;
+	106  :   0;
+	107  :   0;
+	108  :   1; -- clk3 counter: Bypass = 1 (1 bit(s))
+	109  :   0; -- clk3 counter: High Count = 0 (8 bit(s))
+	110  :   0;
+	111  :   0;
+	112  :   0;
+	113  :   0;
+	114  :   0;
+	115  :   0;
+	116  :   0;
+	117  :   0; -- clk3 counter: Odd Division = 0 (1 bit(s))
+	118  :   0; -- clk3 counter: Low Count = 0 (8 bit(s))
+	119  :   0;
+	120  :   0;
+	121  :   0;
+	122  :   0;
+	123  :   0;
+	124  :   0;
+	125  :   0;
+	126  :   1; -- clk4 counter: Bypass = 1 (1 bit(s))
+	127  :   0; -- clk4 counter: High Count = 0 (8 bit(s))
+	128  :   0;
+	129  :   0;
+	130  :   0;
+	131  :   0;
+	132  :   0;
+	133  :   0;
+	134  :   0;
+	135  :   0; -- clk4 counter: Odd Division = 0 (1 bit(s))
+	136  :   0; -- clk4 counter: Low Count = 0 (8 bit(s))
+	137  :   0;
+	138  :   0;
+	139  :   0;
+	140  :   0;
+	141  :   0;
+	142  :   0;
+	143  :   0;
+END;
--- a/cores/archie/fpga/mist/pll_vidc_36.mif
+++ b/cores/archie/fpga/mist/pll_vidc_36.mif
@@ -0,0 +1,174 @@
+-- Copyright (C) 1991-2014 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- MIF file representing initial state of PLL Scan Chain
+--    Device Family: Cyclone III
+--    Device Part: -
+--    Device Speed Grade: 8
+--    PLL Scan Chain: Fast PLL (144 bits)
+--    File Name: /home/gyuri/git/mist-board/cores/archie/fpga/mist/pll_vidc_36.mif
+--    Generated: Sat Feb 23 00:01:12 2019
+
+WIDTH=1;
+DEPTH=144;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+	0    :   0; -- Reserved Bits = 0 (1 bit(s))
+	1    :   0; -- Reserved Bits = 0 (1 bit(s))
+	2    :   0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
+	3    :   0;
+	4    :   0; -- Loop Filter Resistance = 8 (5 bit(s)) (Setting 8)
+	5    :   1;
+	6    :   0;
+	7    :   0;
+	8    :   0;
+	9    :   0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
+	10   :   0; -- Reserved Bits = 0 (5 bit(s))
+	11   :   0;
+	12   :   0;
+	13   :   0;
+	14   :   0;
+	15   :   0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
+	16   :   0;
+	17   :   1;
+	18   :   0; -- N counter: Bypass = 0 (1 bit(s))
+	19   :   0; -- N counter: High Count = 3 (8 bit(s))
+	20   :   0;
+	21   :   0;
+	22   :   0;
+	23   :   0;
+	24   :   0;
+	25   :   1;
+	26   :   1;
+	27   :   1; -- N counter: Odd Division = 1 (1 bit(s))
+	28   :   0; -- N counter: Low Count = 2 (8 bit(s))
+	29   :   0;
+	30   :   0;
+	31   :   0;
+	32   :   0;
+	33   :   0;
+	34   :   1;
+	35   :   0;
+	36   :   0; -- M counter: Bypass = 0 (1 bit(s))
+	37   :   0; -- M counter: High Count = 60 (8 bit(s))
+	38   :   0;
+	39   :   1;
+	40   :   1;
+	41   :   1;
+	42   :   1;
+	43   :   0;
+	44   :   0;
+	45   :   0; -- M counter: Odd Division = 0 (1 bit(s))
+	46   :   0; -- M counter: Low Count = 60 (8 bit(s))
+	47   :   0;
+	48   :   1;
+	49   :   1;
+	50   :   1;
+	51   :   1;
+	52   :   0;
+	53   :   0;
+	54   :   0; -- clk0 counter: Bypass = 0 (1 bit(s))
+	55   :   0; -- clk0 counter: High Count = 5 (8 bit(s))
+	56   :   0;
+	57   :   0;
+	58   :   0;
+	59   :   0;
+	60   :   1;
+	61   :   0;
+	62   :   1;
+	63   :   1; -- clk0 counter: Odd Division = 1 (1 bit(s))
+	64   :   0; -- clk0 counter: Low Count = 4 (8 bit(s))
+	65   :   0;
+	66   :   0;
+	67   :   0;
+	68   :   0;
+	69   :   1;
+	70   :   0;
+	71   :   0;
+	72   :   1; -- clk1 counter: Bypass = 1 (1 bit(s))
+	73   :   0; -- clk1 counter: High Count = 0 (8 bit(s))
+	74   :   0;
+	75   :   0;
+	76   :   0;
+	77   :   0;
+	78   :   0;
+	79   :   0;
+	80   :   0;
+	81   :   0; -- clk1 counter: Odd Division = 0 (1 bit(s))
+	82   :   0; -- clk1 counter: Low Count = 0 (8 bit(s))
+	83   :   0;
+	84   :   0;
+	85   :   0;
+	86   :   0;
+	87   :   0;
+	88   :   0;
+	89   :   0;
+	90   :   1; -- clk2 counter: Bypass = 1 (1 bit(s))
+	91   :   0; -- clk2 counter: High Count = 0 (8 bit(s))
+	92   :   0;
+	93   :   0;
+	94   :   0;
+	95   :   0;
+	96   :   0;
+	97   :   0;
+	98   :   0;
+	99   :   0; -- clk2 counter: Odd Division = 0 (1 bit(s))
+	100  :   0; -- clk2 counter: Low Count = 0 (8 bit(s))
+	101  :   0;
+	102  :   0;
+	103  :   0;
+	104  :   0;
+	105  :   0;
+	106  :   0;
+	107  :   0;
+	108  :   1; -- clk3 counter: Bypass = 1 (1 bit(s))
+	109  :   0; -- clk3 counter: High Count = 0 (8 bit(s))
+	110  :   0;
+	111  :   0;
+	112  :   0;
+	113  :   0;
+	114  :   0;
+	115  :   0;
+	116  :   0;
+	117  :   0; -- clk3 counter: Odd Division = 0 (1 bit(s))
+	118  :   0; -- clk3 counter: Low Count = 0 (8 bit(s))
+	119  :   0;
+	120  :   0;
+	121  :   0;
+	122  :   0;
+	123  :   0;
+	124  :   0;
+	125  :   0;
+	126  :   1; -- clk4 counter: Bypass = 1 (1 bit(s))
+	127  :   0; -- clk4 counter: High Count = 0 (8 bit(s))
+	128  :   0;
+	129  :   0;
+	130  :   0;
+	131  :   0;
+	132  :   0;
+	133  :   0;
+	134  :   0;
+	135  :   0; -- clk4 counter: Odd Division = 0 (1 bit(s))
+	136  :   0; -- clk4 counter: Low Count = 0 (8 bit(s))
+	137  :   0;
+	138  :   0;
+	139  :   0;
+	140  :   0;
+	141  :   0;
+	142  :   0;
+	143  :   0;
+END;
--- a/cores/archie/fpga/mist/rom_reconfig_24.qip
+++ b/cores/archie/fpga/mist/rom_reconfig_24.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rom_reconfig_24.v"]
--- a/cores/archie/fpga/mist/rom_reconfig_24.v
+++ b/cores/archie/fpga/mist/rom_reconfig_24.v
@@ -0,0 +1,164 @@
+// megafunction wizard: %ROM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: rom_reconfig_24.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module rom_reconfig_24 (
+	address,
+	clock,
+	rden,
+	q);
+
+	input	[7:0]  address;
+	input	  clock;
+	input	  rden;
+	output	[0:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri1	  rden;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [0:0] sub_wire0;
+	wire [0:0] q = sub_wire0[0:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address),
+				.clock0 (clock),
+				.rden_a (rden),
+				.q_a (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.address_b (1'b1),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_a (1'b1),
+				.data_b (1'b1),
+				.eccstatus (),
+				.q_b (),
+				.rden_b (1'b1),
+				.wren_a (1'b0),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_a = "NONE",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.init_file = "../pll_vidc_24.mif",
+		altsyncram_component.intended_device_family = "Cyclone III",
+		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 256,
+		altsyncram_component.operation_mode = "ROM",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "CLOCK0",
+		altsyncram_component.widthad_a = 8,
+		altsyncram_component.width_a = 1,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "../pll_vidc_24.mif"
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+// Retrieval info: PRIVATE: WidthData NUMERIC "1"
+// Retrieval info: PRIVATE: rden NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "../pll_vidc_24.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
+// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_24.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_24.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_24.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_24.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_24_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_24_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
--- a/cores/archie/fpga/mist/rom_reconfig_25.qip
+++ b/cores/archie/fpga/mist/rom_reconfig_25.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rom_reconfig_25.v"]
--- a/cores/archie/fpga/mist/rom_reconfig_25.v
+++ b/cores/archie/fpga/mist/rom_reconfig_25.v
@@ -0,0 +1,164 @@
+// megafunction wizard: %ROM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: rom_reconfig_25.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module rom_reconfig_25 (
+	address,
+	clock,
+	rden,
+	q);
+
+	input	[7:0]  address;
+	input	  clock;
+	input	  rden;
+	output	[0:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri1	  rden;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [0:0] sub_wire0;
+	wire [0:0] q = sub_wire0[0:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address),
+				.clock0 (clock),
+				.rden_a (rden),
+				.q_a (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.address_b (1'b1),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_a (1'b1),
+				.data_b (1'b1),
+				.eccstatus (),
+				.q_b (),
+				.rden_b (1'b1),
+				.wren_a (1'b0),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_a = "NONE",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.init_file = "../pll_vidc_25.mif",
+		altsyncram_component.intended_device_family = "Cyclone III",
+		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 256,
+		altsyncram_component.operation_mode = "ROM",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "CLOCK0",
+		altsyncram_component.widthad_a = 8,
+		altsyncram_component.width_a = 1,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "../pll_vidc_25.mif"
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+// Retrieval info: PRIVATE: WidthData NUMERIC "1"
+// Retrieval info: PRIVATE: rden NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "../pll_vidc_25.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
+// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_25.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_25.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_25.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_25.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_25_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_25_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
--- a/cores/archie/fpga/mist/rom_reconfig_36.qip
+++ b/cores/archie/fpga/mist/rom_reconfig_36.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rom_reconfig_36.v"]
--- a/cores/archie/fpga/mist/rom_reconfig_36.v
+++ b/cores/archie/fpga/mist/rom_reconfig_36.v
@@ -0,0 +1,164 @@
+// megafunction wizard: %ROM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: rom_reconfig_36.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module rom_reconfig_36 (
+	address,
+	clock,
+	rden,
+	q);
+
+	input	[7:0]  address;
+	input	  clock;
+	input	  rden;
+	output	[0:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri1	  rden;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [0:0] sub_wire0;
+	wire [0:0] q = sub_wire0[0:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address),
+				.clock0 (clock),
+				.rden_a (rden),
+				.q_a (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.address_b (1'b1),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_a (1'b1),
+				.data_b (1'b1),
+				.eccstatus (),
+				.q_b (),
+				.rden_b (1'b1),
+				.wren_a (1'b0),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_a = "NONE",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.init_file = "pll_vidc_36.mif",
+		altsyncram_component.intended_device_family = "Cyclone III",
+		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 256,
+		altsyncram_component.operation_mode = "ROM",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "CLOCK0",
+		altsyncram_component.widthad_a = 8,
+		altsyncram_component.width_a = 1,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "pll_vidc_36.mif"
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+// Retrieval info: PRIVATE: WidthData NUMERIC "1"
+// Retrieval info: PRIVATE: rden NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "pll_vidc_36.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
+// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_36.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_36.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_36.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_36.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_36_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_36_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
--- a/cores/archie/fpga/mist/user_io.v
+++ b/cores/archie/fpga/mist/user_io.v
@@ -31,6 +31,7 @@ module user_io (

        output     [7:0] JOY0,
        output     [7:0] JOY1,
+        output           scandoubler_disable,
        output           ypbpr,

        input      [7:0] kbd_out_data,
@@ -60,12 +61,13 @@ assign JOY1 = joystick_1[7:0];

 assign BUTTONS  = but_sw[1:0];
 assign SWITCHES = but_sw[3:2];
+assign scandoubler_disable = but_sw[4];
 assign ypbpr = but_sw[5];
+
 // this variant of user_io is for the achie core (type == a6) only
 wire [7:0] core_type = 8'ha6;
 reg  [7:0] spi_byte_out;

-wire [7:0] kbd_out_status = { 4'ha, 3'b000, kbd_out_data_available };
 reg kbd_out_data_available = 0;

 // SPI bit and byte counters
@@ -73,8 +75,9 @@ always@(posedge SPI_CLK or posedge SPI_SS_IO) begin
    if(SPI_SS_IO == 1) begin
        bit_cnt <= 0;
        byte_cnt <= 0;
+        cmd <= 0;
    end else begin
-        if((bit_cnt == 7)&&(~&byte_cnt)) begin
+        if((&bit_cnt)&&(~&byte_cnt)) begin
            byte_cnt <= byte_cnt + 8'd1;
            if (!byte_cnt) cmd <= {sbuf, SPI_MOSI};
        end
@@ -83,9 +86,14 @@ always@(posedge SPI_CLK or posedge SPI_SS_IO) begin
 end

 always@(negedge SPI_CLK or posedge SPI_SS_IO) begin
+    reg [7:0] kbd_out_status;
+    reg [7:0] kbd_out_data_r;
+
    if(SPI_SS_IO == 1) begin
        SPI_MISO <= 1'bZ;
 	end else begin
+        kbd_out_status <= { 4'ha, 3'b000, kbd_out_data_available };
+        kbd_out_data_r <= kbd_out_data;
        // first byte returned is always core type, further bytes are 
        // command dependent
        if(byte_cnt == 0) begin
@@ -94,7 +102,7 @@ always@(negedge SPI_CLK or posedge SPI_SS_IO) begin
            // reading keyboard data
            if(cmd == 8'h04) begin
                if(byte_cnt == 1) SPI_MISO <= kbd_out_status[~bit_cnt];
-                else              SPI_MISO <= kbd_out_data[~bit_cnt];
+                else              SPI_MISO <= kbd_out_data_r[~bit_cnt];
            end
        end
    end
@@ -114,14 +122,12 @@ always@(posedge SPI_CLK or posedge SPI_SS_IO) begin
    end else begin
        spi_transfer_end_r <= 0;

-        if(bit_cnt != 7)
-            sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
-
+        if(&bit_cnt) begin
            // finished reading a byte, prepare to transfer to clk_sys
-            if(bit_cnt == 7) begin
-                spi_byte_in <= { sbuf, SPI_MOSI};
-                spi_receiver_strobe_r <= ~spi_receiver_strobe_r;
-            end
+            spi_byte_in <= { sbuf, SPI_MOSI};
+            spi_receiver_strobe_r <= ~spi_receiver_strobe_r;
+        end else
+            sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
    end
 end

@@ -151,7 +157,7 @@ always @(posedge clk_sys) begin
        if(~&abyte_cnt)
            abyte_cnt <= abyte_cnt + 8'd1;

-        if(abyte_cnt == 0) begin
+        if(!abyte_cnt) begin
            acmd <= spi_byte_in;
        end else begin
            case(acmd)
--- a/cores/archie/rtl/fdc1772.v
+++ b/cores/archie/rtl/fdc1772.v
@@ -92,9 +92,9 @@ always @(posedge clkcpu)
   
 wire irq_clr = !floppy_reset || cpu_read_status;
   
-always @(posedge irq_set or posedge irq_clr) begin
+always @(posedge clkcpu or posedge irq_clr) begin
   if(irq_clr) irq <= 1'b0;
-   else        irq <= 1'b1;
+   else if(irq_set) irq <= 1'b1;
 end
   
 assign floppy_firq = irq;
@@ -106,12 +106,12 @@ reg cpu_read_data;
 always @(posedge clkcpu)
  cpu_read_data <= wb_stb && wb_cyc && !wb_we && 
 		   (wb_adr[3:2] == FDC_REG_DATA);
-   
+
 wire drq_clr = !floppy_reset || cpu_read_data;
-   
-always @(posedge drq_set or posedge drq_clr) begin
+
+always @(posedge clkcpu or posedge drq_clr) begin
   if(drq_clr) drq <= 1'b0;
-   else        drq <= 1'b1;
+   else if(drq_set) drq <= 1'b1;
 end

 assign floppy_drq = drq;
@@ -131,9 +131,9 @@ wire fd0_sector_hdr;
 wire fd0_sector_data;
 wire fd0_dclk;

-floppy floppy0 (
-		.clk         ( clk8m_en        ), 
-		
+floppy #(.SYS_CLK(32000000)) floppy0 (
+		.clk         ( clkcpu          ),
+
 		// control signals into floppy
 		.select      (!floppy_drive[0] ),
 		.motor_on    ( motor_on        ),
@@ -141,7 +141,7 @@ floppy floppy0 (
 		.step_out    ( step_out        ),

 		// status signals generated by floppy
-		.dclk        ( fd0_dclk        ),
+		.dclk_en     ( fd0_dclk        ),
 		.track       ( fd0_track       ),
 		.sector      ( fd0_sector      ),
 		.sector_hdr  ( fd0_sector_hdr  ),
@@ -161,9 +161,9 @@ wire fd1_sector_hdr;
 wire fd1_sector_data;
 wire fd1_dclk;

-floppy floppy1 (
-		.clk         ( clk8m_en        ), 
-		
+floppy #(.SYS_CLK(32000000)) floppy1 (
+		.clk         ( clkcpu          ),
+
 		// control signals into floppy
 		.select      (!floppy_drive[1] ),
 		.motor_on    ( motor_on        ),
@@ -171,7 +171,7 @@ floppy floppy1 (
 		.step_out    ( step_out        ),

 		// status signals generated by floppy
-		.dclk        ( fd1_dclk        ),
+		.dclk_en     ( fd1_dclk        ),
 		.track       ( fd1_track       ),
 		.sector      ( fd1_sector      ),
 		.sector_hdr  ( fd1_sector_hdr  ),
@@ -191,9 +191,9 @@ wire fd2_sector_hdr;
 wire fd2_sector_data;
 wire fd2_dclk;

-floppy floppy2 (
-		.clk         ( clk8m_en        ), 
-		
+floppy #(.SYS_CLK(32000000)) floppy2 (
+		.clk         ( clkcpu          ),
+
 		// control signals into floppy
 		.select      (!floppy_drive[2] ),
 		.motor_on    ( motor_on        ),
@@ -201,7 +201,7 @@ floppy floppy2 (
 		.step_out    ( step_out        ),

 		// status signals generated by floppy
-		.dclk        ( fd2_dclk        ),
+		.dclk_en     ( fd2_dclk        ),
 		.track       ( fd2_track       ),
 		.sector      ( fd2_sector      ),
 		.sector_hdr  ( fd2_sector_hdr  ),
@@ -221,9 +221,9 @@ wire fd3_sector_hdr;
 wire fd3_sector_data;
 wire fd3_dclk;

-floppy floppy3 (
-		.clk         ( clk8m_en        ), 
-		
+floppy #(.SYS_CLK(32000000)) floppy3 (
+		.clk         ( clkcpu          ),
+
 		// control signals into floppy
 		.select      (!floppy_drive[3] ),
 		.motor_on    ( motor_on        ),
@@ -231,7 +231,7 @@ floppy floppy3 (
 		.step_out    ( step_out        ),

 		// status signals generated by floppy
-		.dclk        ( fd3_dclk        ),
+		.dclk_en     ( fd3_dclk        ),
 		.track       ( fd3_track       ),
 		.sector      ( fd3_sector      ),
 		.sector_hdr  ( fd3_sector_hdr  ),
@@ -280,7 +280,7 @@ wire fd_sector_data = 	(!floppy_drive[0])?fd0_sector_data:
 								(!floppy_drive[3])?fd3_sector_data:
 								1'b0;

-wire fd_dclk = 			(!floppy_drive[0])?fd0_dclk:
+wire fd_dclk_en =		(!floppy_drive[0])?fd0_dclk:
 								(!floppy_drive[1])?fd1_dclk:
 								(!floppy_drive[2])?fd2_dclk:
 								(!floppy_drive[3])?fd3_dclk:
@@ -329,7 +329,8 @@ reg [15:0] step_rate_cnt;
 wire step_busy = (step_rate_cnt != 0);
 reg [7:0] step_to;

-always @(posedge clk8m_en) begin
+always @(posedge clkcpu) begin
+   irq_set <= 0;
   if(!floppy_reset) begin
      motor_on <= 1'b0;
      busy <= 1'b0;
@@ -338,7 +339,7 @@ always @(posedge clk8m_en) begin
      irq_set <= 1'b0;
      data_read_start_set <= 1'b0;
      data_read_done_clr <= 1'b0;
-   end else begin
+   end else if (clk8m_en) begin
      irq_set <= 1'b0;
      data_read_start_set <= 1'b0;
      data_read_done_clr <= 1'b0;
@@ -473,20 +474,9 @@ end
 // floppy delivers data at a floppy generated rate (usually 250kbit/s), so the start and stop
 // signals need to be passed forth and back from cpu clock domain to floppy data clock domain
 reg data_read_start_set;
-reg data_read_start_clr;
-reg data_read_start;
-always @(posedge data_read_start_set or posedge data_read_start_clr) begin
-   if(data_read_start_clr) data_read_start <= 1'b0;
-   else                    data_read_start <= 1'b1;
-end

-reg data_read_done_set;
 reg data_read_done_clr;
 reg data_read_done;
-always @(posedge data_read_done_set or posedge data_read_done_clr) begin
-   if(data_read_done_clr) data_read_done <= 1'b0;
-   else                   data_read_done <= 1'b1;
-end

 // ==================================== FIFO ==================================
   
@@ -498,11 +488,11 @@ reg [10:0] fifo_wptr;

 // -------------------- data write -----------------------
   
-always @(posedge dio_in_strobe or posedge cmd_rx) begin
+always @(posedge clkcpu or posedge cmd_rx) begin
   if(cmd_rx)
     fifo_wptr <= 11'd0;
   else begin
-      if(fifo_wptr != 11'd1024) begin
+      if(dio_in_strobe && (fifo_wptr != 11'd1024)) begin
 			fifo[fifo_wptr] <= dio_in;
 			fifo_wptr <= fifo_wptr + 11'd1;
      end
@@ -511,20 +501,18 @@ end
   
 // -------------------- data read -----------------------

-reg dclkD, dclkD2;
 reg [10:0] data_read_cnt;
 always @(posedge clkcpu) begin
+   reg data_read_start_setD;
   // reset fifo read pointer on reception of a new command
   if(cmd_rx)
     fifo_rptr <= 11'd0;

-   data_read_start_clr <= 1'b0;
-   data_read_done_set <= 1'b0;
   drq_set <= 1'b0;
-
+   if (data_read_done_clr) data_read_done <= 0;
+   data_read_start_setD <= data_read_start_set;
   // received request to read data
-   if(data_read_start) begin
-      data_read_start_clr <= 1'b1;
+   if(~data_read_start_setD & data_read_start_set) begin

      // read_address command has 6 data bytes
      if(cmd[7:4] == 4'b1100)
@@ -535,10 +523,7 @@ always @(posedge clkcpu) begin
 			data_read_cnt <= 11'd1024+11'd1;
   end

-   // rising edge of floppy data clock (fd_dclk)
-   dclkD <= fd_dclk;
-   dclkD2 <= dclkD;
-   if(dclkD && !dclkD2) begin
+   if(fd_dclk_en) begin
      if(data_read_cnt != 0) begin
 			if(data_read_cnt != 1) begin
 				drq_set <= 1'b1;
@@ -567,7 +552,7 @@ always @(posedge clkcpu) begin
 			// count down and stop after last byte
 			data_read_cnt <= data_read_cnt - 11'd1;
 			if(data_read_cnt == 1)
-				data_read_done_set <= 1'b1;
+				data_read_done <= 1'b1;
 		end
   end
 end
--- a/cores/archie/rtl/floppy.v
+++ b/cores/archie/rtl/floppy.v
@@ -25,7 +25,7 @@ module floppy (
 	input 	     step_in,
 	input 	     step_out,

-	output 	     dclk,         // data clock 
+	output 	     dclk_en,      // data clock enable
 	output [6:0] track,        // number of track under head
 	output [3:0] sector,       // number of sector under head, 0 = no sector
 	output 	     sector_hdr,   // valid sector header under head
@@ -37,7 +37,7 @@ module floppy (

 // The sysclock is the value all floppy timings are derived from. 
 // Default: 8 MHz
-localparam SYS_CLK = 8000000;  
+parameter SYS_CLK = 8000000;

 assign sector_hdr = (sec_state == SECTOR_STATE_HDR);
 assign sector_data = (sec_state == SECTOR_STATE_DATA);
@@ -70,7 +70,7 @@ assign ready = select && (rate == RATE) && (step_busy == 0);
 // Index pulse generation. Pulse starts with the begin of index_pulse_start
 // and lasts INDEX_PULSE_CYCLES system clock cycles
 localparam INDEX_PULSE_CYCLES = INDEX_PULSE_LEN * SYS_CLK / 1000;
-reg [15:0] index_pulse_cnt;   
+reg [18:0] index_pulse_cnt;
 always @(posedge clk) begin
   if(index_pulse_start && (index_pulse_cnt == INDEX_PULSE_CYCLES-1)) begin
      index <= 1'b0;
@@ -92,7 +92,7 @@ reg [6:0] current_track = 7'd0;

 reg step_inD;
 reg step_outD;
-reg [17:0] step_busy;
+reg [19:0] step_busy;
   
 always @(posedge clk) begin
   step_inD <= step_in;
@@ -136,7 +136,8 @@ reg [1:0] sec_state;
 reg [9:0] sec_byte_cnt;  // counting bytes within sectors
 reg [3:0] current_sector = SECTOR_BASE;
  
-always @(posedge byte_clk) begin
+always @(posedge clk) begin
+	if (byte_clk_en) begin
   if(index_pulse_start) begin
      sec_byte_cnt <= SECTOR_GAP_LEN-1;
      sec_state <= SECTOR_STATE_GAP;     // track starts with gap
@@ -170,6 +171,8 @@ always @(posedge byte_clk) begin
      end else
 	sec_byte_cnt <= sec_byte_cnt - 10'd1;
   end
+
+   end
 end
   
 // ================================================================
@@ -179,24 +182,31 @@ end
 // An ed floppy at 300rpm with 1MBit/s has max 31.250 bytes/track
 // thus we need to support up to 31250 events
 reg [14:0] byte_cnt;
-reg 	   index_pulse_start;   
-always @(posedge byte_clk) begin
-   index_pulse_start <= 1'b0;
+reg 	   index_pulse_start;
+always @(posedge clk) begin
+	if (byte_clk_en) begin
+		index_pulse_start <= 1'b0;

-   if(byte_cnt == BPT-1) begin
-      byte_cnt <= 0;
-      index_pulse_start <= 1'b1;      
-   end else
-     byte_cnt <= byte_cnt + 1;
+		if(byte_cnt == BPT-1) begin
+			byte_cnt <= 0;
+			index_pulse_start <= 1'b1;
+		end else
+			byte_cnt <= byte_cnt + 1;
+	end
 end

 // Make byte clock from bit clock.
 // When a DD disk spins at 300RPM every 32us a byte passes the disk head
-assign dclk = byte_clk;
-wire byte_clk = clk_cnt2[2];
+assign dclk_en = byte_clk_en;
+reg byte_clk_en;
 reg [2:0] clk_cnt2;
-always @(posedge data_clk)
-  clk_cnt2 <= clk_cnt2 + 1;
+always @(posedge clk) begin
+	byte_clk_en <= 0;
+	if (data_clk_en) begin
+		clk_cnt2 <= clk_cnt2 + 1;
+		if (clk_cnt2 == 3'b011) byte_clk_en <= 1;
+	end
+end

 // ================================================================
 // ===================== SPIN VIRTUAL DISK ========================
@@ -246,11 +256,14 @@ end
 // speed and reaches the full rate when the disk rotates at 300RPM. No
 // valid data can be read until the disk has reached it's full speed.
 reg data_clk;
+reg data_clk_en;
 reg [31:0] clk_cnt;
 always @(posedge clk) begin
+   data_clk_en <= 0;
   if(clk_cnt + rate > SYS_CLK/2) begin
      clk_cnt <= clk_cnt - (SYS_CLK/2 - rate);
      data_clk <= !data_clk;
+      if (~data_clk) data_clk_en <= 1;
   end else
     clk_cnt <= clk_cnt + rate;
 end