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STEroids work
This commit is contained in:
harbaum
101
cores/mist/cache.v
Normal file
101
cores/mist/cache.v
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@@ -0,0 +1,101 @@
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//
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// cache.v
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//
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// Atari ST CPU cache implementation for the MiST board
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// http://code.google.com/p/mist-board/
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//
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// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module cache (
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input clk_128,
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input clk_8,
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input reset,
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input flush,
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input [22:0] addr, // cpu word address
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input wr,
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input rd,
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output [15:0] dout,
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output hit,
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// interface to update entire caches when read from ram
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input [63:0] din64,
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input update64
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);
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reg [3:0] t;
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always @(posedge clk_128) begin
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// 128Mhz counter synchronous to 8 Mhz clock
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// force counter to pass state 0 exactly after the rising edge of clk_8
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if(((t == 4'd15) && ( clk_8 == 0)) ||
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((t == 4'd0) && ( clk_8 == 1)) ||
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((t != 4'd15) && (t != 4'd0)))
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t <= t + 4'd1;
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end
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// de-multiplex 64 bit data into word requested by cpu
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assign dout = (word == 2'd0)?current_data[15: 0]:
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(word == 2'd1)?current_data[31:16]:
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(word == 2'd2)?current_data[47:32]:
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current_data[63:48];
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// wire entry according to line/address
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wire [63:0] current_data = data_latch[line];
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// cache size configuration
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localparam BITS = 5;
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localparam ENTRIES = 32; // 2 ** BITS
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localparam ALLZERO = 32'd0; // 2 ** BITS zero bits
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// _word_ address mapping example with 16 cache lines (BITS == 4)
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// 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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// T T T T T T T T T T T T T T T T T L L L L W W
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// T = stored in tag RAM
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// L = cache line
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// W = 16 bit word select
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wire [21-BITS-1:0] tag = addr[22:2+BITS] /* synthesis keep */;
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wire [BITS-1:0] line = addr[2+BITS-1:2];
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wire [1:0] word = addr[1:0];
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/* ------------------------------------------------------------------------------ */
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/* --------------------------------- cache memory ------------------------------- */
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/* ------------------------------------------------------------------------------ */
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reg [63:0] data_latch [ENTRIES-1:0];
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reg [21-BITS-1:0] tag_latch [ENTRIES-1:0];
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reg [ENTRIES-1:0] valid;
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// signal indicating the currently selected cache line is valid and matches the
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// address the cpu is currently requesting
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assign hit = valid[line] && (tag_latch[line] == tag);
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always @(posedge clk_128) begin
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if(reset || flush) begin
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valid <= ALLZERO;
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end else begin
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// update64 indicates that a whole cache line is to be updated
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if(update64) begin
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data_latch[line] <= din64;
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tag_latch[line] <= tag;
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valid[line] <= 1'b1;
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end
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end
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end
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endmodule
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@@ -139,54 +139,54 @@ reg [7:0] vr;
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// any pending and not masked interrupt causes the irq line to go high
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// if highest_irq_pending != higest_irq_active then there's a high prio
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// irq in service and no irq is generated until this one is finished
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assign irq = ((ipr & imr) != 16'h0000) && (highest_irq_active == highest_irq_pending);
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//assign irq = ((ipr & imr) != 16'h0000) && (highest_irq_active == highest_irq_pending);
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// handle pending and in service irqs
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wire [15:0] irq_active_map = (ipr | isr) & imr;
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//wire [15:0] irq_active_map = (ipr | isr) & imr;
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// (i am pretty sure this can be done much more elegant ...)
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// check the number of the highest active irq
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wire [3:0] highest_irq_active=
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( irq_active_map[15] == 1'b1)?4'd15:
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((irq_active_map[15:14] == 2'b01)?4'd14:
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((irq_active_map[15:13] == 3'b001)?4'd13:
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((irq_active_map[15:12] == 4'b0001)?4'd12:
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((irq_active_map[15:11] == 5'b00001)?4'd11:
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((irq_active_map[15:10] == 6'b000001)?4'd10:
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((irq_active_map[15:9] == 7'b0000001)?4'd9:
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((irq_active_map[15:8] == 8'b00000001)?4'd8:
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((irq_active_map[15:7] == 9'b000000001)?4'd7:
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((irq_active_map[15:6] == 10'b000000001)?4'd6:
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((irq_active_map[15:5] == 11'b0000000001)?4'd5:
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((irq_active_map[15:4] == 12'b00000000001)?4'd4:
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((irq_active_map[15:3] == 13'b000000000001)?4'd3:
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((irq_active_map[15:2] == 14'b0000000000001)?4'd2:
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((irq_active_map[15:1] == 15'b00000000000001)?4'd1:
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((irq_active_map[15:0] == 16'b000000000000001)?4'd0:
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4'd0)))))))))))))));
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//wire [3:0] highest_irq_active=
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// ( irq_active_map[15] == 1'b1)?4'd15:
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// ((irq_active_map[15:14] == 2'b01)?4'd14:
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// ((irq_active_map[15:13] == 3'b001)?4'd13:
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// ((irq_active_map[15:12] == 4'b0001)?4'd12:
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// ((irq_active_map[15:11] == 5'b00001)?4'd11:
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// ((irq_active_map[15:10] == 6'b000001)?4'd10:
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// ((irq_active_map[15:9] == 7'b0000001)?4'd9:
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// ((irq_active_map[15:8] == 8'b00000001)?4'd8:
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// ((irq_active_map[15:7] == 9'b000000001)?4'd7:
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// ((irq_active_map[15:6] == 10'b000000001)?4'd6:
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// ((irq_active_map[15:5] == 11'b0000000001)?4'd5:
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// ((irq_active_map[15:4] == 12'b00000000001)?4'd4:
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// ((irq_active_map[15:3] == 13'b000000000001)?4'd3:
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// ((irq_active_map[15:2] == 14'b0000000000001)?4'd2:
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// ((irq_active_map[15:1] == 15'b00000000000001)?4'd1:
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// ((irq_active_map[15:0] == 16'b000000000000001)?4'd0:
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// 4'd0)))))))))))))));
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// generate irq signal if an irq is pending and no other irq of same or higher prio is in service
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//assign irq = ((ipr & imr) != 16'h0000) && ((isr == 16'h0000) || (highest_irq_pending > irq_in_service));
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assign irq = ((ipr & imr) != 16'h0000) && ((isr == 16'h0000) || (highest_irq_pending > irq_in_service));
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// check number of current interrupt in service
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//wire [3:0] irq_in_service =
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// ( isr[15] == 1'b1)?4'd15:
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// ((isr[15:14] == 2'b01)?4'd14:
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// ((isr[15:13] == 3'b001)?4'd13:
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// ((isr[15:12] == 4'b0001)?4'd12:
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// ((isr[15:11] == 5'b00001)?4'd11:
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// ((isr[15:10] == 6'b000001)?4'd10:
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// ((isr[15:9] == 7'b0000001)?4'd9:
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// ((isr[15:8] == 8'b00000001)?4'd8:
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// ((isr[15:7] == 9'b000000001)?4'd7:
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// ((isr[15:6] == 10'b000000001)?4'd6:
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// ((isr[15:5] == 11'b0000000001)?4'd5:
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// ((isr[15:4] == 12'b00000000001)?4'd4:
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// ((isr[15:3] == 13'b000000000001)?4'd3:
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// ((isr[15:2] == 14'b0000000000001)?4'd2:
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// ((isr[15:1] == 15'b00000000000001)?4'd1:
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// ((isr[15:0] == 16'b000000000000001)?4'd0:
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// 4'd0)))))))))))))));
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wire [3:0] irq_in_service =
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( isr[15] == 1'b1)?4'd15:
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((isr[15:14] == 2'b01)?4'd14:
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((isr[15:13] == 3'b001)?4'd13:
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((isr[15:12] == 4'b0001)?4'd12:
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((isr[15:11] == 5'b00001)?4'd11:
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((isr[15:10] == 6'b000001)?4'd10:
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((isr[15:9] == 7'b0000001)?4'd9:
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((isr[15:8] == 8'b00000001)?4'd8:
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((isr[15:7] == 9'b000000001)?4'd7:
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((isr[15:6] == 10'b000000001)?4'd6:
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((isr[15:5] == 11'b0000000001)?4'd5:
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((isr[15:4] == 12'b00000000001)?4'd4:
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((isr[15:3] == 13'b000000000001)?4'd3:
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((isr[15:2] == 14'b0000000000001)?4'd2:
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((isr[15:1] == 15'b00000000000001)?4'd1:
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((isr[15:0] == 16'b000000000000001)?4'd0:
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4'd0)))))))))))))));
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wire [15:0] irq_pending_map = ipr & imr;
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@@ -215,7 +215,7 @@ wire [7:0] gpip_cpu_out = (i & ~ddr) | (gpip & ddr);
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// cpu read interface
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always @(iack, sel, ds, rw, addr, gpip_cpu_out, aer, ddr, ier, ipr, isr, imr,
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vr, irq_vec, serial_data_out_fifo_full, timera_dat_o, timerb_dat_o,
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vr, serial_data_out_fifo_full, timera_dat_o, timerb_dat_o,
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timerc_dat_o, timerd_dat_o, timera_ctrl_o, timerb_ctrl_o, timerc_ctrl_o,
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timerd_ctrl_o) begin
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@@ -248,15 +248,13 @@ always @(iack, sel, ds, rw, addr, gpip_cpu_out, aer, ddr, ier, ipr, isr, imr,
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if(addr == 5'h16) dout = serial_data_out_fifo_full?8'h00:8'h80;
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end else if(iack) begin
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dout = irq_vec;
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dout = { vr[7:4], highest_irq_pending };
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end
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end
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// delay inputs to detect changes
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reg [7:0] iD, iD2;
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reg [7:0] irq_vec;
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// mask of input irqs which are overwritten by timer a/b inputs
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wire [7:0] ti_irq_mask = { 3'b000, pulse_mode, 3'b000};
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wire [7:0] ti_irq = { 3'b000, t_i[0], t_i[1], 3'b000};
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@@ -265,11 +263,6 @@ reg iackD;
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always @(posedge clk) begin
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iackD <= iack;
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// the pending irq changes in the middle of an iack
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// phase, so we latch the current vector to keep ist stable
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// during the entire cpu read
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irq_vec <= { vr[7:4], highest_irq_pending };
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// delay inputs for irq generation, apply aer (irq edge)
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iD <= aer ^ ((i & ~ti_irq_mask) | (ti_irq & ti_irq_mask));
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iD2 <= iD;
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@@ -94,8 +94,11 @@ always @(posedge clk_8) begin
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if(cpu_cycle) begin
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// timeout only when cpu owns the bus and when
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// neither dtack nor another bus master are active
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// also cacheable areas should never generate a
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// bus error (TODO: check for write on first eight words)
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if(dtack_timeout != 3'd7) begin
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if(!tg68_dtack || br || tg68_as)
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if(!tg68_dtack || br || tg68_as || cacheable)
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dtack_timeout <= 3'd0;
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else
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dtack_timeout <= dtack_timeout + 3'd1;
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@@ -690,12 +693,16 @@ always @(posedge clk_8) begin
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tg68_lds <= tg68_lds_S;
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tg68_rw <= tg68_rw_S;
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end
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localparam CPU_THROTTLE = 4'd4;
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reg [3:0] fromCache;
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// the CPU throttle counter limits the CPU speed to a rate the tg68 core can
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// handle. With a throttle of "4" the core will run effectively at 32MHz which
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// is equivalent to ~64MHz on a real 68000. This speed will never be achieved
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// since memory and peripheral access slows the cpu further
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localparam CPU_THROTTLE = 4'd5;
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reg [3:0] clkcnt;
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// TODO: make sure 8Mhz cycles are complete and were from the start
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reg [15:0] cacheReadLatch;
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always @(posedge clk_128) begin
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// count 0..15 within a 8MHz cycle
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if(((clkcnt == 15) && ( clk_8 == 0)) ||
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@@ -706,10 +713,14 @@ always @(posedge clk_128) begin
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// default: cpu does not run
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clkena <= 1'b0;
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cacheUpdate <= 1'b0;
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cacheRead <= 1'b0;
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// assume the cpu uses the following 8 Mhz cycles
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if(clkcnt == 15)
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cpuDoes8MhzCycle <= 1'b1;
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// only run cpu if throttle counter has run down
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if((cpu_throttle == 4'd0) && !reset) begin
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cacheRead <= 1'b0;
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// cpu does internal processing -> let it do this immediately
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// don't let this happen in the cpu cycle as this may result in a
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@@ -719,35 +730,27 @@ always @(posedge clk_128) begin
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clkena <= 1'b1;
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cpu_throttle <= CPU_THROTTLE;
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cpuDoes8MhzCycle <= 1'b0;
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end else if((fromCache != 0) && !br && steroids && tg68_rw_S &&
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(tg68_busstate == 2'b00) && cache_hit && cacheable) begin
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end else if( !br && steroids && (tg68_busstate == 2'b00) && cache_hit && cacheable) begin
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clkena <= 1'b1;
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cacheRead <= 1'b1;
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cacheReadLatch <= cache_data_out;
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cpu_throttle <= CPU_THROTTLE;
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cpuDoes8MhzCycle <= 1'b0;
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fromCache <= fromCache - 4'd1;
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end begin
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// cpu does io -> force it to wait for end of its bus cycle
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// three cases:
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// cpu addresses ram (incl. rom) -> terminate transfer early
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// cpu addresses io -> terminate transfer after current cycle
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// ...
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// assume the cpu uses the following 8 Mhz cycles
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if(clkcnt == 15)
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cpuDoes8MhzCycle <= 1'b1;
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if(clkcnt == 13) begin // 15
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// this ends a normal 8MHz bus cycle. This requires that the
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// cpu/chipset had the entire cycle and not e.g. started just in
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// the middle. This is verified using the puDoes8MhzCycle signal
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// which is invalidated whenever the cpu uses a
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// clkcnt == 14 -> clkena in cycle 15 -> cpu runs in cycle 15
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if(clkcnt == 13) begin
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if(cpu_uses_8mhz_cycle && cpuDoes8MhzCycle) begin
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clkena <= 1'b1;
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cpu_throttle <= CPU_THROTTLE;
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// update cache on cpu instruction read
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if(tg68_rw && (tg68_busstate == 2'b00))
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if(tg68_busstate == 2'b00)
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cacheUpdate <= 1'b1;
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fromCache <= 4'd1;
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end
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end
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end
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@@ -757,14 +760,14 @@ end
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wire [1:0] tg68_busstate;
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// rewire cache
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wire [15:0] cpu_data_in_cache = cacheRead?cache_data_out:cpu_data_in;
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// feed data from cache into the cpu
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wire [15:0] cpu_data_in = cacheRead?cacheReadLatch:system_data_out;
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TG68KdotC_Kernel #(2,2,2,2,2,2) tg68k (
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.clk (clk_128 ),
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.nReset (~reset ),
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.clkena_in (clkena ),
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.data_in (cpu_data_in_cache ),
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.data_in (cpu_data_in ),
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.IPL (ipl ),
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.IPL_autovector (1'b0 ),
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.berr (tg68_berr ),
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@@ -805,7 +808,7 @@ cache cache (
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.clk_128 ( clk_128 ),
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.clk_8 ( clk_8 ),
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.reset ( reset ),
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.flush ( 1'b0 ),
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.flush ( br ),
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// use the tg68_*_S signals here to quickly react on cpu requests
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.addr ( tg68_adr_S[23:1] ),
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@@ -911,7 +914,7 @@ wire cpu_cycle_wr = data_io_br?data_io_write:(blitter_br?blitter_master_write:(a
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wire ram_wr = video_cycle?video_cycle_wr:(cpu_cycle?cpu_cycle_wr:1'b0);
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wire [15:0] ram_data_out;
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wire [15:0] cpu_data_in = cpu2mem?ram_data_out:io_data_out;
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wire [15:0] system_data_out = cpu2mem?ram_data_out:io_data_out;
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wire [15:0] ram_data_in = data_io_br?data_io_dout:(blitter_br?blitter_master_data_out:tg68_dat_out);
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// data strobe
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