Added ypbpr support to atari st core

cores/mist/mist_top.v

@@ -269,8 +269,6 @@ end
 
 wire viking_active = (viking_in_use == 8'hff);
 
-// xyz
-
 video video (
 	.clk_128      	(clk_128    ),
 	.clk_32      	(clk_32     ),
@@ -312,6 +310,7 @@ video video (
    .viking_enable       ( viking_active       ), // enable and activate viking video card
    .viking_himem        ( steroids            ), // let viking use memory from $e80000
    .scandoubler_disable ( scandoubler_disable ), // don't use scandoubler in 15khz modes 
+   .ypbpr               ( ypbpr               ), // output ypbpr instead of rgb 
 	.adjust              ( video_adj    	    ),
 	.pal56               ( ~system_ctrl[9]     ),
    .scanlines           ( system_ctrl[21:20]  ),
@@ -1127,6 +1126,7 @@ wire eth_rx_write_strobe, eth_rx_write_begin;
 
 wire [2:0] switches;
 wire scandoubler_disable;
+wire ypbpr;
 
 //// user io has an extra spi channel outside minimig core ////
 user_io user_io(
@@ -1180,6 +1180,7 @@ user_io user_io(
 
 		// io controller requests to disable vga scandoubler
 		.scandoubler_disable       (scandoubler_disable),
+		.ypbpr                     (ypbpr),
 		.SWITCHES                  (switches ),
 		.CORE_TYPE						(8'ha3)    // mist core id
 );

cores/mist/rgb2ypbpr.sv

@@ -0,0 +1,55 @@
+module rgb2ypbpr (
+	input [5:0]     red,
+	input [5:0]     green,
+	input [5:0]     blue,
+
+	output [5:0]    y,
+	output [5:0]    pb,
+	output [5:0]    pr
+);	
+	
+wire [5:0] yuv_full[225] = '{
+  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
+  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
+  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
+  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
+  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
+  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
+  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
+  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
+  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
+  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
+  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
+  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
+  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
+  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
+  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
+  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
+  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
+  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
+  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
+  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
+  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
+  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
+  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
+  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
+  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
+  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
+  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
+  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
+  6'd63
+};
+
+wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
+wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
+wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
+
+wire [7:0] y_i  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
+wire [7:0] pb_i = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
+wire [7:0] pr_i = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
+
+assign pr = yuv_full[pr_i - 8'd16];
+assign y  = yuv_full[y_i  - 8'd16];
+assign pb = yuv_full[pb_i - 8'd16];
+
+endmodule

cores/mist/user_io.v

@@ -59,7 +59,8 @@ module user_io(
 		// on-board buttons and dip switches
 		output [1:0] 	  BUTTONS,
 		output [1:0]     SWITCHES,
-		output           scandoubler_disable
+		output           scandoubler_disable,
+		output           ypbpr
 );
 
 // filter spi clock. the 8 bit gate delay is ~2.5ns in total
@@ -70,7 +71,7 @@ reg [3:0] 			byte_cnt;
 reg [6:0]         sbuf;
 reg [7:0]         cmd;
 reg [3:0] 	      bit_cnt;       // 0..15
-reg [4:0] 	      but_sw;
+reg [5:0] 	      but_sw;
 
 // counter runs 0..7,8..15,8..15,8..15
 wire [2:0] tx_bit = ~(bit_cnt[2:0]);
@@ -78,6 +79,7 @@ wire [2:0] tx_bit = ~(bit_cnt[2:0]);
 assign BUTTONS = but_sw[1:0];
 assign SWITCHES = but_sw[3:2];
 assign scandoubler_disable = but_sw[4];
+assign ypbpr = but_sw[5];
 
 // prepent "a5" to status to make sure io controller can detect that a core
 // doesn't support the command
@@ -204,7 +206,7 @@ always@(negedge spi_sck) begin
 				eth_mac_begin <= 1'b0;
 
 				if(cmd == 1) 
-					 but_sw <= { sbuf[3:0], SPI_MOSI }; 
+					 but_sw <= { sbuf[4:0], SPI_MOSI }; 
 
 				// send ikbd byte to acia
 			   if(cmd == 2) begin

cores/mist/video.v

@@ -59,7 +59,8 @@ module video (
   // system config
   input         viking_enable,       // enable viking video card
   input         viking_himem,        // let viking use memory from $e80000
-  input 	scandoubler_disable, // don't use scandoubler in 15khz modes 
+  input 	scandoubler_disable,        // don't use scandoubler in 15khz modes 
+  input 	ypbpr,                      // output ypbpr instead of rgb 
   input 	pal56,               // use VGA compatible 56hz for PAL
   input [1:0] 	scanlines,           // scanlines (00-none 01-25% 10-50% 11-100%)
   input [15:0] 	adjust,              // hor/ver video adjust
@@ -75,13 +76,15 @@ module video (
 assign vaddr = viking_enable?viking_vaddr:shifter_vaddr;
 assign read  = viking_enable?viking_read:shifter_read;
 
+wire ypbpr_cs = ~(shifter_sd_adjusted_hs ^ shifter_sd_adjusted_vs);
+
 // if we use 15khz signals without scan doubler then we need
 // to create a composite sync on hsync
 wire enable_csync =  sd_15khz_detected && scandoubler_disable;
 // wire csync = shifter_hs == shifter_vs;
 wire csync = shifter_sd_adjusted_hs == shifter_sd_adjusted_vs;
-assign hs = enable_csync?csync:stvid_hs;
-assign vs = enable_csync?1'b1:stvid_vs;
+assign hs = enable_csync?csync:ypbpr?ypbpr_cs:stvid_hs;
+assign vs = (enable_csync || ypbpr)?1'b1:stvid_vs;
 
 // ------------------------- OSD ---------------------------
 
@@ -92,7 +95,24 @@ always @(posedge clk_128)
 
 wire osd_clk = viking_enable?clk_128:clk_32;
    
+wire [5:0] y, pb, pr;
+rgb2ypbpr rgb2ypbpr (
+	.red    ( osd_r ),
+	.green  ( osd_g ),
+	.blue   ( osd_b ),
+	
+	.y      ( y     ),
+	.pb     ( pb    ),
+	.pr     ( pr    )
+);
+
+// demultiplex between ypbpr and rgb signals
+assign video_r = ypbpr?pr:osd_r;
+assign video_g = ypbpr? y:osd_g;
+assign video_b = ypbpr?pb:osd_b;
+
 // include OSD overlay
+wire [5:0] osd_r, osd_g, osd_b;
 osd osd (
          .clk        ( osd_clk    ),
 
@@ -110,9 +130,9 @@ osd osd (
          .b_in       ( ovl_b ),
 	 
          // receive signal with OSD overlayed
-         .r_out      ( video_r  ),
-         .g_out      ( video_g  ),
-         .b_out      ( video_b  )
+         .r_out      ( osd_r  ),
+         .g_out      ( osd_g  ),
+         .b_out      ( osd_b  )
 );
 
 // include debug overlay