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Code Issues Releases Wiki Activity

Fix blitter to pass diagnostic cartridge tests

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This commit is contained in:
harbaum
2014-02-04 20:28:52 +00:00
parent 7e8bd85fa1
commit a17551a8d8
2 changed files with 8 additions and 18 deletions
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17
cores/mist/blitter.v
View File

@@ -78,6 +78,7 @@ reg [1:0] hop;
reg [3:0] op;
reg [3:0] line_number;
reg [3:0] line_number_latch;
reg smudge;
reg hog;
reg busy;
@@ -102,7 +103,7 @@ end
// CPU READ
always @(sel, rw, addr, src_y_inc, src_x_inc, src_addr, endmask1, endmask2, endmask3,
dst_x_inc, dst_y_inc, dst_addr, x_count, y_count, hop, op, busy, hog,
smudge, line_number, fxsr, nfsr, skew) begin
smudge, line_number_latch, fxsr, nfsr, skew) begin
dout = 16'h0000;
if(sel && rw) begin
@@ -128,7 +129,7 @@ always @(sel, rw, addr, src_y_inc, src_x_inc, src_addr, endmask1, endmask2, endm
// since reading them has no side effect we can return the 8 bit registers
// without caring for uds/lds
if(addr == 5'h1d) dout <= { 6'b000000, hop, 4'b0000, op };
if(addr == 5'h1e) dout <= { busy, hog, smudge, 1'b0, line_number, fxsr, nfsr, 2'b00, skew };
if(addr == 5'h1e) dout <= { busy, hog, smudge, 1'b0, line_number_latch, fxsr, nfsr, 2'b00, skew };
end
end
@@ -197,7 +198,7 @@ always @(negedge clk) begin
if((addr == 5'h1d) && ~lds) op <= din[3:0];
if((addr == 5'h1e) && ~uds) begin
line_number <= din[11:8];
line_number_latch <= din[11:8];
smudge <= din[13];
hog <= din[14];
@@ -256,6 +257,7 @@ always @(negedge clk) begin
// blitter has just been setup, so init the state machine in first step
if(init) begin
init <= 1'b0;
line_number <= line_number_latch;
if(skip_src_read) begin // skip source read (state 0)
if(dest_required) state <= 2'd1; // but dest needs to be read
@@ -320,8 +322,8 @@ always @(negedge clk) begin
// do signed add by sign expanding XXX_y_inc
dst_addr <= dst_addr + { {8{dst_y_inc[15]}}, dst_y_inc };
if(dst_y_inc[15]) line_number <= line_number + 4'd1;
else line_number <= line_number - 4'd1;
if(!dst_y_inc[15]) line_number <= line_number + 4'd1;
else line_number <= line_number - 4'd1;
x_count <= x_count_latch;
y_count <= y_count - 8'd1;
@@ -341,11 +343,6 @@ always @(negedge clk) begin
else state <= 2'd0; // normal source read state
end
end
// if(busy && (y_count == 0)) begin
// undo last src inc
// src_addr <= src_addr - { {8{src_x_inc[15]}}, src_x_inc };
// end
end
end

9
cores/mist/mist_top.v
View File

@@ -346,13 +346,6 @@ wire blitter_master_read;
wire blitter_irq;
wire [15:0] blitter_master_data_out;
// The bg signal works a little different as usual. The blitter
// will only apply br when bg allows it to do so. Forcing bussatte == 0
// make sure that the bus is never transferred in the middle of an
// instruction. This is required since some instructions use d to control
// the blitter are atomic on a real ST
wire blitter_bg = (tg68_busstate == 2'd0);
blitter blitter (
.bus_cycle (bus_cycle ),
@@ -375,7 +368,7 @@ blitter blitter (
.br_in (data_io_br ),
.br_out (blitter_br ),
.bg (blitter_bg ),
.bg (1'b1 ), // blitter grabs bus at any time
.irq (blitter_irq ),
.turbo (steroids )