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Code Issues Releases Wiki Activity

BBC: update PSG from Colecovision

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This commit is contained in:
Gyorgy Szombathelyi
2020-05-11 20:23:23 +02:00
parent 4a662b9aa9
commit a36bea9524
14 changed files with 61 additions and 332 deletions
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11
cores/bbc/fpga/mist/bbc_mist_top.qsf
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@@ -162,6 +162,7 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
set_location_assignment PLL_1 -to CLOCKS|altpll_component|auto_generated|pll1
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VERILOG_FILE ../rtl/sigma_delta_dac.v
set_global_assignment -name VERILOG_FILE ../rtl/audio.v
set_global_assignment -name VERILOG_FILE ../../rtl/adc.v
@@ -175,18 +176,11 @@ set_global_assignment -name VERILOG_FILE ../../rtl/bbc.v
set_global_assignment -name VHDL_FILE ../../rtl/via6522.vhd
set_global_assignment -name VERILOG_FILE ../../rtl/saa5050/saa5050_rom.v
set_global_assignment -name VERILOG_FILE ../../rtl/saa5050/saa5050.v
set_global_assignment -name VHDL_FILE "../../rtl/sn76489-1.0/sn76489_top-c.vhd"
set_global_assignment -name VHDL_FILE "../../rtl/sn76489-1.0/sn76489_top.vhd"
set_global_assignment -name VHDL_FILE "../../rtl/sn76489-1.0/sn76489_tone-c.vhd"
set_global_assignment -name VHDL_FILE "../../rtl/sn76489-1.0/sn76489_tone.vhd"
set_global_assignment -name VHDL_FILE "../../rtl/sn76489-1.0/sn76489_noise-c.vhd"
set_global_assignment -name VHDL_FILE "../../rtl/sn76489-1.0/sn76489_noise.vhd"
set_global_assignment -name VHDL_FILE "../../rtl/sn76489-1.0/sn76489_latch_ctrl-c.vhd"
set_global_assignment -name VHDL_FILE "../../rtl/sn76489-1.0/sn76489_latch_ctrl.vhd"
set_global_assignment -name VHDL_FILE "../../rtl/sn76489-1.0/sn76489_comp_pack-p.vhd"
set_global_assignment -name VHDL_FILE "../../rtl/sn76489-1.0/sn76489_clock_div-c.vhd"
set_global_assignment -name VHDL_FILE "../../rtl/sn76489-1.0/sn76489_clock_div.vhd"
set_global_assignment -name VHDL_FILE "../../rtl/sn76489-1.0/sn76489_attenuator-c.vhd"
set_global_assignment -name VHDL_FILE "../../rtl/sn76489-1.0/sn76489_attenuator.vhd"
set_global_assignment -name QIP_FILE ../../rtl/T65/T65.qip
set_global_assignment -name QIP_FILE mmfs.qip
@@ -199,5 +193,4 @@ set_global_assignment -name VERILOG_FILE sdram.v
set_global_assignment -name VERILOG_FILE clockgen.v
set_global_assignment -name QIP_FILE "../../../../mist-modules/mist.qip"
set_global_assignment -name VERILOG_FILE "../../../../mist-modules/sd_card.v"
set_global_assignment -name SIGNALTAP_FILE output_files/via.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name SIGNALTAP_FILE output_files/via.stp

5
cores/bbc/rtl/bbc.v
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@@ -590,9 +590,8 @@ always @(crtc_ma or crtc_ra or disp_addr_offs)
end
// SOUND
// Convert from 8bit signed to unsigned for MiST DAC
assign AUDIO_L = {~sound_ao[7], sound_ao[6:0], 8'b00000000};
assign AUDIO_R = {~sound_ao[7], sound_ao[6:0], 8'b00000000};
assign AUDIO_L = {sound_ao, 8'b00000000};
assign AUDIO_R = {sound_ao, 8'b00000000};
// VIDPROC
assign vidproc_invert_n = 1'b 1;

14
cores/bbc/rtl/sn76489-1.0/sn76489_attenuator-c.vhd
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@@ -1,14 +0,0 @@
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's SN76489AN.
--
-- $Id: sn76489_attenuator-c.vhd,v 1.2 2005/10/10 22:12:38 arnim Exp $
--
-------------------------------------------------------------------------------
configuration sn76489_attenuator_rtl_c0 of sn76489_attenuator is
for rtl
end for;
end sn76489_attenuator_rtl_c0;

45
cores/bbc/rtl/sn76489-1.0/sn76489_attenuator.vhd
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@@ -45,22 +45,24 @@
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sn76489_attenuator is
port (
attenuation_i : in std_logic_vector(0 to 3);
factor_i : in signed(0 to 1);
product_o : out signed(0 to 7)
factor_i : in std_logic;
product_o : out std_logic_vector(0 to 7)
);
end sn76489_attenuator;
architecture rtl of sn76489_attenuator is
type volume_t is array (natural range 0 to 15) of natural;
constant volume_c : volume_t := (31, 25, 20, 16, 12, 10, 8, 6, 5, 4, 3, 2, 2, 2, 1, 0);
begin
-----------------------------------------------------------------------------
@@ -78,37 +80,8 @@ begin
-- v(0) = 31
-- v(n+1) = v(n) * 0.79432823
--
attenuate: process (attenuation_i,
factor_i)
type volume_t is array (natural range 0 to 15) of natural;
constant volume_c : volume_t :=
(31, 25, 20, 16, 12, 10, 8, 6, 5, 4, 3, 2, 2, 2, 1, 0);
variable attenuation_v : unsigned(attenuation_i'range);
variable volume_v : signed(product_o'range);
begin
attenuation_v := unsigned(attenuation_i);
-- volume look-up table
volume_v := to_signed(volume_c(to_integer(attenuation_v)),
product_o'length);
-- this replaces a multiplier and consumes a bit fewer
-- resources
case to_integer(factor_i) is
when +1 =>
product_o <= volume_v;
when -1 =>
product_o <= -volume_v;
when others =>
product_o <= (others => '0');
end case;
end process attenuate;
--
-----------------------------------------------------------------------------
product_o <= conv_std_logic_vector(volume_c(conv_integer(attenuation_i)), product_o'length) when factor_i = '1'
else (others => '0');
end rtl;

14
cores/bbc/rtl/sn76489-1.0/sn76489_clock_div-c.vhd
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@@ -1,14 +0,0 @@
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's SN76489AN.
--
-- $Id: sn76489_clock_div-c.vhd,v 1.2 2005/10/10 22:12:38 arnim Exp $
--
-------------------------------------------------------------------------------
configuration sn76489_clock_div_rtl_c0 of sn76489_clock_div is
for rtl
end for;
end sn76489_clock_div_rtl_c0;

10
cores/bbc/rtl/sn76489-1.0/sn76489_clock_div.vhd
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@@ -45,7 +45,9 @@
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sn76489_clock_div is
@@ -68,7 +70,7 @@ use ieee.numeric_std.all;
architecture rtl of sn76489_clock_div is
signal cnt_s,
cnt_q : unsigned(3 downto 0);
cnt_q : std_logic_vector(3 downto 0);
begin
@@ -109,9 +111,9 @@ begin
clk_en_o <= true;
if clock_div_16_g = 1 then
cnt_s <= to_unsigned(15, cnt_q'length);
cnt_s <= conv_std_logic_vector(15, cnt_q'length);
elsif clock_div_16_g = 0 then
cnt_s <= to_unsigned( 1, cnt_q'length);
cnt_s <= conv_std_logic_vector( 1, cnt_q'length);
else
-- pragma translate_off
assert false

96
cores/bbc/rtl/sn76489-1.0/sn76489_comp_pack-p.vhd
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@@ -1,96 +0,0 @@
-------------------------------------------------------------------------------
--
-- $Id: sn76489_comp_pack-p.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $
--
-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sn76489_comp_pack is
component sn76489_attenuator
port (
attenuation_i : in std_logic_vector(0 to 3);
factor_i : in signed(0 to 1);
product_o : out signed(0 to 7)
);
end component;
component sn76489_tone
port (
clock_i : in std_logic;
clk_en_i : in boolean;
res_n_i : in std_logic;
we_i : in boolean;
d_i : in std_logic_vector(0 to 7);
r2_i : in std_logic;
ff_o : out std_logic;
tone_o : out signed(0 to 7)
);
end component;
component sn76489_noise
port (
clock_i : in std_logic;
clk_en_i : in boolean;
res_n_i : in std_logic;
we_i : in boolean;
d_i : in std_logic_vector(0 to 7);
r2_i : in std_logic;
tone3_ff_i : in std_logic;
noise_o : out signed(0 to 7)
);
end component;
component sn76489_latch_ctrl
port (
clock_i : in std_logic;
clk_en_i : in boolean;
res_n_i : in std_logic;
ce_n_i : in std_logic;
we_n_i : in std_logic;
d_i : in std_logic_vector(0 to 7);
ready_o : out std_logic;
tone1_we_o : out boolean;
tone2_we_o : out boolean;
tone3_we_o : out boolean;
noise_we_o : out boolean;
r2_o : out std_logic
);
end component;
component sn76489_clock_div
generic (
clock_div_16_g : integer := 1
);
port (
clock_i : in std_logic;
clock_en_i : in std_logic;
res_n_i : in std_logic;
clk_en_o : out boolean
);
end component;
component sn76489_top
generic (
clock_div_16_g : integer := 1
);
port (
clock_i : in std_logic;
clock_en_i : in std_logic;
res_n_i : in std_logic;
ce_n_i : in std_logic;
we_n_i : in std_logic;
ready_o : out std_logic;
d_i : in std_logic_vector(0 to 7);
aout_o : out signed(0 to 7)
);
end component;
end sn76489_comp_pack;

14
cores/bbc/rtl/sn76489-1.0/sn76489_latch_ctrl-c.vhd
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@@ -1,14 +0,0 @@
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's SN76489AN.
--
-- $Id: sn76489_latch_ctrl-c.vhd,v 1.2 2005/10/10 22:12:38 arnim Exp $
--
-------------------------------------------------------------------------------
configuration sn76489_latch_ctrl_rtl_c0 of sn76489_latch_ctrl is
for rtl
end for;
end sn76489_latch_ctrl_rtl_c0;

19
cores/bbc/rtl/sn76489-1.0/sn76489_noise-c.vhd
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@@ -1,19 +0,0 @@
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's SN76489AN.
--
-- $Id: sn76489_noise-c.vhd,v 1.2 2005/10/10 22:12:38 arnim Exp $
--
-------------------------------------------------------------------------------
configuration sn76489_noise_rtl_c0 of sn76489_noise is
for rtl
for attenuator_b : sn76489_attenuator
use configuration work.sn76489_attenuator_rtl_c0;
end for;
end for;
end sn76489_noise_rtl_c0;

40
cores/bbc/rtl/sn76489-1.0/sn76489_noise.vhd
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@@ -45,8 +45,9 @@
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sn76489_noise is
@@ -58,29 +59,25 @@ entity sn76489_noise is
d_i : in std_logic_vector(0 to 7);
r2_i : in std_logic;
tone3_ff_i : in std_logic;
noise_o : out signed(0 to 7)
noise_o : out std_logic_vector(0 to 7)
);
end sn76489_noise;
use work.sn76489_comp_pack.sn76489_attenuator;
architecture rtl of sn76489_noise is
signal nf_q : std_logic_vector(0 to 1);
signal fb_q : std_logic;
signal a_q : std_logic_vector(0 to 3);
signal freq_cnt_q : unsigned(0 to 6);
signal freq_cnt_q : std_logic_vector(0 to 6);
signal freq_ff_q : std_logic;
signal shift_source_s,
shift_source_q : std_logic;
signal shift_rise_edge_s : boolean;
signal lfsr_q : std_logic_vector(0 to 15);
signal freq_s : signed(0 to 1);
signal lfsr_q : std_logic_vector(0 to 14);
begin
@@ -136,11 +133,11 @@ begin
-- reload frequency counter according to NF setting
case nf_q is
when "00" =>
freq_cnt_q <= to_unsigned(16 * 2 - 1, freq_cnt_q'length);
freq_cnt_q <= conv_std_logic_vector(16 * 2 - 1, freq_cnt_q'length);
when "01" =>
freq_cnt_q <= to_unsigned(16 * 4 - 1, freq_cnt_q'length);
freq_cnt_q <= conv_std_logic_vector(16 * 4 - 1, freq_cnt_q'length);
when "10" =>
freq_cnt_q <= to_unsigned(16 * 8 - 1, freq_cnt_q'length);
freq_cnt_q <= conv_std_logic_vector(16 * 8 - 1, freq_cnt_q'length);
when others =>
null;
end case;
@@ -205,9 +202,9 @@ begin
lfsr: process (clock_i, res_n_i)
function lfsr_tapped_f(lfsr : in std_logic_vector) return std_logic is
constant tapped_bits_c : std_logic_vector(0 to 15)
constant tapped_bits_c : std_logic_vector(0 to 14)
-- tapped bits are 0, 2, 15
:= "1010000000000001";
:= "110000000000000";
variable parity_v : std_logic;
begin
parity_v := '0';
@@ -256,25 +253,14 @@ begin
end if;
end if;
end process lfsr;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Map output of LFSR to signed value for attenuator.
-----------------------------------------------------------------------------
freq_s <= to_signed(+1, 2)
when lfsr_q(0) = '1' else
to_signed( 0, 2);
-----------------------------------------------------------------------------
-- The attenuator itself
-----------------------------------------------------------------------------
attenuator_b : sn76489_attenuator
attenuator_b : entity work.sn76489_attenuator
port map (
attenuation_i => a_q,
factor_i => freq_s,
factor_i => lfsr_q(0),
product_o => noise_o
);

19
cores/bbc/rtl/sn76489-1.0/sn76489_tone-c.vhd
View File

@@ -1,19 +0,0 @@
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's SN76489AN.
--
-- $Id: sn76489_tone-c.vhd,v 1.2 2005/10/10 22:12:38 arnim Exp $
--
-------------------------------------------------------------------------------
configuration sn76489_tone_rtl_c0 of sn76489_tone is
for rtl
for attenuator_b : sn76489_attenuator
use configuration work.sn76489_attenuator_rtl_c0;
end for;
end for;
end sn76489_tone_rtl_c0;

41
cores/bbc/rtl/sn76489-1.0/sn76489_tone.vhd
View File

@@ -45,8 +45,9 @@
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sn76489_tone is
@@ -58,22 +59,18 @@ entity sn76489_tone is
d_i : in std_logic_vector(0 to 7);
r2_i : in std_logic;
ff_o : out std_logic;
tone_o : out signed(0 to 7)
tone_o : out std_logic_vector(0 to 7)
);
end sn76489_tone;
use work.sn76489_comp_pack.sn76489_attenuator;
architecture rtl of sn76489_tone is
signal f_q : std_logic_vector(0 to 9);
signal a_q : std_logic_vector(0 to 3);
signal freq_cnt_q : unsigned(0 to 9);
signal freq_cnt_q : std_logic_vector(0 to 9);
signal freq_ff_q : std_logic;
signal freq_s : signed(0 to 1);
signal output_ff : std_logic;
function all_zero(a : in std_logic_vector) return boolean is
variable result_v : boolean;
@@ -137,21 +134,25 @@ begin
if res_n_i = '0' then
freq_cnt_q <= (others => '0');
freq_ff_q <= '0';
output_ff <= '0';
elsif clock_i'event and clock_i = '1' then
if clk_en_i then
if freq_cnt_q = 0 then
if freq_cnt_q = 1 then
-- update counter from frequency register
freq_cnt_q <= unsigned(f_q);
freq_cnt_q <= f_q;
-- and toggle the frequency flip-flop if enabled
if not all_zero(f_q) then
if (f_q > 5) then
freq_ff_q <= not freq_ff_q;
else
-- if frequency setting is 0, then keep flip-flop at +1
freq_ff_q <= '1';
end if;
-- either way toggle the output_ff - this is used to clock noise
output_ff <= not output_ff;
else
-- decrement frequency counter
freq_cnt_q <= freq_cnt_q - 1;
@@ -160,25 +161,15 @@ begin
end if;
end if;
end process freq_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Map frequency flip-flop to signed value for attenuator.
-----------------------------------------------------------------------------
freq_s <= to_signed(+1, 2)
when freq_ff_q = '1' else
to_signed(-1, 2);
-----------------------------------------------------------------------------
-- The attenuator itself
-----------------------------------------------------------------------------
attenuator_b : sn76489_attenuator
attenuator_b : entity work.sn76489_attenuator
port map (
attenuation_i => a_q,
factor_i => freq_s,
factor_i => freq_ff_q,
product_o => tone_o
);
@@ -186,6 +177,6 @@ begin
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
ff_o <= freq_ff_q;
ff_o <= output_ff;
end rtl;

31
cores/bbc/rtl/sn76489-1.0/sn76489_top-c.vhd
View File

@@ -1,31 +0,0 @@
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's SN76489AN.
--
-- $Id: sn76489_top-c.vhd,v 1.3 2005/10/10 22:12:38 arnim Exp $
--
-------------------------------------------------------------------------------
configuration sn76489_top_struct_c0 of sn76489_top is
for struct
for clock_div_b : sn76489_clock_div
use configuration work.sn76489_clock_div_rtl_c0;
end for;
for latch_ctrl_b : sn76489_latch_ctrl
use configuration work.sn76489_latch_ctrl_rtl_c0;
end for;
for all : sn76489_tone
use configuration work.sn76489_tone_rtl_c0;
end for;
for noise_b : sn76489_noise
use configuration work.sn76489_noise_rtl_c0;
end for;
end for;
end sn76489_top_struct_c0;

34
cores/bbc/rtl/sn76489-1.0/sn76489_top.vhd
View File

@@ -56,8 +56,9 @@
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sn76489_top is
@@ -72,7 +73,7 @@ entity sn76489_top is
we_n_i : in std_logic;
ready_o : out std_logic;
d_i : in std_logic_vector(0 to 7);
aout_o : out signed(0 to 7)
aout_o : out std_logic_vector(0 to 7)
);
end sn76489_top;
@@ -80,7 +81,6 @@ end sn76489_top;
library ieee;
use ieee.numeric_std.all;
use work.sn76489_comp_pack.all;
architecture struct of sn76489_top is
@@ -95,7 +95,7 @@ architecture struct of sn76489_top is
signal tone1_s,
tone2_s,
tone3_s,
noise_s : signed(0 to 7);
noise_s : std_logic_vector(0 to 7);
signal tone3_ff_s : std_logic;
@@ -104,7 +104,7 @@ begin
-----------------------------------------------------------------------------
-- Clock Divider
-----------------------------------------------------------------------------
clock_div_b : sn76489_clock_div
clock_div_b : entity work.sn76489_clock_div
generic map (
clock_div_16_g => clock_div_16_g
)
@@ -119,7 +119,7 @@ begin
-----------------------------------------------------------------------------
-- Latch Control = CPU Interface
-----------------------------------------------------------------------------
latch_ctrl_b : sn76489_latch_ctrl
latch_ctrl_b : entity work.sn76489_latch_ctrl
port map (
clock_i => clock_i,
clk_en_i => clk_en_s,
@@ -139,7 +139,7 @@ begin
-----------------------------------------------------------------------------
-- Tone Channel 1
-----------------------------------------------------------------------------
tone1_b : sn76489_tone
tone1_b : entity work.sn76489_tone
port map (
clock_i => clock_i,
clk_en_i => clk_en_s,
@@ -154,7 +154,7 @@ begin
-----------------------------------------------------------------------------
-- Tone Channel 2
-----------------------------------------------------------------------------
tone2_b : sn76489_tone
tone2_b : entity work.sn76489_tone
port map (
clock_i => clock_i,
clk_en_i => clk_en_s,
@@ -169,7 +169,7 @@ begin
-----------------------------------------------------------------------------
-- Tone Channel 3
-----------------------------------------------------------------------------
tone3_b : sn76489_tone
tone3_b : entity work.sn76489_tone
port map (
clock_i => clock_i,
clk_en_i => clk_en_s,
@@ -184,7 +184,7 @@ begin
-----------------------------------------------------------------------------
-- Noise Channel
-----------------------------------------------------------------------------
noise_b : sn76489_noise
noise_b : entity work.sn76489_noise
port map (
clock_i => clock_i,
clk_en_i => clk_en_s,
@@ -196,15 +196,7 @@ begin
noise_o => noise_s
);
-- Register output
process(clock_i)
begin
if res_n_i = '0' then
aout_o <= (others => '0');
elsif rising_edge(clock_i) then
aout_o <= tone1_s + tone2_s + tone3_s + noise_s;
end if;
end process;
aout_o <= tone1_s + tone2_s + tone3_s + noise_s;
end struct;