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[TG68K] bfextu flag regression fix
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@@ -178,6 +178,7 @@ architecture logic of TG68K_ALU IS
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signal bf_bchg : std_logic;
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signal bf_ins : std_logic;
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signal bf_exts : std_logic;
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signal bf_extu : std_logic;
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signal bf_fffo : std_logic;
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signal bf_d32 : std_logic;
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signal index : std_logic_vector(4 downto 0);
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@@ -452,7 +453,7 @@ begin
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-- contents as with bfset, bfclr or bfchg
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process (clk, mux, mask, bitnr, bf_ins, bf_bchg, bf_bset, bf_exts, bf_shift, inmux0, inmux1, inmux2, inmux3, bf_set2, OP1out, OP2out, result_tmp, bf_ext_in,
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process (clk, mux, mask, bitnr, bf_ins, bf_bchg, bf_bset, bf_exts, bf_extu, bf_shift, inmux0, inmux1, inmux2, inmux3, bf_set2, OP1out, OP2out, result_tmp, bf_ext_in,
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shift, datareg, bf_NFlag, result, reg_QB, sign, bf_d32, copy, bf_loffset, copymux0, copymux1, copymux2, copymux3, bf_width)
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begin
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if rising_edge(clk) then
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@@ -461,11 +462,13 @@ process (clk, mux, mask, bitnr, bf_ins, bf_bchg, bf_bset, bf_exts, bf_shift, inm
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bf_bchg <= '0';
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bf_ins <= '0';
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bf_exts <= '0';
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bf_extu <= '0';
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bf_fffo <= '0';
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bf_d32 <= '0';
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case opcode(10 downto 8) IS
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when "010" => bf_bchg <= '1'; --BFCHG
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when "011" => bf_exts <= '1'; --BFEXTS
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when "001" => bf_extu <= '1'; --BFEXTU
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-- when "100" => insert <= (others =>'0'); --BFCLR
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when "101" => bf_fffo <= '1'; --BFFFO
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when "110" => bf_bset <= '1'; --BFSET
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@@ -813,12 +816,13 @@ process (clk, Reset, exe_opcode, exe_datatype, Flags, last_data_read, OP2out, fl
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Flags(1 downto 0) <= "00";
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Flags(3 downto 2) <= set_flags(3 downto 2);
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if exec(opcBF) = '1' then
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-- flags(2) has correctly been set from set_flags
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Flags(3) <= bf_NFlag;
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--TH TODO: check flag handling of fffo and exts
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--TH TODO: check flag handling of fffo
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-- "normal" flags are taken from
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if bf_fffo = '0' and bf_exts='0' and bf_ins='0' then
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-- "normal" flags are taken from op2in
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if bf_fffo = '0' and bf_extu='0' and bf_exts='0' and bf_ins='0' then
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Flags(2) <= bf_flag_z;
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Flags(3) <= bf_flag_n;
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end if;
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