github.com/mist-devel.mist-board
1
0
Fork 0
mirror of https://github.com/mist-devel/mist-board.git synced 2026-02-26 00:04:08 +00:00
Code Issues Releases Wiki Activity

C16: use only the T65 CPU

Browse Source
This commit is contained in:
Gyorgy Szombathelyi
2018-08-30 19:18:18 +02:00
parent 4b831fb5ab
commit b4cb72ec49
4 changed files with 20 additions and 1636 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
cores/c16/c16_mist.qsf
View File

@@ -323,6 +323,7 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0
set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VHDL_FILE gen_ram.vhd
set_global_assignment -name QIP_FILE pll_ntsc.qip
set_global_assignment -name QIP_FILE pll_pal.qip
@@ -330,8 +331,6 @@ set_global_assignment -name VERILOG_FILE data_io.v
set_global_assignment -name VERILOG_FILE sdram.v
set_global_assignment -name VERILOG_FILE osd.v
set_global_assignment -name VERILOG_FILE scandoubler.v
set_global_assignment -name VHDL_FILE cpu65xx_fast.vhd
set_global_assignment -name VHDL_FILE cpu65xx_e.vhd
set_global_assignment -name VERILOG_FILE user_io.v
set_global_assignment -name VERILOG_FILE ted.v
set_global_assignment -name VERILOG_FILE mos8501.v
@@ -354,5 +353,4 @@ set_global_assignment -name SYSTEMVERILOG_FILE c1541/mist_sd_card.sv
set_global_assignment -name VHDL_FILE t65/T65_Pack.vhd
set_global_assignment -name VHDL_FILE t65/T65_MCode.vhd
set_global_assignment -name VHDL_FILE t65/T65_ALU.vhd
set_global_assignment -name VHDL_FILE t65/T65.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VHDL_FILE t65/T65.vhd

48
cores/c16/cpu65xx_e.vhd
View File

@@ -1,48 +0,0 @@
-- -----------------------------------------------------------------------
--
-- FPGA 64
--
-- A fully functional commodore 64 implementation in a single FPGA
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
-- -----------------------------------------------------------------------
--
-- Interface to 6502/6510 core
--
-- -----------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity cpu65xx is
generic (
pipelineOpcode : boolean;
pipelineAluMux : boolean;
pipelineAluOut : boolean
);
port (
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
nmi_n : in std_logic;
irq_n : in std_logic;
so_n : in std_logic := '1';
di : in unsigned(7 downto 0);
do : out unsigned(7 downto 0);
addr : out unsigned(15 downto 0);
we : out std_logic;
debugOpcode : out unsigned(7 downto 0);
debugPc : out unsigned(15 downto 0);
debugA : out unsigned(7 downto 0);
debugX : out unsigned(7 downto 0);
debugY : out unsigned(7 downto 0);
debugS : out unsigned(7 downto 0)
);
end cpu65xx;

1565
cores/c16/cpu65xx_fast.vhd
View File

File diff suppressed because it is too large Load Diff

37
cores/c16/mos8501.v
View File

@@ -59,26 +59,25 @@ reg [7:0] port_data=8'b0;
reg rw_reg,aec_reg;
// 6502 CPU core
wire we_n;
assign we = ~we_n;
cpu65xx #(.pipelineOpcode("\false"),.pipelineAluMux("\false"),.pipelineAluOut("\false"))
cpu_core(
.clk(clk),
.reset(reset),
.enable(enable_cpu),
.nmi_n(1'b1),
.irq_n(irq_n),
.di(core_data_in),
.do(core_data_out),
.addr(core_address),
.we(we),
.so_n(1'b1),
.debugOpcode(),
.debugPc(),
.debugA(),
.debugX(),
.debugY(),
.debugS()
);
T65 cpu_core(
.Mode (2'b00),
.Res_n (~reset),
.Enable(enable_cpu),
.Clk(clk),
.Rdy(enable_cpu),
.Abort_n(1),
.IRQ_n(irq_n),
.NMI_n(1),
.SO_n(1),
.R_w_n(we_n),
.A(core_address),
.DI(core_data_in),
.DO(core_data_out)
);
assign address=(aec)?core_address:16'hffff; // address tri state emulated for easy bus signal combining