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Code Issues Releases Wiki Activity

Thanks, Gideon!

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This commit is contained in:
Gyorgy Szombathelyi
2020-05-21 21:25:43 +02:00
parent 1920675a8f
commit c5eb1db7e9
3 changed files with 85 additions and 68 deletions
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15
cores/bbc/rtl/via6522.vhd
View File

@@ -1,17 +1,15 @@
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2007-2017, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : VIA 6522
-------------------------------------------------------------------------------
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: This module implements the 6522 VIA chip.
-- Please note: A LOT OF REVERSE ENGINEERING has been done to
-- make this module as accurate as it is now. Please do not copy
-- (use in your own projects) without written permission of the
-- author.
-- A LOT OF REVERSE ENGINEERING has been done to make this module
-- as accurate as it is now. Thanks to gyurco for ironing out some
-- differences that were left unnoticed.
-------------------------------------------------------------------------------
-- License: GPL 3.0 - Free to use, distribute and change to your own needs.
-- Leaving a reference to the author will be highly appreciated.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
@@ -704,3 +702,4 @@ begin
end process;
end block ser;
end Gideon;

15
cores/c16/c1541/via6522.vhd
View File

@@ -1,17 +1,15 @@
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2007-2017, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : VIA 6522
-------------------------------------------------------------------------------
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: This module implements the 6522 VIA chip.
-- Please note: A LOT OF REVERSE ENGINEERING has been done to
-- make this module as accurate as it is now. Please do not copy
-- (use in your own projects) without written permission of the
-- author.
-- A LOT OF REVERSE ENGINEERING has been done to make this module
-- as accurate as it is now. Thanks to gyurco for ironing out some
-- differences that were left unnoticed.
-------------------------------------------------------------------------------
-- License: GPL 3.0 - Free to use, distribute and change to your own needs.
-- Leaving a reference to the author will be highly appreciated.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
@@ -704,3 +702,4 @@ begin
end process;
end block ser;
end Gideon;

123
cores/c64/rtl/c1541/via6522.vhd
View File

@@ -1,17 +1,15 @@
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2007-2017, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : VIA 6522
-------------------------------------------------------------------------------
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: This module implements the 6522 VIA chip.
-- Please note: A LOT OF REVERSE ENGINEERING has been done to
-- make this module as accurate as it is now. Please do not copy
-- (use in your own projects) without written permission of the
-- author.
-- A LOT OF REVERSE ENGINEERING has been done to make this module
-- as accurate as it is now. Thanks to gyurco for ironing out some
-- differences that were left unnoticed.
-------------------------------------------------------------------------------
-- License: GPL 3.0 - Free to use, distribute and change to your own needs.
-- Leaving a reference to the author will be highly appreciated.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
@@ -97,8 +95,11 @@ architecture Gideon of via6522 is
signal serport_en : std_logic;
signal ser_cb2_o : std_logic;
signal hs_cb2_o : std_logic;
signal trigger_serial: std_logic;
signal cb1_t_int : std_logic;
signal cb1_o_int : std_logic;
signal cb2_t_int : std_logic;
signal cb2_o_int : std_logic;
alias ca2_event : std_logic is irq_events(0);
alias ca1_event : std_logic is irq_events(1);
alias serial_event : std_logic is irq_events(2);
@@ -165,8 +166,13 @@ begin
cb2_event <= (cb2_c xor cb2_d) and (cb2_d xor cb2_edge_select);
ca2_t <= ca2_is_output;
cb2_t <= cb2_is_output when serport_en='0' else shift_dir;
cb2_o <= hs_cb2_o when serport_en='0' else ser_cb2_o;
cb2_t_int <= cb2_is_output when serport_en='0' else shift_dir;
cb2_o_int <= hs_cb2_o when serport_en='0' else ser_cb2_o;
cb1_t <= cb1_t_int;
cb1_o <= cb1_o_int;
cb2_t <= cb2_t_int;
cb2_o <= cb2_o_int;
with ca2_out_mode select ca2_o <=
ca2_handshake_o when "00",
@@ -207,8 +213,16 @@ begin
-- CA1/CA2/CB1/CB2 edge detect flipflops
ca1_c <= To_X01(ca1_i);
ca2_c <= To_X01(ca2_i);
cb1_c <= To_X01(cb1_i);
cb2_c <= To_X01(cb2_i);
if cb1_t_int = '0' then
cb1_c <= To_X01(cb1_i);
else
cb1_c <= cb1_o_int;
end if;
if cb2_t_int = '0' then
cb2_c <= To_X01(cb2_i);
else
cb2_c <= cb2_o_int;
end if;
ca1_d <= ca1_c;
ca2_d <= ca2_c;
@@ -261,10 +275,6 @@ begin
-- Interrupt logic
irq_flags <= irq_flags or irq_events;
if falling = '1' then
trigger_serial <= '0';
end if;
-- Writes --
if wen='1' and falling = '1' then
last_data <= data_in;
@@ -311,9 +321,6 @@ begin
when X"A" => -- Serial port
serial_flag <= '0';
if shift_active = '0' then
trigger_serial <= '1';
end if;
when X"B" => -- ACR (Auxiliary Control Register)
acr <= data_in;
@@ -405,7 +412,6 @@ begin
when X"A" => -- SR
serial_flag <= '0';
trigger_serial <= '1';
when others =>
null;
@@ -424,7 +430,6 @@ begin
cb2_pulse_o <= '1';
timer_a_latch <= latch_reset_pattern;
timer_b_latch <= latch_reset_pattern;
trigger_serial <= '0';
end if;
end if;
end process;
@@ -567,41 +572,56 @@ begin
end block tmr_b;
ser: block
signal trigger_serial: std_logic;
signal shift_clock_d : std_logic;
signal shift_clock : std_logic;
signal shift_tick_r : std_logic;
signal shift_tick_f : std_logic;
signal shift_timer_tick : std_logic;
signal cb2_c : std_logic := '0';
signal bit_cnt : integer range 0 to 7;
signal shift_pulse : std_logic;
begin
process(shift_active, timer_b_tick, shift_clk_sel, shift_clock, shift_clock_d)
process(shift_active, timer_b_tick, shift_clk_sel, shift_clock, shift_clock_d, shift_timer_tick)
begin
case shift_clk_sel is
when "10" =>
shift_pulse <= '1';
when "00"|"01" =>
shift_pulse <= timer_b_tick;
shift_pulse <= shift_timer_tick;
when others =>
shift_pulse <= shift_clock and not shift_clock_d;
end case;
if shift_active = '0' then
shift_pulse <= '0';
-- Mode 0 still loads the shift register to external pulse (MMBEEB SD-Card interface uses this)
if shift_mode_control = "000" then
shift_pulse <= shift_clock and not shift_clock_d;
else
shift_pulse <= '0';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
cb2_c <= To_X01(cb2_i);
if rising = '1' then
cb2_c <= To_X01(cb2_i);
if shift_active='0' then
shift_clock <= '1';
if shift_mode_control = "000" then
shift_clock <= To_X01(cb1_i);
else
shift_clock <= '1';
end if;
elsif shift_clk_sel = "11" then
shift_clock <= To_X01(cb1_i);
elsif shift_pulse = '1' then
@@ -610,55 +630,53 @@ begin
shift_clock_d <= shift_clock;
if shift_tick_f = '1' then
ser_cb2_o <= shift_reg(7);
end if;
end if;
if falling = '1' then
shift_timer_tick <= timer_b_tick;
end if;
if reset = '1' then
shift_clock <= '1';
shift_clock_d <= '1';
ser_cb2_o <= '1';
end if;
end if;
end process;
cb1_t <= '0' when shift_clk_sel="11" else serport_en;
cb1_o <= shift_clock_d;
cb1_t_int <= '0' when shift_clk_sel="11" else serport_en;
cb1_o_int <= shift_clock_d;
ser_cb2_o <= shift_reg(7);
serport_en <= shift_dir or shift_clk_sel(1) or shift_clk_sel(0);
trigger_serial <= '1' when (ren='1' or wen='1') and addr=x"A" else '0';
shift_tick_r <= not shift_clock_d and shift_clock;
shift_tick_f <= shift_clock_d and not shift_clock;
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
shift_reg <= X"FF";
shift_tick_r <= '0';
shift_tick_f <= '0';
elsif falling = '1' then
shift_tick_r <= not shift_clock_d and shift_clock;
shift_tick_f <= shift_clock_d and not shift_clock;
if wen = '1' and addr = X"A" then
shift_reg <= data_in;
elsif shift_tick_r = '1' then
if shift_dir='1' then -- output
shift_reg <= shift_reg(6 downto 0) & shift_reg(7);
else
shift_reg <= shift_reg(6 downto 0) & cb2_c;
end if;
elsif shift_dir='1' and shift_tick_f = '1' then -- output
shift_reg <= shift_reg(6 downto 0) & shift_reg(7);
elsif shift_dir='0' and shift_tick_r = '1' then -- input
shift_reg <= shift_reg(6 downto 0) & cb2_c;
end if;
end if;
end if;
end process;
-- tell people that we're ready!
serial_event <= shift_tick_r and not shift_active and rising;
serial_event <= shift_tick_r and not shift_active and rising and serport_en;
process(clock)
begin
if rising_edge(clock) then
if falling = '1' then
if shift_active = '0' then
if shift_active = '0' and shift_mode_control /= "000" then
if trigger_serial = '1' then
bit_cnt <= 7;
shift_active <= '1';
@@ -675,7 +693,7 @@ begin
end if;
end if;
end if;
if reset='1' then
shift_active <= '0';
bit_cnt <= 0;
@@ -684,3 +702,4 @@ begin
end process;
end block ser;
end Gideon;