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Code Issues Releases Wiki Activity

Unify T65 versions

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This commit is contained in:
Gyorgy Szombathelyi
2020-05-18 22:57:34 +02:00
parent d4b9591cd2
commit c9a10cfe16
16 changed files with 813 additions and 738 deletions
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22
cores/bbc/rtl/T65/T65.vhd Executable file → Normal file
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@@ -134,14 +134,16 @@ library IEEE;
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
BCD_en : in std_logic := '1'; -- '0' => 2A03/2A07, '1' => others
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
Rdy : in std_logic := '1';
Abort_n : in std_logic := '1';
IRQ_n : in std_logic := '1';
NMI_n : in std_logic := '1';
SO_n : in std_logic := '1';
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
@@ -157,7 +159,7 @@ entity T65 is
-- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB)
Regs : out std_logic_vector(63 downto 0);
DEBUG : out T_t65_dbg;
NMI_ack : out std_logic
NMI_ack : out std_logic
);
end T65;
@@ -183,6 +185,7 @@ architecture rtl of T65 is
signal DO_r : std_logic_vector(7 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal BCD_en_r : std_logic;
signal ALU_Op_r : T_ALU_Op;
signal Write_Data_r : T_Write_Data;
signal Set_Addr_To_r : T_Set_Addr_To;
@@ -245,8 +248,8 @@ architecture rtl of T65 is
signal NMI_entered : std_logic;
begin
NMI_ack <= NMIAct;
NMI_ack <= NMIAct;
-- gate Rdy with read/write to make an "OK, it's really OK to stop the processor
really_rdy <= Rdy or not(WRn_i);
Sync <= '1' when MCycle = "000" else '0';
@@ -309,6 +312,7 @@ begin
alu : entity work.T65_ALU
port map(
Mode => Mode_r,
BCD_en => BCD_en_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
@@ -340,6 +344,7 @@ begin
DBR <= (others => '0');
Mode_r <= (others => '0');
BCD_en_r <= '1';
ALU_Op_r <= ALU_OP_BIT;
Write_Data_r <= Write_Data_DL;
Set_Addr_To_r <= Set_Addr_To_PBR;
@@ -369,6 +374,7 @@ begin
if MCycle = "000" then
Mode_r <= Mode;
BCD_en_r <= BCD_en;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;

19
cores/bbc/rtl/T65/T65_ALU.vhd Executable file → Normal file
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@@ -57,6 +57,7 @@ use work.T65_Pack.all;
entity T65_ALU is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
BCD_en : in std_logic;
Op : in T_ALU_OP;
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
@@ -83,7 +84,7 @@ architecture rtl of T65_ALU is
begin
process (P_In, BusA, BusB)
process (P_In, BusA, BusB, BCD_en)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(6 downto 0);
variable C : std_logic;
@@ -102,7 +103,7 @@ begin
ADC_Z <= '0';
end if;
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' and BCD_en = '1' then
AL(6 downto 1) := AL(6 downto 1) + 6;
end if;
@@ -116,7 +117,7 @@ begin
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' and BCD_en = '1' then
AH(6 downto 1) := AH(6 downto 1) + 6;
end if;
@@ -125,7 +126,7 @@ begin
ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB)
process (Op, P_In, BusA, BusB, BCD_en)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(5 downto 0);
variable C : std_logic;
@@ -165,7 +166,7 @@ begin
SBX_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
if P_In(Flag_D) = '1' then
if P_In(Flag_D) = '1' and BCD_en = '1' then
if AL(5) = '1' then
AL(5 downto 1) := AL(5 downto 1) - 6;
end if;
@@ -180,15 +181,15 @@ begin
process (Op, P_In, BusA, BusB,
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q,
SBX_Q)
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q,
SBX_Q, BCD_en)
variable Q_t : std_logic_vector(7 downto 0);
variable Q2_t : std_logic_vector(7 downto 0);
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
P_Out <= P_In;
Q_t := BusA;
Q_t := BusA;
Q2_t := BusA;
case Op is
when ALU_OP_OR=>
@@ -226,7 +227,7 @@ begin
Q_t := P_In(Flag_C) & (BusA(7 downto 1) and BusB(7 downto 1));
P_Out(Flag_V) <= Q_t(5) xor Q_t(6);
Q2_t := Q_t;
if P_In(Flag_D)='1' then
if P_In(Flag_D)='1' and BCD_en = '1' then
if (BusA(3 downto 0) and BusB(3 downto 0)) > "0100" then
Q2_t(3 downto 0) := std_logic_vector(unsigned(Q_t(3 downto 0)) + x"6");
end if;

0
cores/bbc/rtl/T65/T65_MCode.vhd Executable file → Normal file
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0
cores/bbc/rtl/T65/T65_Pack.vhd Executable file → Normal file
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22
cores/c16/t65/T65.vhd Executable file → Normal file
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@@ -134,14 +134,16 @@ library IEEE;
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
BCD_en : in std_logic := '1'; -- '0' => 2A03/2A07, '1' => others
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
Rdy : in std_logic := '1';
Abort_n : in std_logic := '1';
IRQ_n : in std_logic := '1';
NMI_n : in std_logic := '1';
SO_n : in std_logic := '1';
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
@@ -157,7 +159,7 @@ entity T65 is
-- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB)
Regs : out std_logic_vector(63 downto 0);
DEBUG : out T_t65_dbg;
NMI_ack : out std_logic
NMI_ack : out std_logic
);
end T65;
@@ -183,6 +185,7 @@ architecture rtl of T65 is
signal DO_r : std_logic_vector(7 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal BCD_en_r : std_logic;
signal ALU_Op_r : T_ALU_Op;
signal Write_Data_r : T_Write_Data;
signal Set_Addr_To_r : T_Set_Addr_To;
@@ -245,8 +248,8 @@ architecture rtl of T65 is
signal NMI_entered : std_logic;
begin
NMI_ack <= NMIAct;
NMI_ack <= NMIAct;
-- gate Rdy with read/write to make an "OK, it's really OK to stop the processor
really_rdy <= Rdy or not(WRn_i);
Sync <= '1' when MCycle = "000" else '0';
@@ -309,6 +312,7 @@ begin
alu : entity work.T65_ALU
port map(
Mode => Mode_r,
BCD_en => BCD_en_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
@@ -340,6 +344,7 @@ begin
DBR <= (others => '0');
Mode_r <= (others => '0');
BCD_en_r <= '1';
ALU_Op_r <= ALU_OP_BIT;
Write_Data_r <= Write_Data_DL;
Set_Addr_To_r <= Set_Addr_To_PBR;
@@ -369,6 +374,7 @@ begin
if MCycle = "000" then
Mode_r <= Mode;
BCD_en_r <= BCD_en;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;

19
cores/c16/t65/T65_ALU.vhd Executable file → Normal file
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@@ -57,6 +57,7 @@ use work.T65_Pack.all;
entity T65_ALU is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
BCD_en : in std_logic;
Op : in T_ALU_OP;
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
@@ -83,7 +84,7 @@ architecture rtl of T65_ALU is
begin
process (P_In, BusA, BusB)
process (P_In, BusA, BusB, BCD_en)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(6 downto 0);
variable C : std_logic;
@@ -102,7 +103,7 @@ begin
ADC_Z <= '0';
end if;
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' and BCD_en = '1' then
AL(6 downto 1) := AL(6 downto 1) + 6;
end if;
@@ -116,7 +117,7 @@ begin
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' and BCD_en = '1' then
AH(6 downto 1) := AH(6 downto 1) + 6;
end if;
@@ -125,7 +126,7 @@ begin
ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB)
process (Op, P_In, BusA, BusB, BCD_en)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(5 downto 0);
variable C : std_logic;
@@ -165,7 +166,7 @@ begin
SBX_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
if P_In(Flag_D) = '1' then
if P_In(Flag_D) = '1' and BCD_en = '1' then
if AL(5) = '1' then
AL(5 downto 1) := AL(5 downto 1) - 6;
end if;
@@ -180,15 +181,15 @@ begin
process (Op, P_In, BusA, BusB,
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q,
SBX_Q)
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q,
SBX_Q, BCD_en)
variable Q_t : std_logic_vector(7 downto 0);
variable Q2_t : std_logic_vector(7 downto 0);
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
P_Out <= P_In;
Q_t := BusA;
Q_t := BusA;
Q2_t := BusA;
case Op is
when ALU_OP_OR=>
@@ -226,7 +227,7 @@ begin
Q_t := P_In(Flag_C) & (BusA(7 downto 1) and BusB(7 downto 1));
P_Out(Flag_V) <= Q_t(5) xor Q_t(6);
Q2_t := Q_t;
if P_In(Flag_D)='1' then
if P_In(Flag_D)='1' and BCD_en = '1' then
if (BusA(3 downto 0) and BusB(3 downto 0)) > "0100" then
Q2_t(3 downto 0) := std_logic_vector(unsigned(Q_t(3 downto 0)) + x"6");
end if;

0
cores/c16/t65/T65_MCode.vhd Executable file → Normal file
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0
cores/c16/t65/T65_Pack.vhd Executable file → Normal file
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22
cores/c64/rtl/t65/T65.vhd Executable file → Normal file
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@@ -134,14 +134,16 @@ library IEEE;
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
BCD_en : in std_logic := '1'; -- '0' => 2A03/2A07, '1' => others
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
Rdy : in std_logic := '1';
Abort_n : in std_logic := '1';
IRQ_n : in std_logic := '1';
NMI_n : in std_logic := '1';
SO_n : in std_logic := '1';
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
@@ -157,7 +159,7 @@ entity T65 is
-- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB)
Regs : out std_logic_vector(63 downto 0);
DEBUG : out T_t65_dbg;
NMI_ack : out std_logic
NMI_ack : out std_logic
);
end T65;
@@ -183,6 +185,7 @@ architecture rtl of T65 is
signal DO_r : std_logic_vector(7 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal BCD_en_r : std_logic;
signal ALU_Op_r : T_ALU_Op;
signal Write_Data_r : T_Write_Data;
signal Set_Addr_To_r : T_Set_Addr_To;
@@ -245,8 +248,8 @@ architecture rtl of T65 is
signal NMI_entered : std_logic;
begin
NMI_ack <= NMIAct;
NMI_ack <= NMIAct;
-- gate Rdy with read/write to make an "OK, it's really OK to stop the processor
really_rdy <= Rdy or not(WRn_i);
Sync <= '1' when MCycle = "000" else '0';
@@ -309,6 +312,7 @@ begin
alu : entity work.T65_ALU
port map(
Mode => Mode_r,
BCD_en => BCD_en_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
@@ -340,6 +344,7 @@ begin
DBR <= (others => '0');
Mode_r <= (others => '0');
BCD_en_r <= '1';
ALU_Op_r <= ALU_OP_BIT;
Write_Data_r <= Write_Data_DL;
Set_Addr_To_r <= Set_Addr_To_PBR;
@@ -369,6 +374,7 @@ begin
if MCycle = "000" then
Mode_r <= Mode;
BCD_en_r <= BCD_en;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;

19
cores/c64/rtl/t65/T65_ALU.vhd Executable file → Normal file
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@@ -57,6 +57,7 @@ use work.T65_Pack.all;
entity T65_ALU is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
BCD_en : in std_logic;
Op : in T_ALU_OP;
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
@@ -83,7 +84,7 @@ architecture rtl of T65_ALU is
begin
process (P_In, BusA, BusB)
process (P_In, BusA, BusB, BCD_en)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(6 downto 0);
variable C : std_logic;
@@ -102,7 +103,7 @@ begin
ADC_Z <= '0';
end if;
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' and BCD_en = '1' then
AL(6 downto 1) := AL(6 downto 1) + 6;
end if;
@@ -116,7 +117,7 @@ begin
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' and BCD_en = '1' then
AH(6 downto 1) := AH(6 downto 1) + 6;
end if;
@@ -125,7 +126,7 @@ begin
ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB)
process (Op, P_In, BusA, BusB, BCD_en)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(5 downto 0);
variable C : std_logic;
@@ -165,7 +166,7 @@ begin
SBX_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
if P_In(Flag_D) = '1' then
if P_In(Flag_D) = '1' and BCD_en = '1' then
if AL(5) = '1' then
AL(5 downto 1) := AL(5 downto 1) - 6;
end if;
@@ -180,15 +181,15 @@ begin
process (Op, P_In, BusA, BusB,
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q,
SBX_Q)
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q,
SBX_Q, BCD_en)
variable Q_t : std_logic_vector(7 downto 0);
variable Q2_t : std_logic_vector(7 downto 0);
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
P_Out <= P_In;
Q_t := BusA;
Q_t := BusA;
Q2_t := BusA;
case Op is
when ALU_OP_OR=>
@@ -226,7 +227,7 @@ begin
Q_t := P_In(Flag_C) & (BusA(7 downto 1) and BusB(7 downto 1));
P_Out(Flag_V) <= Q_t(5) xor Q_t(6);
Q2_t := Q_t;
if P_In(Flag_D)='1' then
if P_In(Flag_D)='1' and BCD_en = '1' then
if (BusA(3 downto 0) and BusB(3 downto 0)) > "0100" then
Q2_t(3 downto 0) := std_logic_vector(unsigned(Q_t(3 downto 0)) + x"6");
end if;

0
cores/c64/rtl/t65/T65_MCode.vhd Executable file → Normal file
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0
cores/c64/rtl/t65/T65_Pack.vhd Executable file → Normal file
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1386
cores/nes/src/t65/T65.vhd
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File diff suppressed because it is too large Load Diff

2
cores/nes/src/t65/T65_ALU.vhd
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@@ -190,7 +190,7 @@ begin
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
P_Out <= P_In;
Q_t := BusA;
Q2_t := Q_t;
Q2_t := BusA;
case Op is
when ALU_OP_OR=>
Q_t := BusA or BusB;

36
cores/nes/src/t65/T65_MCode.vhd
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@@ -61,6 +61,7 @@ entity T65_MCode is
IR : in std_logic_vector(7 downto 0);
MCycle : in T_Lcycle;
P : in std_logic_vector(7 downto 0);
Rdy_mod : in std_logic;
LCycle : out T_Lcycle;
ALU_Op : out T_ALU_Op;
Set_BusA_To : out T_Set_BusA_To; -- DI,A,X,Y,S,P,DA,DAO,DAX,AAX
@@ -68,6 +69,7 @@ entity T65_MCode is
Write_Data : out T_Write_Data; -- DL,A,X,Y,S,P,PCL,PCH,AX,AXB,XB,YB
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BAQuirk : out std_logic_vector(1 downto 0); -- None,And,Copy
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
@@ -106,7 +108,7 @@ begin
not P(Flag_Z) when "110",
P(Flag_Z) when others;
process (IR, MCycle, P, Branch, Mode)
process (IR, MCycle, P, Branch, Mode, Rdy_mod)
begin
lCycle <= Cycle_1;
Set_BusA_To <= Set_BusA_To_ABC;
@@ -114,6 +116,7 @@ begin
Write_Data <= Write_Data_DL;
Jump <= (others => '0');
BAAdd <= "00";
BAQuirk <= "00";
BreakAtNA <= '0';
ADAdd <= '0';
PCAdd <= '0';
@@ -140,14 +143,22 @@ begin
when "00" => -- IR: $80,$84,$88,$8C,$90,$94,$98,$9C
Set_BusA_To <= Set_BusA_To_Y;
if IR(4 downto 2)="111" then -- SYA ($9C)
Write_Data <= Write_Data_YB;
if Rdy_mod = '0' then
Write_Data <= Write_Data_YB;
else
Write_Data <= Write_Data_Y;
end if;
else
Write_Data <= Write_Data_Y;
end if;
when "10" => -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E
Set_BusA_To <= Set_BusA_To_X;
if IR(4 downto 2)="111" then -- SXA ($9E)
Write_Data <= Write_Data_XB;
if Rdy_mod = '0' then
Write_Data <= Write_Data_XB;
else
Write_Data <= Write_Data_X;
end if;
else
Write_Data <= Write_Data_X;
end if;
@@ -159,7 +170,11 @@ begin
Set_BusA_To <= Set_BusA_To_ABC;
end if;
if IR(4 downto 2)="111" or IR(4 downto 2)="110" or IR(4 downto 2)="100" then -- SHA ($9F, $93), SHS ($9B)
Write_Data <= Write_Data_AXB;
if Rdy_mod = '0' then
Write_Data <= Write_Data_AXB;
else
Write_Data <= Write_Data_AX;
end if;
else
Write_Data <= Write_Data_AX;
end if;
@@ -843,6 +858,9 @@ begin
BAAdd <= "11"; -- BA Adj
if IR(7 downto 5) = "100" then
Write <= '1';
if IR(3 downto 0) = x"3" then
BAQuirk <= "10"; -- COPY
end if;
elsif IR(1)='0' or IR=x"B3" then -- Dont do this on $x3, except undoc LAXiy $B3 (says real CPU and Lorenz tests)
BreakAtNA <= '1';
end if;
@@ -956,6 +974,9 @@ begin
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then--99/9b
Write <= '1';
if IR(3 downto 0) = x"B" then
BAQuirk <= "01"; -- AND
end if;
elsif IR(1)='0' or IR=x"BB" then -- Dont do this on $xB, except undoc $BB (says real CPU and Lorenz tests)
BreakAtNA <= '1';
end if;
@@ -1045,8 +1066,13 @@ begin
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then -- ($9E,$9F)
if IR(7 downto 5) = "100" then -- ($9C,$9D,$9E,$9F)
Write <= '1';
case IR(1 downto 0) is
when "00"|"10" => BAQuirk <= "01"; -- AND
when "11" => BAQuirk <= "10"; -- COPY
when others => null;
end case;
else
BreakAtNA <= '1';
end if;

4
cores/nes/src/t65/T65_Pack.vhd
View File

@@ -92,9 +92,9 @@ package T65_Pack is
type T_Set_Addr_To is
(
Set_Addr_To_PBR,
Set_Addr_To_SP,
Set_Addr_To_ZPG,
Set_Addr_To_PBR,
Set_Addr_To_BA
);
@@ -177,4 +177,4 @@ package body T65_Pack is
end case;
end CycleNext;
end T65_Pack;
end T65_Pack;