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Code Issues Releases Wiki Activity

[Archie] Remove obsolete files

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This commit is contained in:
Gyorgy Szombathelyi
2019-03-03 15:24:02 +01:00
parent b6c3910709
commit ca812da031
3 changed files with 5 additions and 195 deletions
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11
cores/archie/fpga/mist/archimedes_mist_top.qsf
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@@ -136,7 +136,7 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_*
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/vidc.stp
set_global_assignment -name USE_SIGNALTAP_FILE output_files/sd.stp
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
@@ -161,7 +161,7 @@ set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
set_location_assignment PIN_7 -to LED
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
@@ -174,8 +174,9 @@ set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[*]
set_global_assignment -name SEED 2
set_global_assignment -name SEED 1
set_global_assignment -name ENABLE_DRC_SETTINGS OFF
set_location_assignment PLL_1 -to CLOCKS|altpll_component|auto_generated|pll1
set_global_assignment -name VERILOG_FILE archimedes_mist_top.v
set_global_assignment -name SYSTEMVERILOG_FILE rgb2ypbpr.sv
set_global_assignment -name VERILOG_FILE sigma_delta_dac.v
@@ -187,7 +188,6 @@ set_global_assignment -name VERILOG_FILE sram_line_en.v
set_global_assignment -name VERILOG_FILE sram_byte_en.v
set_global_assignment -name QIP_FILE clockgen.qip
set_global_assignment -name VERILOG_FILE ../../rtl/fdc1772.v
set_global_assignment -name VERILOG_FILE ../../rtl/vidc_divider.v
set_global_assignment -name VERILOG_FILE ../../rtl/latches.v
set_global_assignment -name VERILOG_FILE ../../rtl/floppy.v
set_global_assignment -name VERILOG_FILE ../../rtl/podules.v
@@ -221,12 +221,11 @@ set_global_assignment -name VERILOG_FILE ../../rtl/amber/a23_cache.v
set_global_assignment -name VERILOG_FILE ../../rtl/amber/a23_alu.v
set_global_assignment -name VERILOG_FILE ../../rtl/archimedes_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/sdram/sdram_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/sdram/sdram_init.v
set_global_assignment -name QIP_FILE rom_reconfig_24.qip
set_global_assignment -name QIP_FILE rom_reconfig_25.qip
set_global_assignment -name QIP_FILE pll_reconfig.qip
set_location_assignment PLL_1 -to CLOCKS|altpll_component|auto_generated|pll1
set_global_assignment -name QIP_FILE rom_reconfig_36.qip
set_global_assignment -name QIP_FILE pll_vidc.qip
set_global_assignment -name SIGNALTAP_FILE output_files/vidc.stp
set_global_assignment -name SIGNALTAP_FILE output_files/sd.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

101
cores/archie/rtl/sdram/sdram_init.v
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@@ -1,101 +0,0 @@
/* sdram_init.v
Copyright (c) 2013-2014, Stephen J. Leary
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the Stephen J. Leary nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL STEPHEN J. LEARY BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module sdram_init(
input sd_clk,
input sd_rst,
output reg [3:0] sd_cmd,
output reg [12:0] sd_a, // 13 bit multiplexed address bus
output reg sd_rdy
);
`include "sdram_defines.v"
parameter MODE = 0;
reg [3:0] t;
reg [4:0] reset;
initial begin
t = 4'd0;
reset = 5'h1f;
sd_a = 13'd0;
sd_cmd = CMD_INHIBIT;
sd_rdy = 0;
end
always @(posedge sd_clk) begin
sd_cmd <= CMD_INHIBIT; // default: idle
if (sd_rst) begin
t <= 4'd0;
reset <= 5'h1f;
sd_a <= 13'd0;
sd_rdy <= 0;
end else begin
if (!sd_rdy) t <= t + 4'd1;
if (t ==4'hF) begin
reset <= reset - 5'd1;
end
if (t == 4'h0) begin
if(reset == 13) begin
$display("precharging all banks");
sd_cmd <= CMD_PRECHARGE;
sd_a[10] <= 1'b1; // precharge all banks
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
sd_a <= MODE;
end
if(reset == 1) begin
$display("loading mode");
sd_cmd <= CMD_LOAD_MODE;
sd_a <= MODE;
end
if(reset == 0) sd_rdy <= 1;
end
end
end
endmodule

88
cores/archie/rtl/vidc_divider.v
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@@ -1,88 +0,0 @@
`timescale 1ns / 1ps
/* vidc_divider.v
Copyright (c) 2015, Stephen J. Leary
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module vidc_divider(
input clkpix2x,
input [1:0] clk_select,
output clkpix
);
reg clk24_m;
reg clk12_m;
wire clk16_m;
reg clk8_m;
reg [1:0] pos_cnt;
reg [1:0] neg_cnt;
initial begin
clk24_m = 1'b0;
clk12_m = 1'b0;
clk8_m = 1'b0;
pos_cnt = 'd0;
neg_cnt = 'd0;
end
always @(posedge clkpix2x) begin
clk24_m <= ~clk24_m;
pos_cnt <= (pos_cnt == 2) ? 0 : pos_cnt + 1;
end
always @(negedge clkpix2x) begin
neg_cnt <= (neg_cnt == 2) ? 0 : neg_cnt + 1;
end
always @(posedge clk24_m) begin
clk12_m <= ~clk12_m;
end
always @(posedge clk16_m) begin
clk8_m <= ~clk8_m;
end
// this is a divide by 3.
assign clk16_m = ((pos_cnt != 2) && (neg_cnt != 2));
assign clkpix = clk_select == 2'b00 ? clk8_m :
clk_select == 2'b01 ? clk12_m :
clk_select == 2'b10 ? clk16_m : clk24_m;
endmodule