Merge pull request #56 from gyurco/bbc

BBC Micro updates
2026-02-05 15:44:40 +00:00 · 2018-08-23 19:57:46 +01:00
parent ae8e19adf1 a490eec4f3
commit d3cbcabfd8
21 changed files with 4443 additions and 3389 deletions
--- a/cores/bbc/fpga/mist/bbc_mist.sdc
+++ b/cores/bbc/fpga/mist/bbc_mist.sdc
@@ -0,0 +1,52 @@
+#************************************************************
+# THIS IS A WIZARD-GENERATED FILE.                           
+#
+# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
+#
+#************************************************************
+
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+# Clock constraints
+
+create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27[0]}]
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# Clock groups
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[*]}]
+
+
+# Some relaxed constrain to the VGA pins. The signals should arrive together, the delay is not really important.
+set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -max 0 [get_ports {VGA_*}]
+set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -min -5 [get_ports {VGA_*}]
+
+# SDRAM delays
+set_input_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -max 6.4 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -min 3.2 [get_ports SDRAM_DQ[*]]
+
+set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+
+set_false_path -to [get_ports {AUDIO_L}]
+set_false_path -to [get_ports {AUDIO_R}]
+set_false_path -to [get_ports {LED}]
--- a/cores/bbc/fpga/mist/bbc_mist_top.qsf
+++ b/cores/bbc/fpga/mist/bbc_mist_top.qsf
@@ -133,7 +133,7 @@ set_location_assignment PIN_65 -to AUDIO_L
 set_location_assignment PIN_80 -to AUDIO_R

 set_global_assignment -name ENABLE_SIGNALTAP OFF
-set_global_assignment -name USE_SIGNALTAP_FILE signal_tap.stp
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp2.stp
 set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
 set_global_assignment -name ENABLE_NCE_PIN OFF
 set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
@@ -158,10 +158,9 @@ set_location_assignment PIN_7 -to LED
 set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON

 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+
 set_global_assignment -name VERILOG_FILE ../../rtl/adc.v
 set_global_assignment -name VERILOG_FILE sdram.v
-set_global_assignment -name VERILOG_FILE ../../rtl/cpu.v
-set_global_assignment -name VERILOG_FILE ../../rtl/ALU.v
 set_global_assignment -name VERILOG_FILE ../../rtl/mc6845.v
 set_global_assignment -name VERILOG_FILE ../../rtl/ps2_intf.v
 set_global_assignment -name VERILOG_FILE ../../rtl/vidproc.v
@@ -185,6 +184,7 @@ set_global_assignment -name VHDL_FILE "../../rtl/sn76489-1.0/sn76489_clock_div-c
 set_global_assignment -name VHDL_FILE "../../rtl/sn76489-1.0/sn76489_clock_div.vhd"
 set_global_assignment -name VHDL_FILE "../../rtl/sn76489-1.0/sn76489_attenuator-c.vhd"
 set_global_assignment -name VHDL_FILE "../../rtl/sn76489-1.0/sn76489_attenuator.vhd"
+set_global_assignment -name VERILOG_FILE sd_card.v
 set_global_assignment -name VERILOG_FILE user_io.v
 set_global_assignment -name VERILOG_FILE osd.v
 set_global_assignment -name VERILOG_FILE data_io.v
@@ -192,9 +192,11 @@ set_global_assignment -name VERILOG_FILE clockgen.v
 set_global_assignment -name VERILOG_FILE ../rtl/scandoubler.v
 set_global_assignment -name VERILOG_FILE ../../rtl/bbc.v
 set_global_assignment -name CDF_FILE output_files/Chain4.cdf
-set_global_assignment -name VERILOG_FILE ../../rtl/m6522.v
-set_global_assignment -name QIP_FILE smmc.qip
+set_global_assignment -name VHDL_FILE ../../rtl/m6522.vhd
+set_global_assignment -name QIP_FILE ../../rtl/T65/T65.qip
+set_global_assignment -name QIP_FILE mmfs.qip
 set_global_assignment -name QIP_FILE os12.qip
 set_global_assignment -name QIP_FILE basic2.qip
 set_global_assignment -name QIP_FILE dfs09.qip
+set_global_assignment -name SDC_FILE bbc_mist.sdc
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
--- a/cores/bbc/fpga/mist/bbc_mist_top.v
+++ b/cores/bbc/fpga/mist/bbc_mist_top.v
@@ -34,7 +34,7 @@ module bbc_mist_top(
 	
  
  // SPI
-  inout          SPI_DO,
+  output         SPI_DO,
  input          SPI_DI,
  input          SPI_SCK,
  input          SPI_SS2,    // data_io
@@ -157,6 +157,8 @@ wire [7:0] sd_dout;
 wire sd_dout_strobe;
 wire [7:0] sd_din;
 wire sd_din_strobe;
+wire [8:0] sd_buff_addr;
+wire sd_ack_conf;

 wire [7:0] joystick_0;
 wire [7:0] joystick_1;
@@ -167,8 +169,9 @@ wire scandoubler_disable;

 user_io #(.STRLEN(CONF_STR_LEN)) user_io(
   .conf_str      ( CONF_STR        ),
-   // the spi interface
+	.clk_sys(clk_32m),

+   // the spi interface
   .SPI_CLK     	( SPI_SCK         ),
   .SPI_SS_IO     ( CONF_DATA0      ),
   .SPI_MISO      ( SPI_DO          ),   // tristate handling inside user_io
@@ -196,6 +199,8 @@ user_io #(.STRLEN(CONF_STR_LEN)) user_io(
   .sd_dout_strobe(sd_dout_strobe	),
   .sd_din     	( sd_din				),
   .sd_din_strobe (sd_din_strobe		),
+	.sd_buff_addr  (sd_buff_addr     ),
+	.sd_ack_conf   (sd_ack_conf      ),

 	.ps2_clk 		( clk_14k			), 
 	.ps2_kbd_clk	( ps2_clk			), 
@@ -203,28 +208,29 @@ user_io #(.STRLEN(CONF_STR_LEN)) user_io(
 );

 // wire the sd card to the user port
-wire sd_sck = user_via_pb_out[1];
-wire sd_cs = 1'b0;
-wire sd_sdi = user_via_pb_out[0];
-wire sd_sdo = user_via_cb2_in;
-assign user_via_cb1_in = user_via_pb_out[1];
+wire sd_sck;
+wire sd_cs;
+wire sd_sdi;
+wire sd_sdo;

-sd_card sd_card (
-   // connection to io controller
-   .io_lba (sd_lba ),
-   .io_rd  (sd_rd),
-   .io_wr  (sd_wr),
-   .io_ack (sd_ack),
-   .io_conf (sd_conf),
-   .io_sdhc (sd_sdhc),
-   .io_din (sd_dout),
-   .io_din_strobe (sd_dout_strobe),
-   .io_dout (sd_din),
-   .io_dout_strobe ( sd_din_strobe),
+ sd_card sd_card (
+	// connection to io controller
+	.clk(clk_32m),
+	.io_lba (sd_lba ),
+	.io_rd  (sd_rd),
+	.io_wr  (sd_wr),
+	.io_ack (sd_ack),
+	.io_ack_conf (sd_ack_conf      ),
+	.io_conf (sd_conf),
+	.io_sdhc (sd_sdhc),
+	.io_din (sd_dout),
+	.io_din_strobe (sd_dout_strobe),
+	.io_dout (sd_din),
+	.io_dout_strobe ( sd_din_strobe),
+	.io_buff_addr  (sd_buff_addr     ),
+   .allow_sdhc ( 1'b1),   // SDHC not supported
 
-   .allow_sdhc ( 1'b0),   // SDHC not supported
-
-   // connection to local CPU
+    // connection to local CPU
   .sd_cs   ( sd_cs          ),
   .sd_sck  ( sd_sck         ),
   .sd_sdi  ( sd_sdi         ),
@@ -317,11 +323,12 @@ bbc BBC(
    .VID_ADR    ( vid_adr       ),
    .VID_DI     ( vid_data      ),
 	
-    .SHIFT     ( autoboot_shift ),
-	
-	 .user_via_pb_out ( user_via_pb_out   ),
-	 .user_via_cb1_in ( user_via_cb1_in   ),
-	 .user_via_cb2_in ( user_via_cb2_in   ),
+    .SHIFT      ( autoboot_shift ),
+
+	 .SDCLK      (sd_sck         ),
+	 .SDSS       (sd_cs          ),
+	 .SDMISO     (sd_sdo         ),
+	 .SDMOSI     (sd_sdi         ),

 	 .joy_but    ( { joystick_1[4], joystick_0[4] } ),
 	 .joy0_axis0 ( joystick_analog_0[15:8] ),
@@ -398,11 +405,11 @@ basic2 basic2 (
   .q			( basic_do			)
 );

-wire [7:0] smmc_do;
-smmc smmc (
+wire [7:0] mmfs_do;
+mmfs mmfs (
 	.clock 	( clk_32m			),
   .address	( mem_adr[13:0]	),
-   .q			( smmc_do		   )
+   .q			( mmfs_do		   )
 );

 audio	AUDIO	(
@@ -459,11 +466,11 @@ wire sideways_ram =

 // status[2] is '1' of low mapping is selected in the menu
 wire basic_map = status[2]?(mem_romsel == 4'h0):(mem_romsel == 4'he);
-wire smmc_map = status[2]?(mem_romsel == 4'h2):(mem_romsel == 4'hc);
+wire mmfs_map = status[2]?(mem_romsel == 4'h2):(mem_romsel == 4'hc);
 	
 assign mem_di = 
 	((mem_adr[15:14] == 2'b10) && basic_map) ? basic_do : 
-	((mem_adr[15:14] == 2'b10) && smmc_map) ? smmc_do :
+	((mem_adr[15:14] == 2'b10) && mmfs_map) ? mmfs_do :
 	((mem_adr[15:14] == 2'b10) && (mem_romsel == 4'ha)) ? ram_do :
 	mos_rom ? os_do : 
 	cpu_ram ? ram_do :
--- a/cores/bbc/fpga/mist/mmfs.qip
+++ b/cores/bbc/fpga/mist/mmfs.qip
@@ -1,3 +1,3 @@
 set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
 set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "smmc.v"]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mmfs.v"]
--- a/cores/bbc/fpga/mist/mmfs.v
+++ b/cores/bbc/fpga/mist/mmfs.v
@@ -4,7 +4,7 @@
 // MODULE: altsyncram 

 // ============================================================
-// File Name: smmc.v
+// File Name: mmfs.v
 // Megafunction Name(s):
 // 			altsyncram
 //
@@ -36,7 +36,7 @@
 // synopsys translate_off
 `timescale 1 ps / 1 ps
 // synopsys translate_on
-module smmc (
+module mmfs (
 	address,
 	clock,
 	q);
@@ -84,9 +84,9 @@ module smmc (
 		altsyncram_component.clock_enable_input_a = "BYPASS",
 		altsyncram_component.clock_enable_output_a = "BYPASS",
 `ifdef NO_PLI
-		altsyncram_component.init_file = "../../roms/smmc.rif"
+		altsyncram_component.init_file = "../../roms/mmfs.rif"
 `else
-		altsyncram_component.init_file = "../../roms/smmc.hex"
+		altsyncram_component.init_file = "../../roms/mmfs.hex"
 `endif
 ,
 		altsyncram_component.intended_device_family = "Cyclone III",
@@ -123,7 +123,7 @@ endmodule
 // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
 // Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
 // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING "../../roms/smmc.hex"
+// Retrieval info: PRIVATE: MIFfilename STRING "../../roms/mmfs.hex"
 // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 // Retrieval info: PRIVATE: RegAddr NUMERIC "1"
@@ -138,7 +138,7 @@ endmodule
 // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
 // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
 // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: INIT_FILE STRING "../../roms/smmc.hex"
+// Retrieval info: CONSTANT: INIT_FILE STRING "../../roms/mmfs.hex"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
@@ -155,10 +155,10 @@ endmodule
 // Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
 // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL smmc.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL smmc.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL smmc.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL smmc.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL smmc_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL smmc_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmfs.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmfs.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmfs.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmfs.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmfs_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmfs_bb.v FALSE
 // Retrieval info: LIB_FILE: altera_mf
--- a/cores/bbc/fpga/mist/sd_card.v
+++ b/cores/bbc/fpga/mist/sd_card.v
@@ -25,25 +25,29 @@
 // http://elm-chan.org/docs/mmc/mmc_e.html

 module sd_card (
+	input         clk,
 	// link to user_io for io controller
 	output [31:0] io_lba,
 	output reg    io_rd,
 	output reg    io_wr,
-	input			  io_ack,
-	output		  io_conf,
-	output		  io_sdhc,
-	
+	input         io_ack,
+	input         io_ack_conf,
+	output        io_conf,
+	output        io_sdhc,
+
 	// data coming in from io controller
-	input	[7:0]	  io_din,
-	input 		  io_din_strobe,
+	input   [7:0] io_din,
+	input         io_din_strobe,

 	// data going out to io controller
-	output [7:0]  io_dout,
-	input 		  io_dout_strobe,
+	output  [7:0] io_dout,
+	input         io_dout_strobe,
+
+	input   [8:0] io_buff_addr,

 	// configuration input
 	input         allow_sdhc,
-	
+
   input         sd_cs,
   input         sd_sck,
   input         sd_sdi,
@@ -53,15 +57,23 @@ module sd_card (
 // set io_rd once read_state machine starts waiting (rising edge of req_io_rd)
 // and clear it once io controller uploads something (io_ack==1) 
 reg req_io_rd = 1'b0; // set when write_state is changed to RD_STATE_WAIT_IO
-always @(posedge req_io_rd or posedge io_ack) begin
-	if(io_ack) io_rd <= 1'b0;
-	else 		  io_rd <= 1'b1;
-end

 reg req_io_wr = 1'b0; // set when write_state is changed to WR_STATE_BUSY
-always @(posedge req_io_wr or posedge io_ack) begin
-	if(io_ack) io_wr <= 1'b0;
-	else 		  io_wr <= 1'b1;
+
+always @(posedge clk) begin
+	reg old_io_ack;
+	reg req_io_rdD;
+	reg req_io_wrD;
+
+	old_io_ack <= io_ack;
+	req_io_rdD <= req_io_rd;
+	req_io_wrD <= req_io_wr;
+	
+	if(~old_io_ack & io_ack) { io_rd, io_wr } <= 2'b00;
+	else begin
+		if (~req_io_rdD & req_io_rd) io_rd <= 1;
+		if (~req_io_wrD & req_io_wr) io_wr <= 1;
+	end
 end

 wire [31:0] OCR = { 1'b0, io_sdhc, 30'h0 };  // bit30 = 1 -> high capaciry card (sdhc)
@@ -88,7 +100,6 @@ reg [2:0] write_state = WR_STATE_IDLE;
 reg card_is_reset = 1'b0;    // flag that card has received a reset command
 reg [6:0] sbuf; 
 reg cmd55;
-reg new_cmd_rcvd;
 reg [7:0] cmd = 8'h00;
 reg [2:0] bit_cnt = 3'd0;    // counts bits 0-7 0-7 ...
 reg [3:0] byte_cnt= 4'd15;   // counts bytes
@@ -104,118 +115,92 @@ reg [3:0] reply_len;
 // the sector buffer by the io controller. This signal is kept set as long
 // as the read state machine is in the "wait for io controller" state (state 1)
 wire rd_wait_io = (read_state != RD_STATE_IDLE);
-reg rd_io_ack_i = 1'b0;
-always @(negedge io_ack or negedge rd_wait_io) begin
-	if(!rd_wait_io) rd_io_ack_i <= 1'b0;
-	else            rd_io_ack_i <= 1'b1;
-end
+reg rd_io_ack = 1'b0;
 
 wire wr_wait_io = (write_state == WR_STATE_BUSY);
-reg wr_io_ack_i = 1'b0;
-always @(negedge io_ack or negedge wr_wait_io) begin
-	if(!wr_wait_io) wr_io_ack_i <= 1'b0;
-	else            wr_io_ack_i <= 1'b1;
-end
+reg wr_io_ack = 1'b0;

-// bring xx_io_ack into sd cards clock domain
-reg wr_io_ack;
-reg rd_io_ack;
-always @(posedge sd_sck) begin	
-	rd_io_ack <= rd_io_ack_i;
-	wr_io_ack <= wr_io_ack_i;
+always @(posedge clk) begin
+   reg old_io_ack;
+	old_io_ack <= io_ack;
+	
+	if(!wr_wait_io) wr_io_ack <= 1'b0;
+	else if (~io_ack & old_io_ack) begin
+		wr_io_ack <= 1'b1;
+	end
+
+	if(!rd_wait_io) rd_io_ack <= 1'b0;
+	else if (~io_ack & old_io_ack) begin
+		rd_io_ack <= 1'b1;
+	end
 end

 // ------------------------- SECTOR BUFFER -----------------------

 // the buffer itself. Can hold one sector
-reg [7:0] buffer [511:0];
+reg  [8:0] buffer_ptr;
+wire [7:0] buffer_dout;
+reg  [7:0] buffer_din;
+reg        buffer_write_strobe;

-// ---------------- buffer read engine -----------------------
-reg [8:0] buffer_rptr;
-reg buffer_read_strobe;
-wire buffer_dout_strobe = buffer_read_strobe || io_dout_strobe;
-reg [7:0] buffer_dout;
-assign io_dout = buffer_dout;
+sd_card_dpram #(8, 9) buffer_dpram
+(
+	.clock_a	     (clk),
+	.address_a    (io_buff_addr),
+	.data_a       (io_din),
+	.wren_a       (io_din_strobe & io_ack),
+	.q_a          (io_dout),

-// buffer_rptr is increased in a diferent clock domain than it's
-// evaluated. These single bit registers bring certain states from
-// one domain into the other one in a safe (atomic) way
-reg buffer_read_sector_done;
-reg buffer_read_ciscid_done;
-
-always @(posedge buffer_dout_strobe or posedge new_cmd_rcvd) begin
-	if(new_cmd_rcvd == 1) begin
-		buffer_rptr <= 9'd0;
-		buffer_read_sector_done <= 1'b0;
-		buffer_read_ciscid_done <= 1'b0;
-	end else begin
-		buffer_dout <= buffer[buffer_rptr];
-		buffer_rptr <= buffer_rptr + 9'd1;
-		if(buffer_rptr == 511) buffer_read_sector_done <= 1'b1;
-		if(buffer_rptr == 15)  buffer_read_ciscid_done <= 1'b1;
-	end
-end
-
-// ---------------- buffer write engine -----------------------
-reg [8:0] buffer_wptr;
-reg buffer_write_strobe;
-wire buffer_din_strobe = io_din_strobe || buffer_write_strobe;
-wire [7:0] buffer_din = (cmd == 8'h51)?io_din:{sbuf, sd_sdi};
-
-always @(posedge buffer_din_strobe or posedge new_cmd_rcvd) begin
-	if(new_cmd_rcvd == 1)
-		buffer_wptr <= 9'd0;
-	else begin
-		buffer[buffer_wptr] <= buffer_din;	
-		buffer_wptr <= buffer_wptr + 9'd1;
-	end
-end
+	.clock_b      (clk),
+	.address_b    (buffer_ptr),
+	.data_b       (buffer_din),
+	.wren_b       (buffer_write_strobe),
+	.q_b          (buffer_dout)
+);

 wire [7:0] WRITE_DATA_RESPONSE = 8'h05;

 // ------------------------- CSD/CID BUFFER ----------------------
-assign io_conf = (csd_wptr == 0);  // csd_wptr still 0 -> configuration required
+reg  [7:0] conf;
+assign     io_conf = io_configuring;

-// the 32 bytes as sent from the io controller
-reg [7:0] cid [15:0];
-reg [7:0] csd [15:0];
-reg [7:0] conf;
+reg        io_configuring = 1;
+reg  [4:0] conf_buff_ptr;
+wire [7:0] conf_byte;

-reg [7:0] cid_byte;
-reg [7:0] csd_byte;
-reg [5:0] csd_wptr = 6'd0;
+sd_card_dpram #(8, 6) conf_dpram
+(
+	.clock_a	     (clk),
+	.address_a    (io_buff_addr),
+	.data_a       (io_din),
+	.wren_a       (io_din_strobe & io_ack_conf),
+
+	.clock_b      (clk),
+	.address_b    (conf_buff_ptr),
+	.q_b          (conf_byte)
+);

 // conf[0]==1 -> io controller is using an sdhc card
 wire io_has_sdhc = conf[0];
 assign io_sdhc = allow_sdhc && io_has_sdhc;

-always @(posedge io_din_strobe) begin
-	// if io controller sends data without asserting io_ack, then it's
-	// updating the config
-	if(!io_ack && (csd_wptr <= 32)) begin
-	
-		if(csd_wptr < 16)                       // first 16 bytes are cid
-			cid[csd_wptr[3:0]] <= io_din;	
-		if((csd_wptr >= 16) && (csd_wptr < 32)) // then comes csd
-			csd[csd_wptr[3:0]] <= io_din;	
-		if(csd_wptr == 32)                      // finally a config byte
-			conf <= io_din;	
-			
-		csd_wptr	<= csd_wptr + 6'd1;
+always @(posedge clk) begin
+	if(io_din_strobe && io_ack_conf && io_buff_addr== 32) begin
+		conf <= io_din;
+		io_configuring <= 0;
 	end
 end
- 
-always @(posedge buffer_dout_strobe) begin
-	cid_byte <= cid[buffer_rptr[3:0]];
-	csd_byte <= csd[buffer_rptr[3:0]];
-end
- 	
-// ----------------- spi transmitter --------------------
+
+always@(posedge clk) begin
+
+	reg illegal_write_state /* synthesis noprune */;
+	reg old_sd_sck;
+	old_sd_sck <= sd_sck;
 // advance transmitter state machine on falling sck edge, so data is valid on the 
 // rising edge
-always@(negedge sd_sck) begin
-	if(sd_cs == 0) begin
-		buffer_read_strobe <= 1'b0;
+// ----------------- spi transmitter --------------------
+	if(sd_cs == 0 && old_sd_sck && ~sd_sck) begin
+
 		sd_sdo <= 1'b1;				// default: send 1's (busy/wait)
 		req_io_rd <= 1'b0;
 		
@@ -257,8 +242,10 @@ always@(negedge sd_sck) begin

 			// waiting for io controller to return data
 			RD_STATE_WAIT_IO: begin
+				buffer_ptr <= 0;
 				if(rd_io_ack && (bit_cnt == 7)) 
 					read_state <= RD_STATE_SEND_TOKEN;
+
 			end

 			// send data token
@@ -267,7 +254,7 @@ always@(negedge sd_sck) begin
 	
 				if(bit_cnt == 7) begin
 					read_state <= RD_STATE_SEND_DATA;   // next: send data
-					buffer_read_strobe <= 1'b1;         // trigger read of first data byte
+					conf_buff_ptr <= (cmd == 8'h4a) ? 5'h0 : 5'h10;
 				end
 			end
 					
@@ -276,27 +263,29 @@ always@(negedge sd_sck) begin
 				if(cmd == 8'h51) 							// CMD17: READ_SINGLE_BLOCK
 					sd_sdo <= buffer_dout[~bit_cnt];
 				else if(cmd == 8'h49) 					// CMD9: SEND_CSD
-					sd_sdo <= csd_byte[~bit_cnt];
+					sd_sdo <= conf_byte[~bit_cnt];
 				else if(cmd == 8'h4a) 					// CMD10: SEND_CID
-					sd_sdo <= cid_byte[~bit_cnt];
+					sd_sdo <= conf_byte[~bit_cnt];
 				else
 					sd_sdo <= 1'b1;

 				if(bit_cnt == 7) begin
 					// sent 512 sector data bytes?
-					if((cmd == 8'h51) && buffer_read_sector_done) // (buffer_rptr == 0))
+					if((cmd == 8'h51) && &buffer_ptr) // (buffer_ptr ==511))
 						read_state <= RD_STATE_IDLE;   // next: send crc. It's ignored so return to idle state
-						
+
 					// sent 16 cid/csd data bytes?
-					else if(((cmd == 8'h49)||(cmd == 8'h4a)) && buffer_read_ciscid_done) // && (buffer_rptr == 16))
+					else if(((cmd == 8'h49)||(cmd == 8'h4a)) && conf_buff_ptr[3:0] == 4'h0f) // && (buffer_rptr == 16))
 						read_state <= RD_STATE_IDLE;   // return to idle state
-						
-					else
-						buffer_read_strobe <= 1'b1;    // not done yet -> trigger read of next data byte
+
+					else begin
+						buffer_ptr <= buffer_ptr + 1'd1;
+						conf_buff_ptr<= conf_buff_ptr+ 1'd1;
+					end
 				end
 			end
 		endcase
-					
+
 		// ------------------ write support ----------------------
 		// send write data response
 		if(write_state == WR_STATE_SEND_DRESP) 
@@ -306,19 +295,18 @@ always@(negedge sd_sck) begin
 		if(write_state == WR_STATE_BUSY) 
 			sd_sdo <= 1'b0;
   end
-end

-// spi receiver  
-reg illegal_write_state /* synthesis noprune */;
+	if (buffer_write_strobe) begin
+		buffer_write_strobe <= 1'b0;
+		buffer_ptr <= buffer_ptr + 1'd1;
+	end

-always @(posedge sd_sck or posedge sd_cs) begin
+	// spi receiver  
 	// cs is active low
 	if(sd_cs == 1) begin
 		bit_cnt <= 3'd0;
-	end else begin 
+	end else if (~old_sd_sck & sd_sck) begin
 		illegal_write_state <= 1'b0;
-		new_cmd_rcvd <= 1'b0;
-		buffer_write_strobe <= 1'b0;
 		req_io_wr <= 1'b0;
 		bit_cnt <= bit_cnt + 3'd1;
 		
@@ -338,7 +326,6 @@ always @(posedge sd_sck or posedge sd_cs) begin
 				(read_state == RD_STATE_IDLE)  && sbuf[6:5] == 2'b01) begin
 				byte_cnt <= 4'd0;			
 				cmd <= { sbuf, sd_sdi};
-				new_cmd_rcvd <= 1'b1;

 			   // set cmd55 flag if previous command was 55
 			   cmd55 <= (cmd == 8'h77);
@@ -434,16 +421,19 @@ always @(posedge sd_sck or posedge sd_cs) begin
 				
 				// waiting for data token
 				WR_STATE_EXP_DTOKEN:
-					if({ sbuf, sd_sdi} == 8'hfe )
+					if({ sbuf, sd_sdi} == 8'hfe ) begin
 						write_state <= WR_STATE_RECV_DATA;
+						buffer_ptr <= 9'd0;
+					end

 				// transfer 512 bytes
 				WR_STATE_RECV_DATA: begin
 					// push one byte into local buffer
 					buffer_write_strobe <= 1'b1;
+					buffer_din <= { sbuf, sd_sdi };

 					// all bytes written?
-					if(buffer_wptr == 511)
+					if(&buffer_ptr)
 						write_state <= WR_STATE_RECV_CRC0;
 				end
 	
@@ -465,7 +455,7 @@ always @(posedge sd_sck or posedge sd_cs) begin
 				WR_STATE_BUSY:
 					if(wr_io_ack)
 						write_state <= WR_STATE_IDLE;
-						
+
 				default:
 					illegal_write_state <= 1'b1;
 			endcase
@@ -474,3 +464,38 @@ always @(posedge sd_sck or posedge sd_cs) begin
 end

 endmodule
+
+module sd_card_dpram #(parameter DATAWIDTH=8, ADDRWIDTH=9)
+(
+        input                   clock_a,
+        input   [ADDRWIDTH-1:0] address_a,
+        input   [DATAWIDTH-1:0] data_a,
+        input                   wren_a,
+        output reg [DATAWIDTH-1:0] q_a,
+
+		  input                   clock_b,
+        input   [ADDRWIDTH-1:0] address_b,
+        input   [DATAWIDTH-1:0] data_b,
+        input                   wren_b,
+        output reg [DATAWIDTH-1:0] q_b
+);
+
+reg [DATAWIDTH-1:0] ram[0:(1<<ADDRWIDTH)-1];
+
+always @(posedge clock_a) begin
+	q_a <= ram[address_a];
+   if(wren_a) begin
+      q_a <= data_a;
+		ram[address_a] <= data_a;
+   end
+end
+
+always @(posedge clock_b) begin
+	q_b <= ram[address_b];
+   if(wren_b) begin
+      q_b <= data_b;
+		ram[address_b] <= data_b;
+   end
+end
+
+endmodule
--- a/cores/bbc/fpga/mist/user_io.v
+++ b/cores/bbc/fpga/mist/user_io.v
@@ -25,9 +25,10 @@
 module user_io #(parameter STRLEN=0) (
 	input [(8*STRLEN)-1:0] conf_str,

+	input 		       clk_sys,
 	input 		       SPI_CLK,
 	input 		       SPI_SS_IO,
-	output reg 	       SPI_MISO,
+	output reg	       SPI_MISO,
 	input 		       SPI_MOSI,
 	
 	output reg [7:0]       joystick_0,
@@ -41,17 +42,18 @@ module user_io #(parameter STRLEN=0) (
 	output reg [7:0]       status,

 	// connection to sd card emulation
-	input [31:0] 	       sd_lba,
+	input       [31:0] sd_lba,
 	input 		       sd_rd,
 	input 		       sd_wr,
 	output reg 	       sd_ack,
+	output reg         sd_ack_conf,
 	input 		       sd_conf,
 	input 		       sd_sdhc,
-	output [7:0] 	       sd_dout, // valid on rising edge of sd_dout_strobe
+	output reg   [7:0] sd_dout, // valid on rising edge of sd_dout_strobe
 	output reg 	       sd_dout_strobe,
-	input [7:0] 	       sd_din,
+	input        [7:0] sd_din,
 	output reg 	       sd_din_strobe,
-	
+	output reg   [8:0] sd_buff_addr,

 	// ps2 keyboard emulation
 	input 		       ps2_clk, // 12-16khz provided by core
@@ -76,7 +78,6 @@ reg [2:0]         stick_idx;

 assign buttons = but_sw[1:0];
 assign switches = but_sw[3:2];
-assign sd_dout = { sbuf, SPI_MOSI};
 assign scandoubler_disable = but_sw[4];

 // this variant of user_io is for 8 bit cores (type == a4) only
@@ -86,56 +87,9 @@ wire [7:0] core_type = 8'ha4;
 wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };

 // filter spi clock. the 8 bit gate delay is ~2.5ns in total
-wire [7:0] spi_sck_D = { spi_sck_D[6:0], SPI_CLK } /* synthesis keep */;
-wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff);
-
-// drive MISO only when transmitting core id
-always@(negedge spi_sck or posedge SPI_SS_IO) begin
-	if(SPI_SS_IO == 1) begin
-	   SPI_MISO <= 1'bZ;
-	end else begin
-
-		// first byte returned is always core type, further bytes are 
-		// command dependent
-      if(byte_cnt == 0) begin
-		  SPI_MISO <= core_type[~bit_cnt];
-
-		end else begin
-			// reading serial fifo
-		   if(cmd == 8'h1b) begin
-				// send alternating flag byte and data
-				if(byte_cnt[0]) 	SPI_MISO <= serial_out_status[~bit_cnt];
-				else					SPI_MISO <= serial_out_byte[~bit_cnt];
-			end
-			
-			// reading config string
-		   else if(cmd == 8'h14) begin
-				// returning a byte from string
-				if(byte_cnt < STRLEN + 1)
-					SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
-				else
-					SPI_MISO <= 1'b0;
-			end
-			
-			// reading sd card status
-		   else if(cmd == 8'h16) begin
-				if(byte_cnt == 1)
-					SPI_MISO <= sd_cmd[~bit_cnt];
-				else if((byte_cnt >= 2) && (byte_cnt < 6))
-					SPI_MISO <= sd_lba[{5-byte_cnt, ~bit_cnt}];
-				else
-					SPI_MISO <= 1'b0;
-			end
-			
-			// reading sd card write data
-		   else if(cmd == 8'h18)
-				SPI_MISO <= sd_din[~bit_cnt];
-				
-			else
-				SPI_MISO <= 1'b0;
-		end
-   end
-end
+//wire [7:0] spi_sck_D = { spi_sck_D[6:0], SPI_CLK } /* synthesis keep */;
+//wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff);
+wire spi_sck = SPI_CLK;

 // ---------------- PS2 ---------------------

@@ -307,108 +261,210 @@ always@(negedge spi_sck or posedge status[0]) begin
 	end
 end

-// SPI receiver
-always@(posedge spi_sck or posedge SPI_SS_IO) begin

+// SPI bit and byte counters
+always@(posedge spi_sck or posedge SPI_SS_IO) begin
 	if(SPI_SS_IO == 1) begin
-	   bit_cnt <= 3'd0;
-	   byte_cnt <= 8'd0;
-		sd_ack <= 1'b0;
-		sd_dout_strobe <= 1'b0;
-		sd_din_strobe <= 1'b0;
+		bit_cnt <= 0;
+	   byte_cnt <= 0;
 	end else begin
-		sd_dout_strobe <= 1'b0;
-		sd_din_strobe <= 1'b0;
-		
-		if(bit_cnt != 7)
-			sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
-			
-		bit_cnt <= bit_cnt + 3'd1;
 		if((bit_cnt == 7)&&(byte_cnt != 8'd255)) 
 			byte_cnt <= byte_cnt + 8'd1;

-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(byte_cnt == 0) begin
-				cmd <= { sbuf, SPI_MOSI};
-			
-				// fetch first byte when sectore FPGA->IO command has been seen
-				if({ sbuf, SPI_MOSI} == 8'h18)
-					sd_din_strobe <= 1'b1;
-					
-				if(({ sbuf, SPI_MOSI} == 8'h17) || ({ sbuf, SPI_MOSI} == 8'h18))
-					sd_ack <= 1'b1;
-					
-			end else begin
-			
-				// buttons and switches
-				if(cmd == 8'h01)
-					but_sw <= { sbuf[3:0], SPI_MOSI }; 
+		bit_cnt <= bit_cnt + 1'd1;
+	end
+end

-				if(cmd == 8'h02)
-					joystick_0 <= { sbuf, SPI_MOSI };
-				 
-				if(cmd == 8'h03)
-					joystick_1 <= { sbuf, SPI_MOSI };
-				 
-				if(cmd == 8'h04) begin
-					// store incoming ps2 mouse bytes 
-					ps2_mouse_fifo[ps2_mouse_wptr] <= { sbuf, SPI_MOSI }; 
-					ps2_mouse_wptr <= ps2_mouse_wptr + 1;
-				end
+// SPI transmitter FPGA -> IO
+reg [7:0] spi_byte_out;

-				if(cmd == 8'h05) begin
-					// store incoming ps2 keyboard bytes 
-					ps2_kbd_fifo[ps2_kbd_wptr] <= { sbuf, SPI_MOSI }; 
-					ps2_kbd_wptr <= ps2_kbd_wptr + 1;
-				end
-				
-				if(cmd == 8'h15)
-					status <= { sbuf[6:0], SPI_MOSI };
-				
-				// send sector IO -> FPGA
-				if(cmd == 8'h17) begin
-					// flag that download begins
-//					sd_dout <= { sbuf, SPI_MOSI};
-					sd_dout_strobe <= 1'b1;
-				end
-				
-				// send sector FPGA -> IO
-				if(cmd == 8'h18)
-					sd_din_strobe <= 1'b1;
-				
-				// send SD config IO -> FPGA
-				if(cmd == 8'h19) begin
-					// flag that download begins
-//					sd_dout <= { sbuf, SPI_MOSI};
-					// sd card knows data is config if sd_dout_strobe is asserted
-					// with sd_ack still being inactive (low)
-					sd_dout_strobe <= 1'b1;
-				end
-				
-				// joystick analog
-				if(cmd == 8'h1a) begin
-					// first byte is joystick indes
-					if(byte_cnt == 1)
-						stick_idx <= { sbuf[1:0], SPI_MOSI };
-					else if(byte_cnt == 2) begin
-						// second byte is x axis
-						if(stick_idx == 0)
-							joystick_analog_0[15:8] <= { sbuf, SPI_MOSI };
-						else if(stick_idx == 1)
-							joystick_analog_1[15:8] <= { sbuf, SPI_MOSI };
-					end else if(byte_cnt == 3) begin
-						// third byte is y axis
-						if(stick_idx == 0)
-							joystick_analog_0[7:0] <= { sbuf, SPI_MOSI };
-						else if(stick_idx == 1)
-							joystick_analog_1[7:0] <= { sbuf, SPI_MOSI };
-					end
-				end
+always@(negedge spi_sck or posedge SPI_SS_IO) begin
+	if(SPI_SS_IO == 1) begin
+	   SPI_MISO <= 1'bZ;
+	end else begin
+		SPI_MISO <= spi_byte_out[~bit_cnt];
+	end
+end

-			end
+always@(posedge spi_sck or posedge SPI_SS_IO) begin
+	reg [31:0] sd_lba_r;
+	
+	if(SPI_SS_IO == 1) begin
+		spi_byte_out <= core_type;
+	end else begin
+		// read the command byte to choose the response
+		if(bit_cnt == 7) begin
+			if(!byte_cnt) cmd <= {sbuf, SPI_MOSI};
+
+         spi_byte_out <= 0;
+         case({(!byte_cnt) ? {sbuf, SPI_MOSI} : cmd})
+				// reading config string
+            8'h14: if(byte_cnt < STRLEN) spi_byte_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
+
+            // reading sd card status
+            8'h16: if(byte_cnt == 0) begin
+					spi_byte_out <= sd_cmd;
+					sd_lba_r <= sd_lba;
+            end
+            else if(byte_cnt < 5) spi_byte_out <= sd_lba_r[(4-byte_cnt)<<3 +:8];
+
+            // reading sd card write data
+            8'h18: spi_byte_out <= sd_din;
+				8'h1b:
+					// send alternating flag byte and data
+					if(byte_cnt[0]) spi_byte_out <= serial_out_status;
+					else spi_byte_out <= serial_out_byte;
+			endcase
 		end
 	end
 end
-   
+
+// SPI receiver IO -> FPGA
+
+reg       spi_receiver_strobe_r;
+reg       spi_transfer_end_r;
+reg [7:0] spi_byte_in_r;
+
+// Read at spi_sck clock domain, assemble bytes for transferring to clk_sys
+always@(posedge spi_sck or posedge SPI_SS_IO) begin
+
+	if(SPI_SS_IO == 1) begin
+		spi_receiver_strobe_r <= 0;
+		spi_transfer_end_r <= 1;
+	end else begin
+		spi_receiver_strobe_r <= 0;
+		spi_transfer_end_r <= 0;
+
+		if(bit_cnt != 7)
+			sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
+
+		// finished reading a byte, prepare to transfer to clk_sys
+      if(bit_cnt == 7) begin
+			spi_byte_in_r <= { sbuf, SPI_MOSI};
+			spi_receiver_strobe_r <= 1;
+		end
+	end
+end
+
+// Process bytes from SPI at the clk_sys domain
+always @(posedge clk_sys) begin
+
+	reg       spi_receiver_strobe;
+	reg       spi_transfer_end;
+	reg [7:0] spi_byte_in;
+	reg       spi_receiver_strobeD;
+	reg       spi_transfer_endD;
+	reg [7:0] spi_byte_inD;
+	reg [7:0] acmd;
+	reg [7:0] abyte_cnt;   // counts bytes
+
+	//synchronize between SPI and sys clock domains
+	spi_receiver_strobeD <= spi_receiver_strobe_r;
+	spi_receiver_strobe <= spi_receiver_strobeD;
+	spi_transfer_endD	<= spi_transfer_end_r;
+	spi_transfer_end	<= spi_transfer_endD;
+	spi_byte_inD <= spi_byte_in_r;
+	spi_byte_in <= spi_byte_inD;
+
+	if(sd_dout_strobe) begin
+		sd_dout_strobe<= 0;
+		if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
+	end
+
+	if(sd_din_strobe) begin
+		sd_din_strobe<= 0;
+		if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
+	end
+
+	if (~spi_transfer_endD & spi_transfer_end) begin
+			abyte_cnt <= 8'd0;
+			sd_ack <= 1'b0;
+			sd_ack_conf <= 1'b0;
+			sd_dout_strobe <= 1'b0;
+			sd_din_strobe <= 1'b0;
+			sd_buff_addr<= 0;
+	end else if (~spi_receiver_strobeD & spi_receiver_strobe) begin
+
+			if(abyte_cnt != 8'd255) 
+				abyte_cnt <= byte_cnt + 8'd1;
+
+			if(abyte_cnt == 0) begin
+				acmd <= spi_byte_in;
+
+				// fetch first byte when sectore FPGA->IO command has been seen
+				if(spi_byte_in == 8'h18)
+					sd_din_strobe <= 1'b1;
+
+				if((spi_byte_in == 8'h17) || (spi_byte_in == 8'h18))
+					sd_ack <= 1'b1;
+
+			end else begin
+
+				// buttons and switches
+				if(acmd == 8'h01)
+					but_sw <= spi_byte_in;
+
+				if(acmd == 8'h02)
+					joystick_0 <= spi_byte_in;
+				 
+				if(acmd == 8'h03)
+					joystick_1 <= spi_byte_in;
+
+				if(acmd == 8'h04) begin
+					// store incoming ps2 mouse bytes 
+					ps2_mouse_fifo[ps2_mouse_wptr] <= spi_byte_in;
+					ps2_mouse_wptr <= ps2_mouse_wptr + 1;
+				end
+
+				if(acmd == 8'h05) begin
+					// store incoming ps2 keyboard bytes 
+					ps2_kbd_fifo[ps2_kbd_wptr] <= spi_byte_in;
+					ps2_kbd_wptr <= ps2_kbd_wptr + 1;
+				end
+
+				if(acmd == 8'h15)
+					status <= spi_byte_in;
+
+				// send sector IO -> FPGA
+				if(acmd == 8'h17) begin
+					// flag that download begins
+					sd_dout_strobe <= 1'b1;
+					sd_dout <= spi_byte_in;
+				end
+
+				// send sector FPGA -> IO
+				if(acmd == 8'h18)
+					sd_din_strobe <= 1'b1;
+
+				// send SD config IO -> FPGA
+				if(acmd == 8'h19) begin
+					// flag that download begins
+					sd_dout_strobe <= 1'b1;
+					sd_ack_conf <= 1'b1;
+					sd_dout <= spi_byte_in;
+				end
+
+				// joystick analog
+				if(acmd == 8'h1a) begin
+					// first byte is joystick indes
+					if(abyte_cnt == 1)
+						stick_idx <= spi_byte_in[2:0];
+					else if(abyte_cnt == 2) begin
+						// second byte is x axis
+						if(stick_idx == 0)
+							joystick_analog_0[15:8] <= spi_byte_in;
+						else if(stick_idx == 1)
+							joystick_analog_1[15:8] <= spi_byte_in;
+					end else if(abyte_cnt == 3) begin
+						// third byte is y axis
+						if(stick_idx == 0)
+							joystick_analog_0[7:0] <= spi_byte_in;
+						else if(stick_idx == 1)
+							joystick_analog_1[7:0] <= spi_byte_in;
+					end
+				end
+		end
+	end
+end
+
 endmodule
--- a/cores/bbc/roms/mmfs.hex
+++ b/cores/bbc/roms/mmfs.hex
@@ -0,0 +1,513 @@
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--- a/cores/bbc/roms/smmc.rom
+++ b/cores/bbc/roms/smmc.rom
--- a/cores/bbc/rtl/ALU.v
+++ b/cores/bbc/rtl/ALU.v
@@ -1,108 +0,0 @@
-/*
- * ALU.
- *
- * AI and BI are 8 bit inputs. Result in OUT.
- * CI is Carry In.
- * CO is Carry Out.
- *
- * op[3:0] is defined as follows:
- *
- * 0011   AI + BI
- * 0111   AI - BI
- * 1011   AI + AI
- * 1100   AI | BI
- * 1101   AI & BI
- * 1110   AI ^ BI
- * 1111   AI
- *
- */
-
-module ALU( clk, op, right, AI, BI, CI, CO, BCD, OUT, V, Z, N, HC, RDY );
-	input clk;
-	input right;
-	input [3:0] op;		// operation
-	input [7:0] AI;
-	input [7:0] BI;
-	input CI;
-	input BCD;		// BCD style carry
-	output [7:0] OUT;
-	output CO;
-	output V;
-	output Z;
-	output N;
-	output HC;
-	input RDY;
-
-reg [7:0] OUT;
-reg CO;
-wire V;
-wire Z;
-reg N;
-reg HC;
-
-reg AI7;
-reg BI7;
-reg [8:0] temp_logic;
-reg [7:0] temp_BI;
-reg [4:0] temp_l;
-reg [4:0] temp_h;
-wire [8:0] temp = { temp_h, temp_l[3:0] };
-wire adder_CI = (right | (op[3:2] == 2'b11)) ? 0 : CI;
-
-// calculate the logic operations. The 'case' can be done in 1 LUT per
-// bit. The 'right' shift is a simple mux that can be implemented by
-// F5MUX.
-always @*  begin
-	case( op[1:0] )
-	    2'b00: temp_logic = AI | BI;
-	    2'b01: temp_logic = AI & BI;
-	    2'b10: temp_logic = AI ^ BI;
-	    2'b11: temp_logic = AI;
-	endcase
-
-	if( right )
-	    temp_logic = { AI[0], CI, AI[7:1] };
-end
-
-// Add logic result to BI input. This only makes sense when logic = AI.
-// This stage can be done in 1 LUT per bit, using carry chain logic.
-always @* begin
-	case( op[3:2] )
-	    2'b00: temp_BI = BI;	// A+B
-	    2'b01: temp_BI = ~BI;	// A-B
-	    2'b10: temp_BI = temp_logic;	// A+A
-	    2'b11: temp_BI = 0;		// A+0
-	endcase	
-end
-
-// HC9 is the half carry bit when doing BCD add
-wire HC9 = BCD & (temp_l[3:1] >= 3'd5);
-
-// CO9 is the carry-out bit when doing BCD add
-wire CO9 = BCD & (temp_h[3:1] >= 3'd5);
-
-// combined half carry bit
-wire temp_HC = temp_l[4] | HC9;
-
-// perform the addition as 2 separate nibble, so we get
-// access to the half carry flag
-always @* begin
-	temp_l = temp_logic[3:0] + temp_BI[3:0] + adder_CI;
-	temp_h = temp_logic[8:4] + temp_BI[7:4] + temp_HC;
-end
-
-// calculate the flags 
-always @(posedge clk)
-    if( RDY ) begin
-	AI7 <= AI[7];
-	BI7 <= temp_BI[7];
-	OUT <= temp[7:0];
-	CO  <= temp[8] | CO9;
-	N   <= temp[7];
-	HC  <= temp_HC;
-    end
-
-assign V = AI7 ^ BI7 ^ CO ^ N;
-assign Z = ~|OUT;
-
-endmodule
--- a/cores/bbc/rtl/T65/T65.qip
+++ b/cores/bbc/rtl/T65/T65.qip
@@ -0,0 +1,4 @@
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "T65_Pack.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "T65_MCode.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "T65_ALU.vhd"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "T65.vhd"]
--- a/cores/bbc/rtl/T65/T65.vhd
+++ b/cores/bbc/rtl/T65/T65.vhd
@@ -0,0 +1,668 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+-- Ver 313 WoS January 2015
+--   Fixed issue that NMI has to be first if issued the same time as a BRK instruction is latched in
+--   Now all Lorenz CPU tests on FPGAARCADE C64 core (sources used: SVN version 1021) are OK! :D :D :D
+--   This is just a starting point to go for optimizations and detailed fixes (the Lorenz test can't find)
+--
+-- Ver 312 WoS January 2015
+--   Undoc opcode timing fixes for $B3 (LAX iy) and $BB (LAS ay)
+--   Added comments in MCode section to find handling of individual opcodes more easily
+--   All "basic" Lorenz instruction test (individual functional checks, CPUTIMING check) work now with 
+--       actual FPGAARCADE C64 core (sources used: SVN version 1021).
+--
+-- Ver 305, 306, 307, 308, 309, 310, 311 WoS January 2015
+--   Undoc opcode fixes (now all Lorenz test on instruction functionality working, except timing issues on $B3 and $BB):
+--     SAX opcode
+--     SHA opcode
+--     SHX opcode
+--     SHY opcode
+--     SHS opcode
+--     LAS opcode
+--     alternate SBC opcode
+--     fixed NOP with immediate param (caused Lorenz trap test to fail)
+--     IRQ and NMI timing fixes (in conjuction with branches)
+--
+-- Ver 304 WoS December 2014
+--   Undoc opcode fixes:
+--     ARR opcode
+--     ANE/XAA opcode
+--   Corrected issue with NMI/IRQ prio (when asserted the same time)
+--
+-- Ver 303 ost(ML) July 2014
+--   (Sorry for some scratchpad comments that may make little sense)
+--   Mods and some 6502 undocumented instructions.
+--   Not correct opcodes acc. to Lorenz tests (incomplete list):
+--     NOPN    (nop)
+--     NOPZX   (nop + byte 172)
+--     NOPAX   (nop + word da  ...  da:  byte 0)
+--     ASOZ    (byte $07 + byte 172)
+--
+-- Ver 303,302 WoS April 2014
+--     Bugfixes for NMI from foft
+--     Bugfix for BRK command (and its special flag)
+--
+-- Ver 300,301 WoS January 2014
+--     More merging
+--     Bugfixes by ehenciak added, started tidyup *bust*
+--
+-- MikeJ March 2005
+--      Latest version from www.fpgaarcade.com (original www.opencores.org)
+-- ****
+--
+-- 65xx compatible microprocessor core
+--
+-- FPGAARCADE SVN: $Id: T65.vhd 1347 2015-05-27 20:07:34Z wolfgang.scherr $
+--
+-- Copyright (c) 2002...2015
+--               Daniel Wallner (jesus <at> opencores <dot> org)
+--               Mike Johnson   (mikej <at> fpgaarcade <dot> com)
+--               Wolfgang Scherr (WoS <at> pin4 <dot> at>
+--               Morten Leikvoll ()
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author(s), but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- ----- IMPORTANT NOTES -----
+--
+-- Limitations:
+--   65C02 and 65C816 modes are incomplete (and definitely untested after all 6502 undoc fixes)
+--      65C02 supported : inc, dec, phx, plx, phy, ply
+--      65D02 missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8
+--   Some interface signals behave incorrect
+--   NMI interrupt handling not nice, needs further rework (to cycle-based encoding).
+--
+-- Usage:
+--   The enable signal allows clock gating / throttling without using the ready signal.
+--   Set it to constant '1' when using the Clk input as the CPU clock directly.
+--
+--   TAKE CARE you route the DO signal back to the DI signal while R_W_n='0',
+--   otherwise some undocumented opcodes won't work correctly.
+--   EXAMPLE:
+--      CPU : entity work.T65
+--          port map (
+--              R_W_n   => cpu_rwn_s,
+--              [....all other ports....]
+--              DI      => cpu_din_s,
+--              DO      => cpu_dout_s
+--          );
+--      cpu_din_s <= cpu_dout_s when cpu_rwn_s='0' else 
+--                   [....other sources from peripherals and memories...]
+--
+-- ----- IMPORTANT NOTES -----
+--
+
+library IEEE;
+  use IEEE.std_logic_1164.all;
+  use IEEE.numeric_std.all;
+  use work.T65_Pack.all;
+
+entity T65 is
+  port(
+    Mode    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65C816
+    Res_n   : in  std_logic;
+    Enable  : in  std_logic;
+    Clk     : in  std_logic;
+    Rdy     : in  std_logic;
+    Abort_n : in  std_logic;
+    IRQ_n   : in  std_logic;
+    NMI_n   : in  std_logic;
+    SO_n    : in  std_logic;
+    R_W_n   : out std_logic;
+    Sync    : out std_logic;
+    EF      : out std_logic;
+    MF      : out std_logic;
+    XF      : out std_logic;
+    ML_n    : out std_logic;
+    VP_n    : out std_logic;
+    VDA     : out std_logic;
+    VPA     : out std_logic;
+    A       : out std_logic_vector(23 downto 0);
+    DI      : in  std_logic_vector(7 downto 0);
+    DO      : out std_logic_vector(7 downto 0);
+    -- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB)
+    Regs    : out std_logic_vector(63 downto 0);
+    DEBUG   : out T_t65_dbg
+  );
+end T65;
+
+architecture rtl of T65 is
+
+  -- Registers
+  signal ABC, X, Y          : std_logic_vector(15 downto 0);
+  signal P, AD, DL          : std_logic_vector(7 downto 0) :=  x"00";
+  signal PwithB             : std_logic_vector(7 downto 0);--ML:New way to push P with correct B state to stack
+  signal BAH                : std_logic_vector(7 downto 0);
+  signal BAL                : std_logic_vector(8 downto 0);
+  signal PBR                : std_logic_vector(7 downto 0);
+  signal DBR                : std_logic_vector(7 downto 0);
+  signal PC                 : unsigned(15 downto 0);
+  signal S                  : unsigned(15 downto 0);
+  signal EF_i               : std_logic;
+  signal MF_i               : std_logic;
+  signal XF_i               : std_logic;
+
+  signal IR                 : std_logic_vector(7 downto 0);
+  signal MCycle             : std_logic_vector(2 downto 0);
+
+  signal Mode_r             : std_logic_vector(1 downto 0);
+  signal ALU_Op_r           : T_ALU_Op;
+  signal Write_Data_r       : T_Write_Data;
+  signal Set_Addr_To_r      : T_Set_Addr_To;
+  signal PCAdder            : unsigned(8 downto 0);
+
+  signal RstCycle           : std_logic;
+  signal IRQCycle           : std_logic;
+  signal NMICycle           : std_logic;
+
+  signal SO_n_o             : std_logic;
+  signal IRQ_n_o            : std_logic;
+  signal NMI_n_o            : std_logic;
+  signal NMIAct             : std_logic;
+
+  signal Break              : std_logic;
+
+  -- ALU signals
+  signal BusA               : std_logic_vector(7 downto 0);
+  signal BusA_r             : std_logic_vector(7 downto 0);
+  signal BusB               : std_logic_vector(7 downto 0);
+  signal BusB_r             : std_logic_vector(7 downto 0);
+  signal ALU_Q              : std_logic_vector(7 downto 0);
+  signal P_Out              : std_logic_vector(7 downto 0);
+
+  -- Micro code outputs
+  signal LCycle             : std_logic_vector(2 downto 0);
+  signal ALU_Op             : T_ALU_Op;
+  signal Set_BusA_To        : T_Set_BusA_To;
+  signal Set_Addr_To        : T_Set_Addr_To;
+  signal Write_Data         : T_Write_Data;
+  signal Jump               : std_logic_vector(1 downto 0);
+  signal BAAdd              : std_logic_vector(1 downto 0);
+  signal BreakAtNA          : std_logic;
+  signal ADAdd              : std_logic;
+  signal AddY               : std_logic;
+  signal PCAdd              : std_logic;
+  signal Inc_S              : std_logic;
+  signal Dec_S              : std_logic;
+  signal LDA                : std_logic;
+  signal LDP                : std_logic;
+  signal LDX                : std_logic;
+  signal LDY                : std_logic;
+  signal LDS                : std_logic;
+  signal LDDI               : std_logic;
+  signal LDALU              : std_logic;
+  signal LDAD               : std_logic;
+  signal LDBAL              : std_logic;
+  signal LDBAH              : std_logic;
+  signal SaveP              : std_logic;
+  signal Write              : std_logic;
+
+  signal Res_n_i        : std_logic;
+  signal Res_n_d        : std_logic;
+
+  signal really_rdy     : std_logic;
+  signal WRn_i          : std_logic;
+
+  signal NMI_entered    : std_logic;
+
+begin
+  -- gate Rdy with read/write to make an "OK, it's really OK to stop the processor 
+  really_rdy <= Rdy or not(WRn_i);
+  Sync <= '1' when MCycle = "000" else '0';
+  EF <= EF_i;
+  MF <= MF_i;
+  XF <= XF_i;
+  R_W_n <= WRn_i;
+  ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
+  VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
+  VDA <= '1' when Set_Addr_To_r /= Set_Addr_To_PBR else '0';
+  VPA <= '1' when Jump(1) = '0' else '0';
+
+  -- debugging signals
+  DEBUG.I <= IR;
+  DEBUG.A <= ABC(7 downto 0);
+  DEBUG.X <= X(7 downto 0);
+  DEBUG.Y <= Y(7 downto 0);
+  DEBUG.S <= std_logic_vector(S(7 downto 0));
+  DEBUG.P <= P;
+
+  Regs <= std_logic_vector(PC) & std_logic_vector(S)& P & Y(7 downto 0) & X(7 downto 0) & ABC(7 downto 0);
+
+  mcode : entity work.T65_MCode
+    port map(
+--inputs
+      Mode        => Mode_r,
+      IR          => IR,
+      MCycle      => MCycle,
+      P           => P,
+--outputs
+      LCycle      => LCycle,
+      ALU_Op      => ALU_Op,
+      Set_BusA_To => Set_BusA_To,
+      Set_Addr_To => Set_Addr_To,
+      Write_Data  => Write_Data,
+      Jump        => Jump,
+      BAAdd       => BAAdd,
+      BreakAtNA   => BreakAtNA,
+      ADAdd       => ADAdd,
+      AddY        => AddY,
+      PCAdd       => PCAdd,
+      Inc_S       => Inc_S,
+      Dec_S       => Dec_S,
+      LDA         => LDA,
+      LDP         => LDP,
+      LDX         => LDX,
+      LDY         => LDY,
+      LDS         => LDS,
+      LDDI        => LDDI,
+      LDALU       => LDALU,
+      LDAD        => LDAD,
+      LDBAL       => LDBAL,
+      LDBAH       => LDBAH,
+      SaveP       => SaveP,
+      Write       => Write
+      );
+
+  alu : entity work.T65_ALU
+    port map(
+      Mode => Mode_r,
+      Op => ALU_Op_r,
+      BusA => BusA_r,
+      BusB => BusB,
+      P_In => P,
+      P_Out => P_Out,
+      Q => ALU_Q
+      );
+
+  -- the 65xx design requires at least two clock cycles before
+  -- starting its reset sequence (according to datasheet)
+  process (Res_n, Clk)
+  begin
+    if Res_n = '0' then
+      Res_n_i <= '0';
+      Res_n_d <= '0';
+    elsif Clk'event and Clk = '1' then
+      Res_n_i <= Res_n_d;
+      Res_n_d <= '1';
+    end if;
+  end process;
+
+  process (Res_n_i, Clk)
+  begin
+    if Res_n_i = '0' then
+      PC <= (others => '0');  -- Program Counter
+      IR <= "00000000";
+      S <= (others => '0');       -- Dummy
+      PBR <= (others => '0');
+      DBR <= (others => '0');
+
+      Mode_r <= (others => '0');
+      ALU_Op_r <= ALU_OP_BIT;
+      Write_Data_r <= Write_Data_DL;
+      Set_Addr_To_r <= Set_Addr_To_PBR;
+
+      WRn_i <= '1';
+      EF_i <= '1';
+      MF_i <= '1';
+      XF_i <= '1';
+
+    elsif Clk'event and Clk = '1' then  
+      if (Enable = '1') then
+        if (really_rdy = '1') then
+          WRn_i <= not Write or RstCycle;
+
+          PBR <= (others => '1'); -- Dummy
+          DBR <= (others => '1'); -- Dummy
+          EF_i <= '0';    -- Dummy
+          MF_i <= '0';    -- Dummy
+          XF_i <= '0';    -- Dummy
+
+          if MCycle  = "000" then
+            Mode_r <= Mode;
+
+            if IRQCycle = '0' and NMICycle = '0' then
+              PC <= PC + 1;
+            end if;
+
+            if IRQCycle = '1' or NMICycle = '1' then
+              IR <= "00000000";
+            else
+              IR <= DI;
+            end if;
+
+            if LDS = '1' then -- LAS won't work properly if not limited to machine cycle 0
+              S(7 downto 0) <= unsigned(ALU_Q);
+            end if;
+          end if;
+
+          ALU_Op_r <= ALU_Op;
+          Write_Data_r <= Write_Data;
+          if Break = '1' then
+            Set_Addr_To_r <= Set_Addr_To_PBR;
+          else
+            Set_Addr_To_r <= Set_Addr_To;
+          end if;
+
+          if Inc_S = '1' then
+            S <= S + 1;
+          end if;
+          if Dec_S = '1' and RstCycle = '0' then
+            S <= S - 1;
+          end if;
+
+          if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
+            PC <= PC + 1;
+          end if;
+          --
+          -- jump control logic
+          --
+          case Jump is
+            when "01" =>
+              PC <= PC + 1;
+            when "10" =>
+              PC <= unsigned(DI & DL);
+            when "11" =>
+              if PCAdder(8) = '1' then
+                if DL(7) = '0' then
+                  PC(15 downto 8) <= PC(15 downto 8) + 1;
+                else
+                  PC(15 downto 8) <= PC(15 downto 8) - 1;
+                end if;
+              end if;
+              PC(7 downto 0) <= PCAdder(7 downto 0);
+            when others => null;
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
+         else "0" & PC(7 downto 0);
+
+  process (Res_n_i, Clk)
+    variable tmpP:std_logic_vector(7 downto 0);--Lets try to handle loading P at mcycle=0 and set/clk flags at same cycle
+  begin
+    if Res_n_i = '0' then
+      P <= x"00"; -- ensure we have nothing set on reset
+    elsif Clk'event and Clk = '1' then
+      tmpP:=P;
+      if (Enable = '1') then
+        if (really_rdy = '1') then
+          if MCycle = "000" then
+            if LDA = '1' then
+              ABC(7 downto 0) <= ALU_Q;
+            end if;
+            if LDX = '1' then
+              X(7 downto 0) <= ALU_Q;
+            end if;
+            if LDY = '1' then
+              Y(7 downto 0) <= ALU_Q;
+            end if;
+            if (LDA or LDX or LDY) = '1' then
+              tmpP:=P_Out;
+            end if;
+          end if;
+          if SaveP = '1' then
+            tmpP:=P_Out;
+          end if;
+          if LDP = '1' then
+            tmpP:=ALU_Q;
+          end if;
+          if IR(4 downto 0) = "11000" then
+            case IR(7 downto 5) is
+            when "000" =>--0x18(clc)
+              tmpP(Flag_C) := '0';
+            when "001" =>--0x38(sec)
+              tmpP(Flag_C) := '1';
+            when "010" =>--0x58(cli)
+              tmpP(Flag_I) := '0';
+            when "011" =>--0x78(sei)
+              tmpP(Flag_I) := '1';
+            when "101" =>--0xb8(clv)
+              tmpP(Flag_V) := '0';
+            when "110" =>--0xd8(cld)
+              tmpP(Flag_D) := '0';
+            when "111" =>--0xf8(sed)
+              tmpP(Flag_D) := '1';
+            when others =>
+            end case;
+          end if;
+          tmpP(Flag_B) := '1';
+          if IR = "00000000" and MCycle = "100" and RstCycle = '0' then
+            --This should happen after P has been pushed to stack
+            tmpP(Flag_I) := '1';
+          end if;
+          if SO_n_o = '1' and SO_n = '0' then
+            tmpP(Flag_V) := '1';
+          end if;
+          if RstCycle = '1' then
+            tmpP(Flag_I) := '1';
+            tmpP(Flag_D) := '0';
+          end if;
+          tmpP(Flag_1) := '1';
+
+          P<=tmpP;--new way
+
+          SO_n_o <= SO_n;
+          if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510), not best way yet, though - but works...
+            IRQ_n_o <= IRQ_n;
+          end if;
+        end if;
+        -- detect nmi even if not rdy
+        if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510) not best way yet, though - but works...
+          NMI_n_o <= NMI_n;
+        end if;
+      end if;
+    end if;
+  end process;
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+
+  process (Res_n_i, Clk)
+  begin
+    if Res_n_i = '0' then
+      BusA_r <= (others => '0');
+      BusB <= (others => '0');
+      BusB_r <= (others => '0');
+      AD <= (others => '0');
+      BAL <= (others => '0');
+      BAH <= (others => '0');
+      DL <= (others => '0');
+    elsif Clk'event and Clk = '1' then
+      if (Enable = '1') then
+        NMI_entered <= '0';
+        if (really_rdy = '1') then
+          BusA_r <= BusA;
+          BusB <= DI;
+
+          -- not really nice, but no better way found yet !
+          if Set_Addr_To_r = Set_Addr_To_PBR or Set_Addr_To_r = Set_Addr_To_ZPG then
+            BusB_r <= std_logic_vector(unsigned(DI(7 downto 0)) + 1); -- required for SHA
+          end if;
+
+          case BAAdd is
+          when "01" =>
+            -- BA Inc
+            AD <= std_logic_vector(unsigned(AD) + 1);
+            BAL <= std_logic_vector(unsigned(BAL) + 1);
+          when "10" =>
+            -- BA Add
+            BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
+          when "11" =>
+            -- BA Adj
+            if BAL(8) = '1' then
+              BAH <= std_logic_vector(unsigned(BAH) + 1);
+            end if;
+          when others =>
+          end case;
+
+          -- modified to use Y register as well
+          if ADAdd = '1' then
+            if (AddY = '1') then
+              AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
+            else
+              AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
+            end if;
+          end if;
+
+          if IR = "00000000" then
+            BAL <= (others => '1');
+            BAH <= (others => '1');
+            if RstCycle = '1' then
+              BAL(2 downto 0) <= "100";
+            elsif NMICycle = '1' or (NMIAct = '1' and MCycle="100") or NMI_entered='1' then
+              BAL(2 downto 0) <= "010";
+              if MCycle="100" then
+                NMI_entered <= '1';
+              end if;
+            else
+              BAL(2 downto 0) <= "110";
+            end if;
+            if Set_addr_To_r = Set_Addr_To_BA then
+              BAL(0) <= '1';
+            end if;
+          end if;
+
+          if LDDI = '1' then
+            DL <= DI;
+          end if;
+          if LDALU = '1' then
+            DL <= ALU_Q;
+          end if;
+          if LDAD = '1' then
+            AD <= DI;
+          end if;
+          if LDBAL = '1' then
+            BAL(7 downto 0) <= DI;
+          end if;
+          if LDBAH = '1' then
+            BAH <= DI;
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
+
+  with Set_BusA_To select
+    BusA <=
+      DI                                    when Set_BusA_To_DI,
+      ABC(7 downto 0)                       when Set_BusA_To_ABC,
+      X(7 downto 0)                         when Set_BusA_To_X,
+      Y(7 downto 0)                         when Set_BusA_To_Y,
+      std_logic_vector(S(7 downto 0))       when Set_BusA_To_S,
+      P                                     when Set_BusA_To_P,
+      ABC(7 downto 0) and DI                when Set_BusA_To_DA,
+      (ABC(7 downto 0) or x"ee") and DI     when Set_BusA_To_DAO,--ee for OAL instruction. constant may be different on other platforms.TODO:Move to generics
+      (ABC(7 downto 0) or x"ee") and DI and X(7 downto 0)    when Set_BusA_To_DAX,--XAA, ee for OAL instruction. constant may be different on other platforms.TODO:Move to generics
+      ABC(7 downto 0) and X(7 downto 0)     when Set_BusA_To_AAX,--SAX, SHA
+      (others => '-')                       when Set_BusA_To_DONTCARE;--Can probably remove this
+
+  with Set_Addr_To_r select
+    A <=
+      "0000000000000001" & std_logic_vector(S(7 downto 0))                            when Set_Addr_To_SP,
+      DBR & "00000000" & AD                                                           when Set_Addr_To_ZPG,
+      "00000000" & BAH & BAL(7 downto 0)                                              when Set_Addr_To_BA,
+      PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when Set_Addr_To_PBR;
+
+  -- This is the P that gets pushed on stack with correct B flag. I'm not sure if NMI also clears B, but I guess it does.
+  PwithB<=(P and x"ef") when (IRQCycle='1' or NMICycle='1') else P;
+
+  with Write_Data_r select
+    DO <=
+      DL                                  when Write_Data_DL,
+      ABC(7 downto 0)                     when Write_Data_ABC,
+      X(7 downto 0)                       when Write_Data_X,
+      Y(7 downto 0)                       when Write_Data_Y,
+      std_logic_vector(S(7 downto 0))     when Write_Data_S,
+      PwithB                              when Write_Data_P,
+      std_logic_vector(PC(7 downto 0))    when Write_Data_PCL,
+      std_logic_vector(PC(15 downto 8))   when Write_Data_PCH,
+      ABC(7 downto 0) and X(7 downto 0)   when Write_Data_AX,
+      ABC(7 downto 0) and X(7 downto 0) and BusB_r(7 downto 0) when Write_Data_AXB, -- no better way found yet...
+      X(7 downto 0) and BusB_r(7 downto 0) when Write_Data_XB, -- no better way found yet...
+      Y(7 downto 0) and BusB_r(7 downto 0) when Write_Data_YB, -- no better way found yet...
+      (others=>'-')                       when Write_Data_DONTCARE;--Can probably remove this
+
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+
+  process (Res_n_i, Clk)
+  begin
+    if Res_n_i = '0' then
+      MCycle <= "001";
+      RstCycle <= '1';
+      IRQCycle <= '0';
+      NMICycle <= '0';
+      NMIAct <= '0';
+    elsif Clk'event and Clk = '1' then
+      if (Enable = '1') then
+        if (really_rdy = '1') then
+          if MCycle = LCycle or Break = '1' then
+            MCycle <= "000";
+            RstCycle <= '0';
+            IRQCycle <= '0';
+            NMICycle <= '0';
+            if NMIAct = '1' and IR/=x"00" then -- delay NMI further if we just executed a BRK
+              NMICycle <= '1';
+              NMIAct <= '0'; -- reset NMI edge detector if we start processing the NMI
+            elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
+              IRQCycle <= '1';
+            end if;
+          else
+            MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+          end if;
+        end if;
+        --detect NMI even if not rdy    
+        if NMI_n_o = '1' and (NMI_n = '0' and (IR(4 downto 0)/="10000" or Jump/="01")) then -- branches have influence on NMI start (not best way yet, though - but works...)
+          NMIAct <= '1';
+        end if;
+        -- we entered NMI during BRK instruction
+        if NMI_entered='1' then
+          NMIAct <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+end;
--- a/cores/bbc/rtl/T65/T65_ALU.vhd
+++ b/cores/bbc/rtl/T65/T65_ALU.vhd
@@ -0,0 +1,293 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+-- See list of changes in T65 top file (T65.vhd)...
+--
+-- ****
+-- 65xx compatible microprocessor core
+--
+-- FPGAARCADE SVN: $Id: T65_ALU.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
+--
+-- Copyright (c) 2002...2015
+--               Daniel Wallner (jesus <at> opencores <dot> org)
+--               Mike Johnson   (mikej <at> fpgaarcade <dot> com)
+--               Wolfgang Scherr (WoS <at> pin4 <dot> at>
+--               Morten Leikvoll ()
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author(s), but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- Limitations :
+--   See in T65 top file (T65.vhd)...
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T65_Pack.all;
+
+entity T65_ALU is
+  port(
+    Mode    : in std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65816
+    Op      : in T_ALU_OP;
+    BusA    : in std_logic_vector(7 downto 0);
+    BusB    : in std_logic_vector(7 downto 0);
+    P_In    : in std_logic_vector(7 downto 0);
+    P_Out   : out std_logic_vector(7 downto 0);
+    Q       : out std_logic_vector(7 downto 0)
+  );
+end T65_ALU;
+
+architecture rtl of T65_ALU is
+
+  -- AddSub variables (temporary signals)
+  signal      ADC_Z           : std_logic;
+  signal      ADC_C           : std_logic;
+  signal      ADC_V           : std_logic;
+  signal      ADC_N           : std_logic;
+  signal      ADC_Q           : std_logic_vector(7 downto 0);
+  signal      SBC_Z           : std_logic;
+  signal      SBC_C           : std_logic;
+  signal      SBC_V           : std_logic;
+  signal      SBC_N           : std_logic;
+  signal      SBC_Q           : std_logic_vector(7 downto 0);
+  signal      SBX_Q           : std_logic_vector(7 downto 0);
+
+begin
+
+  process (P_In, BusA, BusB)
+    variable AL : unsigned(6 downto 0);
+    variable AH : unsigned(6 downto 0);
+    variable C : std_logic;
+  begin
+    AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
+    AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
+
+-- pragma translate_off
+      if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
+      if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
+-- pragma translate_on
+
+    if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
+      ADC_Z <= '1';
+    else
+      ADC_Z <= '0';
+    end if;
+
+    if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
+      AL(6 downto 1) := AL(6 downto 1) + 6;
+    end if;
+
+    C := AL(6) or AL(5);
+    AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
+
+    ADC_N <= AH(4);
+    ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
+
+-- pragma translate_off
+      if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
+-- pragma translate_on
+
+    if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
+      AH(6 downto 1) := AH(6 downto 1) + 6;
+    end if;
+
+    ADC_C <= AH(6) or AH(5);
+
+    ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
+  end process;
+
+  process (Op, P_In, BusA, BusB)
+    variable AL : unsigned(6 downto 0);
+    variable AH : unsigned(5 downto 0);
+    variable C : std_logic;
+    variable CT : std_logic;
+  begin
+    CT:='0';
+    if(  Op=ALU_OP_AND or	--"0001" These OpCodes used to have LSB set
+         Op=ALU_OP_ADC or	--"0011"
+         Op=ALU_OP_EQ2 or	--"0101"
+         Op=ALU_OP_SBC or	--"0111"
+         Op=ALU_OP_ROL or	--"1001"
+         Op=ALU_OP_ROR or	--"1011"
+--         Op=ALU_OP_EQ3 or	--"1101"
+         Op=ALU_OP_INC		--"1111"
+      ) then
+      CT:='1';
+    end if;
+
+    C := P_In(Flag_C) or not CT;--was: or not Op(0);
+    AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
+    AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
+
+    -- pragma translate_off
+    if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
+    if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
+    -- pragma translate_on
+
+    if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
+      SBC_Z <= '1';
+    else
+      SBC_Z <= '0';
+    end if;
+
+    SBC_C <= not AH(5);
+    SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
+    SBC_N <= AH(4);
+
+    SBX_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
+
+    if P_In(Flag_D) = '1' then
+      if AL(5) = '1' then
+        AL(5 downto 1) := AL(5 downto 1) - 6;
+      end if;
+      AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
+      if AH(5) = '1' then
+        AH(5 downto 1) := AH(5 downto 1) - 6;
+      end if;
+    end if;
+
+    SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
+  end process;
+
+  process (Op, P_In, BusA, BusB,
+      ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
+      SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q,
+      SBX_Q)
+    variable Q_t : std_logic_vector(7 downto 0);
+    variable Q2_t : std_logic_vector(7 downto 0);
+  begin
+    -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
+    -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
+    P_Out <= P_In;
+    Q_t := BusA;
+    Q2_t := BusA;
+    case Op is
+      when ALU_OP_OR=>
+        Q_t := BusA or BusB;
+      when ALU_OP_AND=>
+        Q_t := BusA and BusB;
+      when ALU_OP_EOR=>
+        Q_t := BusA xor BusB;
+      when ALU_OP_ADC=>
+        P_Out(Flag_V) <= ADC_V;
+        P_Out(Flag_C) <= ADC_C;
+        Q_t := ADC_Q;
+      when ALU_OP_CMP=>
+        P_Out(Flag_C) <= SBC_C;
+      when ALU_OP_SAX=>
+        P_Out(Flag_C) <= SBC_C;
+        Q_t := SBX_Q;  -- undoc: subtract (A & X) - (immediate)
+      when ALU_OP_SBC=>
+        P_Out(Flag_V) <= SBC_V;
+        P_Out(Flag_C) <= SBC_C;
+        Q_t := SBC_Q;  -- undoc: subtract  (A & X) - (immediate), then decimal correction
+      when ALU_OP_ASL=>
+        Q_t := BusA(6 downto 0) & "0";
+        P_Out(Flag_C) <= BusA(7);
+      when ALU_OP_ROL=>
+        Q_t := BusA(6 downto 0) & P_In(Flag_C);
+        P_Out(Flag_C) <= BusA(7);
+      when ALU_OP_LSR=>
+        Q_t := "0" & BusA(7 downto 1);
+        P_Out(Flag_C) <= BusA(0);
+      when ALU_OP_ROR=>
+        Q_t := P_In(Flag_C) & BusA(7 downto 1);
+        P_Out(Flag_C) <= BusA(0);
+      when ALU_OP_ARR=> 
+        Q_t := P_In(Flag_C) & (BusA(7 downto 1) and BusB(7 downto 1));
+        P_Out(Flag_V) <= Q_t(5) xor Q_t(6);
+        Q2_t := Q_t;
+        if P_In(Flag_D)='1' then
+          if (BusA(3 downto 0) and BusB(3 downto 0)) > "0100" then
+            Q2_t(3 downto 0) := std_logic_vector(unsigned(Q_t(3 downto 0)) + x"6");
+          end if;
+          if (BusA(7 downto 4) and BusB(7 downto 4)) > "0100" then
+            Q2_t(7 downto 4) := std_logic_vector(unsigned(Q_t(7 downto 4)) + x"6");
+            P_Out(Flag_C) <= '1';
+          else
+            P_Out(Flag_C) <= '0';
+          end if;
+        else
+          P_Out(Flag_C) <= Q_t(6);
+        end if;
+      when ALU_OP_BIT=>
+        P_Out(Flag_V) <= BusB(6);
+      when ALU_OP_DEC=>
+        Q_t := std_logic_vector(unsigned(BusA) - 1);
+      when ALU_OP_INC=>
+        Q_t := std_logic_vector(unsigned(BusA) + 1);
+      when others =>
+        null;
+      --EQ1,EQ2,EQ3 passes BusA to Q_t and P_in to P_out
+    end case;
+
+    case Op is
+      when ALU_OP_ADC=>
+        P_Out(Flag_N) <= ADC_N;
+        P_Out(Flag_Z) <= ADC_Z;
+      when ALU_OP_CMP|ALU_OP_SBC|ALU_OP_SAX=>
+        P_Out(Flag_N) <= SBC_N;
+        P_Out(Flag_Z) <= SBC_Z;
+      when ALU_OP_EQ1=>--dont touch P
+      when ALU_OP_BIT=>
+        P_Out(Flag_N) <= BusB(7);
+        if (BusA and BusB) = "00000000" then
+          P_Out(Flag_Z) <= '1';
+        else
+          P_Out(Flag_Z) <= '0';
+        end if;
+      when ALU_OP_ANC=>
+        P_Out(Flag_N) <= Q_t(7);
+        P_Out(Flag_C) <= Q_t(7);
+        if Q_t = "00000000" then
+          P_Out(Flag_Z) <= '1';
+        else
+          P_Out(Flag_Z) <= '0';
+        end if;
+      when others =>
+        P_Out(Flag_N) <= Q_t(7);
+        if Q_t = "00000000" then
+          P_Out(Flag_Z) <= '1';
+        else
+          P_Out(Flag_Z) <= '0';
+        end if;
+    end case;
+
+    if Op=ALU_OP_ARR then
+      -- handled above in ARR code
+      Q <= Q2_t;
+    else
+      Q <= Q_t;
+    end if;
+  end process;
+
+end;
--- a/cores/bbc/rtl/T65/T65_MCode.vhd
+++ b/cores/bbc/rtl/T65/T65_MCode.vhd
--- a/cores/bbc/rtl/T65/T65_Pack.vhd
+++ b/cores/bbc/rtl/T65/T65_Pack.vhd
@@ -0,0 +1,180 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+-- See list of changes in T65 top file (T65.vhd)...
+--
+-- ****
+-- 65xx compatible microprocessor core
+--
+-- FPGAARCADE SVN: $Id: T65_Pack.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
+--
+-- Copyright (c) 2002...2015
+--               Daniel Wallner (jesus <at> opencores <dot> org)
+--               Mike Johnson   (mikej <at> fpgaarcade <dot> com)
+--               Wolfgang Scherr (WoS <at> pin4 <dot> at>
+--               Morten Leikvoll ()
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author(s), but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- Limitations :
+--   See in T65 top file (T65.vhd)...
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T65_Pack is
+
+  constant Flag_C : integer := 0;
+  constant Flag_Z : integer := 1;
+  constant Flag_I : integer := 2;
+  constant Flag_D : integer := 3;
+  constant Flag_B : integer := 4;
+  constant Flag_1 : integer := 5;
+  constant Flag_V : integer := 6;
+  constant Flag_N : integer := 7;
+
+  subtype T_Lcycle is std_logic_vector(2 downto 0);
+  constant Cycle_sync :T_Lcycle:="000";
+  constant Cycle_1    :T_Lcycle:="001";
+  constant Cycle_2    :T_Lcycle:="010";
+  constant Cycle_3    :T_Lcycle:="011";
+  constant Cycle_4    :T_Lcycle:="100";
+  constant Cycle_5    :T_Lcycle:="101";
+  constant Cycle_6    :T_Lcycle:="110";
+  constant Cycle_7    :T_Lcycle:="111";
+
+  function CycleNext(c:T_Lcycle) return T_Lcycle;
+
+  type T_Set_BusA_To is
+  (
+    Set_BusA_To_DI,
+    Set_BusA_To_ABC,
+    Set_BusA_To_X,
+    Set_BusA_To_Y,
+    Set_BusA_To_S,
+    Set_BusA_To_P,
+    Set_BusA_To_DA,
+    Set_BusA_To_DAO,
+    Set_BusA_To_DAX,
+    Set_BusA_To_AAX,
+    Set_BusA_To_DONTCARE
+  );
+  
+  type T_Set_Addr_To is
+  (
+    Set_Addr_To_PBR,
+    Set_Addr_To_SP,
+    Set_Addr_To_ZPG,
+    Set_Addr_To_BA
+  );
+  
+  type T_Write_Data is
+  (
+    Write_Data_DL,
+    Write_Data_ABC,
+    Write_Data_X,
+    Write_Data_Y,
+    Write_Data_S,
+    Write_Data_P,
+    Write_Data_PCL,
+    Write_Data_PCH,
+    Write_Data_AX,
+    Write_Data_AXB,
+    Write_Data_XB,
+    Write_Data_YB,
+    Write_Data_DONTCARE
+  );
+  
+  type T_ALU_OP is
+  (
+    ALU_OP_OR,  --"0000"
+    ALU_OP_AND,  --"0001"
+    ALU_OP_EOR,  --"0010"
+    ALU_OP_ADC,  --"0011"
+    ALU_OP_EQ1,  --"0100" EQ1 does not change N,Z flags, EQ2/3 does.
+    ALU_OP_EQ2,  --"0101" Not sure yet whats the difference between EQ2&3. They seem to do the same ALU op
+    ALU_OP_CMP,  --"0110"
+    ALU_OP_SBC,  --"0111"
+    ALU_OP_ASL,  --"1000"
+    ALU_OP_ROL,  --"1001"
+    ALU_OP_LSR,  --"1010"
+    ALU_OP_ROR,  --"1011"
+    ALU_OP_BIT,  --"1100"
+--    ALU_OP_EQ3,  --"1101"
+    ALU_OP_DEC,  --"1110"
+    ALU_OP_INC,  --"1111"
+    ALU_OP_ARR,
+    ALU_OP_ANC,
+    ALU_OP_SAX,
+    ALU_OP_XAA
+--    ALU_OP_UNDEF--"----"--may be replaced with any?
+  );
+
+  type T_t65_dbg is record
+    I     : std_logic_vector(7 downto 0); -- instruction
+    A     : std_logic_vector(7 downto 0); -- A reg
+    X     : std_logic_vector(7 downto 0); -- X reg
+    Y     : std_logic_vector(7 downto 0); -- Y reg
+    S     : std_logic_vector(7 downto 0); -- stack pointer
+    P     : std_logic_vector(7 downto 0); -- processor flags
+  end record;
+
+end;
+
+package body T65_Pack is
+
+  function CycleNext(c:T_Lcycle) return T_Lcycle is
+  begin
+    case(c) is
+    when Cycle_sync=>
+      return Cycle_1;
+    when Cycle_1=>
+      return Cycle_2;
+    when Cycle_2=>
+      return Cycle_3;
+    when Cycle_3=>
+      return Cycle_4;
+    when Cycle_4=>
+      return Cycle_5;
+    when Cycle_5=>
+      return Cycle_6;
+    when Cycle_6=>
+      return Cycle_7;
+    when Cycle_7=>
+      return Cycle_sync;
+    when others=>
+      return Cycle_sync;
+    end case;
+  end CycleNext;
+
+end T65_Pack;
--- a/cores/bbc/rtl/bbc.v
+++ b/cores/bbc/rtl/bbc.v
@@ -38,11 +38,11 @@ module bbc(

 	// externally pressed "shift" key for autoboot
 	input          SHIFT,
-	
-	// expose pins required for mmc
-	output [7:0]   user_via_pb_out,
-	input          user_via_cb1_in,
-	input          user_via_cb2_in,
+
+	output         SDSS,
+	output         SDCLK,
+	output         SDMOSI,
+	input          SDMISO,
 	
 	// analog joystick input 
 	input [1:0]	 	joy_but,
@@ -115,7 +115,6 @@ wire    cpu_we;

 wire    [23:0] cpu_a; 
 wire    [7:0] cpu_di; 
-reg     [7:0] cpu_di_r;
 wire    [7:0] cpu_do; 

 //  CRTC signals
@@ -176,7 +175,8 @@ wire    [7:0] sound_di;
 wire    [7:0] sound_ao;

 //  System VIA signals
-wire    [7:0] sys_via_do; 
+wire    [7:0] sys_via_do;
+reg     [7:0] sys_via_do_r;
 wire    sys_via_do_oe_n; 
 wire    sys_via_irq_n; 
 wire     sys_via_ca1_in; 
@@ -197,7 +197,8 @@ wire    [7:0] sys_via_pb_out;
 wire    [7:0] sys_via_pb_oe_n; 

 //  User VIA signals
-wire    [7:0] user_via_do; 
+wire    [7:0] user_via_do;
+reg     [7:0] user_via_do_r;
 wire    user_via_do_oe_n; 
 wire    user_via_irq_n; 
 reg     user_via_ca1_in; 
@@ -207,16 +208,28 @@ wire    user_via_ca2_oe_n;
 wire    [7:0] user_via_pa_in; 
 wire    [7:0] user_via_pa_out; 
 wire    [7:0] user_via_pa_oe_n; 
-//TH wire     user_via_cb1_in; 
+wire     user_via_cb1_in; 
 wire    user_via_cb1_out; 
 wire    user_via_cb1_oe_n; 
-//TH wire     user_via_cb2_in; 
+wire     user_via_cb2_in; 
 wire    user_via_cb2_out; 
 wire    user_via_cb2_oe_n; 
 wire    [7:0] user_via_pb_in; 
-//TH wire    [7:0] user_via_pb_out; 
+wire    [7:0] user_via_pb_out; 
 wire    [7:0] user_via_pb_oe_n; 

+// MMC
+// SDCLK is driven from either PB1 or CB1 depending on the SR Mode
+wire   sdclk_int = ~user_via_pb_oe_n[1] ? user_via_pb_out[1] : 
+						(~user_via_cb1_oe_n ? user_via_cb1_out : 1);
+assign SDCLK = sdclk_int;
+assign user_via_cb1_in = sdclk_int;
+// SDMOSI is always driven from PB0
+assign SDMOSI = ~user_via_pb_oe_n[0] ? user_via_pb_out[0] : 1;
+// SDMISO is always read from CB2
+assign user_via_cb2_in = SDMISO;
+assign SDSS = 0;
+
 // calulation for display address

 reg     [3:0]  process_3_aa; 
@@ -270,65 +283,62 @@ address_decode ADDRDECODE(
 	.mhz1_enable(mhz1_enable)
 );

-/*input clk;              // CPU clock 
-input reset;            // reset signal
-output reg [15:0] AB;   // address bus
-input [7:0] DI;         // data in, read bus
-output [7:0] DO;        // data out, write bus
-output WE;              // write enable
-input IRQ;              // interrupt request
-input NMI;              // non-maskable interrupt request
-input RDY;              // Ready signal. Pauses CPU when RDY=0 
-*/
-
-cpu CPU (	
-	.clk	( CLK32M_I	),
-	.reset 	( ~reset_n	),
+T65 CPU (
+	.Mode   (CPU_MODE),
+	.Res_n  (reset_n),
+	.Enable (cpu_clken),
+	.Clk    (CLK32M_I),
+	.Rdy    (cpu_clken),
+	.Abort_n(cpu_abort_n),
+	.NMI_n  (cpu_nmi_n),
+	.IRQ_n  (cpu_irq_n),
+	.SO_n   (cpu_so_n),
+	.R_W_n  (cpu_r_nw),
 	
-    .IRQ	( ~cpu_irq_n	),
-	.NMI	( ~cpu_nmi_n	),
-	
-    .WE     ( cpu_we     	),
-	.AB		( cpu_a[15:0] ),
-	.DI		( cpu_di_r		),
-	.DO		( cpu_do		),
-	.RDY	( cpu_clken     )
+	.DI     (cpu_di),
+	.DO     (cpu_do),
+	.A      (cpu_a)
 );

-assign cpu_r_nw = ~cpu_we;
-

 m6522 SYS_VIA (	
 	  //  System VIA is reset by power on reset only
-	 .ENA_4(mhz4_clken),
-	 .CLK(CLK32M_I),
+
 	 .I_RS(cpu_a[3:0]),
 	 .I_DATA(cpu_do),
 	 .O_DATA(sys_via_do),
 	 .O_DATA_OE_L(sys_via_do_oe_n),
+
 	 .I_RW_L(cpu_r_nw),
 	 .I_CS1(sys_via_enable),
 	 .I_CS2_L(1'b 0), // nCS2(1'b 0),	 
 	 .O_IRQ_L(sys_via_irq_n),
- 	 .I_P2_H(mhz1_clken),
-	 .RESET_L(reset_n),
-	 
+
 	 .I_CA1(sys_via_ca1_in),
 	 .I_CA2(sys_via_ca2_in),
 	 .O_CA2(sys_via_ca2_out),
 	 .O_CA2_OE_L(sys_via_ca2_oe_n),
+
 	 .I_PA(sys_via_pa_in),
 	 .O_PA(sys_via_pa_out),
 	 .O_PA_OE_L(sys_via_pa_oe_n),
+
 	 .I_CB1(sys_via_cb1_in),
 	 .O_CB1(sys_via_cb1_out),
 	 .O_CB1_OE_L(sys_via_cb1_oe_n),
+
 	 .I_CB2(sys_via_cb2_in),
 	 .O_CB2(sys_via_cb2_out),
 	 .O_CB2_OE_L(sys_via_cb2_oe_n),
+
 	 .I_PB(sys_via_pb_in),
 	 .O_PB(sys_via_pb_out),
-	 .O_PB_OE_L(sys_via_pb_oe_n)
+	 .O_PB_OE_L(sys_via_pb_oe_n),
+
+	 .I_P2_H(mhz1_clken),
+	 .RESET_L(reset_n),
+	 .ENA_4(mhz4_clken),
+	 .CLK(CLK32M_I)
 );

 m6522 USER_VIA (	
@@ -482,12 +492,19 @@ saa5050 TELETEXT (

 initial begin : via_init   

-	//user_via_cb1_in = 1'b 0;   
-   user_via_ca2_in = 1'b 0;   
-   user_via_ca1_in = 1'b 0; 
-   user_via_ca2_in = 1'b 0;	
-   crtc_lpstb = 1'b 0;   
-	
+   user_via_ca1_in = 1'b 0;
+   user_via_ca2_in = 1'b 0;
+   crtc_lpstb = 1'b 0;
+
+end
+
+// This is needed as in v003 of the 6522 data out is only valid while I_P2_H is asserted
+// I_P2_H is driven from mhz1_clken
+always @(posedge CLK32M_I) begin 
+	if (mhz1_clken) begin
+		user_via_do_r <= user_via_do;
+		sys_via_do_r  <= sys_via_do;
+	end
 end

 // rom select latch
@@ -519,11 +536,6 @@ always @(posedge CLK32M_I) begin
 				
 		end
 		
-        // retard DI by one cpu clock cycle 
-        if (cpu_clken === 1'b1) begin
-            cpu_di_r <= cpu_di;
-        end 
-        
 	end
 end
 	
@@ -619,8 +631,8 @@ assign cpu_di = ram_enable === 1'b 1 ? MEM_DI :
 	mos_enable === 1'b 1 ? MEM_DI :
 	crtc_enable === 1'b 1 ? crtc_do : 
 	acia_enable === 1'b 1 ? 8'b 00000010 : 
-	sys_via_enable === 1'b 1 ? sys_via_do : 
-	user_via_enable === 1'b 1 ? user_via_do : 
+	sys_via_enable === 1'b 1 ? sys_via_do_r : 
+	user_via_enable === 1'b 1 ? user_via_do_r : 
 	adc_enable === 1'b 1 ? adc_do : 
 	//tube_enable === 1'b 1 ? tube_do : 
 	//adlc_enable === 1'b 1 ? bbcddr_out :
--- a/cores/bbc/rtl/cpu.v
+++ b/cores/bbc/rtl/cpu.v
--- a/cores/bbc/rtl/m6522.v
+++ b/cores/bbc/rtl/m6522.v
--- a/cores/bbc/rtl/m6522.vhd
+++ b/cores/bbc/rtl/m6522.vhd