github.com/mist-devel.mist-board
1
0
Fork 0
mirror of https://github.com/mist-devel/mist-board.git synced 2026-02-06 16:14:42 +00:00
Code Issues Releases Wiki Activity

[Archie] Adjust SDRAM simulation

Browse Source
This commit is contained in:
Gyorgy Szombathelyi
2019-03-07 13:21:27 +01:00
parent dd445a01ca
commit d774f5356b
4 changed files with 43 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
cores/archie/bench/sdram/sdram.cpp
View File

@@ -17,7 +17,7 @@ vluint64_t main_time = 0; // Current simulation time
// This is a 64-bit integer to reduce wrap over issues and
// allow modulus. You can also use a double, if you wish.
double sc_time_stamp () { // Called by $time in Verilog
return main_time; // converts to double, to match
return (double)main_time*3.8; // converts to double, to match
// what SystemC does
}
@@ -30,10 +30,10 @@ void tick()
uut->RESET = 0; // Deassert reset
}
uut->DRAM_CLK = uut->DRAM_CLK ? 0 : 1; // Toggle clock
uut->DRAM_CLK = uut->DRAM_CLK ? 0 : 1; // Toggle SDRAM clock
DRAM_CLK.Update(uut->DRAM_CLK);
if ((main_time % 4) == 0)
if ((main_time % 3) == 0)
{
uut->wb_clk = uut->wb_clk ? 0 : 1; // Toggle clock
wb_clk.Update(uut->wb_clk);
@@ -43,7 +43,7 @@ void tick()
if (tfp != NULL)
{
tfp->dump(main_time);
tfp->dump(main_time*3.8);
}
main_time++; // Time passes...

2
cores/archie/bench/sdram/sdram.v
View File

@@ -54,7 +54,7 @@ sdram_top uut(
.wb_clk ( wb_clk ),
.wb_stb ( wb_stb ),
.wb_cyc ( wb_cyc ),
.wb_we ( wb_wr ),
.wb_we ( wb_we ),
.wb_ack ( wb_ack ),
.wb_sel ( wb_sel ),
.wb_adr ( wb_adr ),

20
cores/archie/bench/support/mt48lc16m16a2.v
View File

@@ -159,7 +159,7 @@ module mt48lc16m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
`define A_REF 5
`define BST 6
`define LMR 7
/*
// Timing Parameters for -7E PC133 CL2
parameter tAC = 5.4;
parameter tHZ = 5.4;
@@ -173,6 +173,20 @@ module mt48lc16m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
parameter tRRD = 14.0;
parameter tWRa = 7.0; // A2 Version - Auto precharge mode (1 Clk + 7 ns)
parameter tWRm = 14.0; // A2 Version - Manual precharge mode (14 ns)
*/
// Timing Parameters for -75 PC133 CL3
parameter tAC = 5.4;
parameter tHZ = 5.4;
parameter tOH = 3.0;
parameter tMRD = 2.0; // 2 Clk Cycles
parameter tRAS = 37.0;
parameter tRC = 60.0;
parameter tRCD = 20.0;
parameter tRFC = 66.0;
parameter tRP = 20.0;
parameter tRRD = 15.0;
parameter tWRa = 7.5; // A2 Version - Auto precharge mode (1 Clk + 7.5 ns)
parameter tWRm = 15.0; // A2 Version - Manual precharge mode (15 ns)
// Timing Check variable
time MRD_chk;
@@ -425,7 +439,7 @@ end
// Record variables
Act_b0 = 1'b1;
//$display ("%m : Bank 0 activated at time %t", $time);
$display ("%m : Bank 0 activated at time %t", $time);
Pc_b0 = 1'b0;
B0_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk0 = $time;
@@ -655,7 +669,7 @@ end
(Ba == 2'b01) && ($time - RCD_chk1 < tRCD) ||
(Ba == 2'b10) && ($time - RCD_chk2 < tRCD) ||
(Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin
$display("%m : at time %t ERROR: tRCD violation during Read", $time);
$display("%m : at time %t ERROR: tRCD violation during Read %t %t %t %t", $time, $time-RCD_chk0, $time-RCD_chk1, $time-RCD_chk2, $time-RCD_chk3 );
end
// CAS Latency pipeline

25
cores/archie/rtl/sdram/sdram_top.v
View File

@@ -88,7 +88,7 @@ end
localparam CYCLE_RAS_START = 4'd1;
localparam CYCLE_RFSH_START = CYCLE_RAS_START;
localparam CYCLE_CAS0 = CYCLE_RFSH_START + RASCAS_DELAY;
localparam CYCLE_CAS0 = CYCLE_RFSH_START + RASCAS_DELAY;
localparam CYCLE_CAS1 = CYCLE_CAS0 + 4'd1;
localparam CYCLE_CAS2 = CYCLE_CAS1 + 4'd1;
localparam CYCLE_CAS3 = CYCLE_CAS2 + 4'd1;
@@ -102,16 +102,25 @@ localparam CYCLE_RFSH_END = CYCLE_RFSH_START + RFC_DELAY;
localparam RAM_CLK = 128000000;
localparam REFRESH_PERIOD = (RAM_CLK / (16 * 8192)) - CYCLE_END;
`ifdef VERILATOR
reg [15:0] sd_q;
assign sd_dq = (sd_writing && (sd_cycle == CYCLE_CAS1 || sd_cycle == CYCLE_CAS2)) ? sd_q : 16'bZZZZZZZZZZZZZZZZ;
`endif
always @(posedge sd_clk) begin
`ifndef VERILATOR
sd_dq <= 16'bZZZZZZZZZZZZZZZZ;
`endif
sd_cmd <= CMD_NOP;
if (sd_rst) begin
t <= 4'd0;
reset <= 5'h1f;
sd_addr <= 13'd0;
sd_ready <= 0;
end else begin
sd_dq <= 16'bZZZZZZZZZZZZZZZZ;
if (!sd_ready) begin
t <= t + 4'd1;
@@ -145,7 +154,6 @@ always @(posedge sd_clk) begin
// bring the wishbone bus signal into the ram clock domain.
sd_we <= wb_we;
sd_cmd <= CMD_INHIBIT;
if (wb_stb & wb_cyc & ~wb_ack) begin
sd_stb <= wb_stb;
sd_cyc <= wb_cyc;
@@ -179,7 +187,6 @@ always @(posedge sd_clk) begin
// while the cycle is active count.
sd_cycle <= sd_cycle + 3'd1;
//sd_cmd <= CMD_NOP;
case (sd_cycle)
CYCLE_RAS_START: begin
sd_cmd <= CMD_ACTIVE;
@@ -203,7 +210,11 @@ always @(posedge sd_clk) begin
sd_cmd <= CMD_READ;
end else if (sd_writing) begin
sd_cmd <= CMD_WRITE;
sd_dq <= wb_dat_i[15:0];
`ifdef VERILATOR
sd_q <= wb_dat_i[15:0];
`else
sd_dq <= wb_dat_i[15:0];
`endif
end
end
@@ -219,7 +230,11 @@ always @(posedge sd_clk) begin
end
end else if (sd_writing) begin
sd_cmd <= CMD_WRITE;
`ifdef VERILATOR
sd_q <= wb_dat_i[31:16];
`else
sd_dq <= wb_dat_i[31:16];
`endif
sd_done <= 1'b1;
end
end