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Merge pull request #107 from gyurco/c16

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C16 some SDRAM + HSync
This commit is contained in:
gyurco
2019-05-02 21:33:07 +02:00
committed by GitHub
parent 9b5ed8cbc4 86ae4c52df
commit dc64adaef4
2 changed files with 15 additions and 12 deletions
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21
cores/c16/c16_mist.v
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@@ -143,9 +143,9 @@ wire mux_sdram_oe = clkref ? c16_sdram_oe : tap_sdram_oe;
wire [15:0] sdram_din = { mux_sdram_data, mux_sdram_data };
wire [14:0] sdram_addr_64k = mux_sdram_addr[15:1]; // 64k mapping
wire [14:0] sdram_addr_16k = { 1'b0, mux_sdram_addr[13:7], 1'b0, mux_sdram_addr[6:1] }; // 16k
wire [24:0] sdram_addr = (clkref | (~clkref & prg_download)) ?
wire [23:0] sdram_addr = (clkref | (~clkref & prg_download)) ?
{ 10'h00, memory_16k?sdram_addr_16k:sdram_addr_64k } :
(tap_sdram_oe ? tap_play_addr : ioctl_sdram_addr);
(tap_sdram_oe ? tap_play_addr[24:1] : ioctl_sdram_addr[24:1]);
wire sdram_wr = mux_sdram_wr;
wire sdram_oe = mux_sdram_oe;
@@ -171,12 +171,15 @@ end
// latch/demultiplex dram address
reg [7:0] c16_a_low;
always @(negedge c16_ras)
c16_a_low <= c16_a;
reg [7:0] c16_a_hi;
always @(negedge c16_cas)
c16_a_hi <= c16_a;
always @(posedge clk28) begin
reg c16_rasD, c16_casD;
c16_rasD <= c16_ras;
c16_casD <= c16_cas;
if (c16_rasD & ~c16_ras) c16_a_low <= c16_a;
if (c16_casD & ~c16_cas) c16_a_hi <= c16_a;
end
sdram sdram (
// interface to the MT48LC16M16 chip
@@ -493,7 +496,7 @@ c1530 c1530
wire [5:0] osd_r_in = tv15khz?{c16_r, 2'b00}:video_r;
wire [5:0] osd_g_in = tv15khz?{c16_g, 2'b00}:video_g;
wire [5:0] osd_b_in = tv15khz?{c16_b, 2'b00}:video_b;
wire osd_hs_in = tv15khz?!c16_hs:video_hs;
wire osd_hs_in = tv15khz?c16_hs:video_hs;
wire osd_vs_in = tv15khz?!c16_vs:video_vs;
wire osd_clk = tv15khz?clk7:clk14;
@@ -556,7 +559,7 @@ scandoubler scandoubler (
.scanlines ( scanlines?2'b10:2'b00 ),
// shifter video interface
.hs_in ( !c16_hs ),
.hs_in ( c16_hs ),
.vs_in ( !c16_vs ),
.r_in ( c16_r ),
.g_in ( c16_g ),

6
cores/c16/sdram.v
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@@ -39,7 +39,7 @@ module sdram (
input [15:0] din, // data input from chipset/cpu
output reg [15:0] dout, // data output to chipset/cpu
input [24:0] addr, // 25 bit word address
input [23:0] addr, // 24 bit word address
input [1:0] ds, // data strobe for hi/low byte
input oe, // cpu/chipset requests read
input we // cpu/chipset requests write
@@ -129,11 +129,11 @@ always @(posedge clk) begin
end
end else begin
if(q <= STATE_CMD_START) begin
sd_addr <= addr[20:8];
sd_addr <= { addr[20:15], addr[6:0] };
sd_ba <= addr[22:21];
sd_dqm <= { !ds[1], !ds[0] };
end else
sd_addr <= { 4'b0010, addr[23], addr[7:0]};
sd_addr <= { 4'b0010, addr[23], addr[14:7]};
if(q == STATE_IDLE) begin
if(we || oe) sd_cmd <= CMD_ACTIVE;