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Code Issues Releases Wiki Activity

C64: [C1541] use programmed value for speedzone

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This commit is contained in:
Gyorgy Szombathelyi
2020-04-13 21:14:29 +02:00
parent 82dfa12c09
commit e20b110731
2 changed files with 7 additions and 6 deletions
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2
cores/c64/rtl/c1541/c1541_sd.vhd
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@@ -199,7 +199,7 @@ port map
mode => mode, -- read/write
-- stp => stp, -- stepper motor control
mtr => mtr, -- stepper motor on/off
-- freq => freq, -- motor (gcr_bit) frequency
freq => freq, -- motor (gcr_bit) frequency
sync_n => sync_n, -- reading SYNC bytes
byte_n => byte_n, -- byte ready

11
cores/c64/rtl/c1541/gcr_floppy.vhd
View File

@@ -24,7 +24,7 @@ port(
mode : in std_logic; -- read/write
-- stp : in std_logic_vector(1 downto 0); -- stepper motor control
mtr : in std_logic; -- stepper motor on/off
-- freq : in std_logic_vector(1 downto 0); -- motor (gcr_bit) frequency
freq : in std_logic_vector(1 downto 0); -- motor (gcr_bit) frequency
sync_n : out std_logic; -- reading SYNC bytes
byte_n : out std_logic; -- byte ready
@@ -160,10 +160,11 @@ with gcr_nibble_out select
X"E" when "11110",--"01111",
X"F" when others; --"10101",
bit_clk_div <= x"67" when track_num < std_logic_vector(to_unsigned(18,6)) else
x"6F" when track_num < std_logic_vector(to_unsigned(25,6)) else
x"77" when track_num < std_logic_vector(to_unsigned(31,6)) else
x"7F";
with freq select
bit_clk_div <= x"67" when "11",
x"6F" when "10",
x"77" when "01",
x"7F" when others;
process (clk32)
variable bit_clk_cnt : std_logic_vector(7 downto 0) := (others => '0');