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First tests Sega Master System

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harbaum
2014-08-18 20:19:02 +00:00
parent 9217f5b977
commit e53ac44f43
30 changed files with 8905 additions and 0 deletions
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cores/sms/sms_mist.qpf Normal file
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# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
QUARTUS_VERSION = "7.2"
DATE = "17:25:25 January 26, 2008"
# Revisions
PROJECT_REVISION = "sms_mist"

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cores/sms/sms_mist.qsf Normal file
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# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
set_global_assignment -name TOP_LEVEL_ENTITY sms_mist
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:49:11 JANUARY 31, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
# Pin & Location Assignments
# ==========================
# Timing Assignments
# ==================
set_global_assignment -name IGNORE_CLOCK_SETTINGS ON
set_global_assignment -name TPD_REQUIREMENT "5 ns"
set_global_assignment -name TSU_REQUIREMENT "5 ns"
set_global_assignment -name TCO_REQUIREMENT "5 ns"
set_global_assignment -name TH_REQUIREMENT "5 ns"
set_global_assignment -name FMAX_REQUIREMENT "101.58 MHz"
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM ON
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name AUTO_RESOURCE_SHARING OFF
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name FLEX10K_DEVICE_IO_STANDARD LVTTL/LVCMOS
# Assembler Assignments
# =====================
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name ENABLE_DRC_SETTINGS ON
set_global_assignment -name ENABLE_CLOCK_LATENCY ON
set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON
set_global_assignment -name IGNORE_LCELL_BUFFERS ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "FAST FIT"
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS ON
set_global_assignment -name AUTO_PACKED_REGISTERS "MINIMIZE AREA"
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS OFF
set_global_assignment -name IGNORE_CARRY_BUFFERS ON
set_global_assignment -name IGNORE_CASCADE_BUFFERS ON
set_global_assignment -name AUTO_GLOBAL_CLOCK ON
set_global_assignment -name AUTO_RAM_RECOGNITION ON
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION AUTO
set_global_assignment -name STATE_MACHINE_PROCESSING AUTO
set_global_assignment -name FMAX_REQUIREMENT "34 MHz" -section_id clk32
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES "DONT CARE"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27[0]
set_location_assignment PIN_55 -to CLOCK_27[1]
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_46 -to UART_TX
set_location_assignment PIN_31 -to UART_RX
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_90 -to SPI_SS4
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SDRAM_CLK
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SPI_SCK
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name VERILOG_FILE src/data_io.v
set_global_assignment -name VERILOG_FILE src/osd.v
set_global_assignment -name VERILOG_FILE src/user_io.v
set_global_assignment -name VHDL_FILE src/sprom.vhd
set_global_assignment -name VHDL_FILE src/spram.vhd
set_global_assignment -name VERILOG_FILE src/sdram.v
set_global_assignment -name VHDL_FILE src/dpram.vhd
set_global_assignment -name VHDL_FILE t80/T80se.vhd
set_global_assignment -name VHDL_FILE src/vga_video.vhd
set_global_assignment -name VHDL_FILE src/vdp_sprites.vhd
set_global_assignment -name VHDL_FILE src/vdp_sprite_shifter.vhd
set_global_assignment -name VHDL_FILE src/vdp_main.vhd
set_global_assignment -name VHDL_FILE src/vdp_cram.vhd
set_global_assignment -name VHDL_FILE src/vdp_background.vhd
set_global_assignment -name VHDL_FILE src/vdp.vhd
set_global_assignment -name VHDL_FILE src/system.vhd
set_global_assignment -name VHDL_FILE src/sms_mist.vhd
set_global_assignment -name VHDL_FILE src/psg_tone.vhd
set_global_assignment -name VHDL_FILE src/psg_noise.vhd
set_global_assignment -name VHDL_FILE src/psg.vhd
set_global_assignment -name VHDL_FILE src/io.vhd
set_global_assignment -name VHDL_FILE src/dac.vhd
set_global_assignment -name VHDL_FILE t80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE t80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE t80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE t80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE t80/T80.vhd
set_global_assignment -name QIP_FILE pll.qip
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "pll:clock_inst|altpll:altpll_component|clk[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to SDRAM_A[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to SDRAM_A[10] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to SDRAM_A[11] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to SDRAM_A[12] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to SDRAM_A[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to SDRAM_A[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to SDRAM_A[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to SDRAM_A[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to SDRAM_A[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to SDRAM_A[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to SDRAM_A[7] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to SDRAM_A[8] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to SDRAM_A[9] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to SDRAM_BA[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to SDRAM_BA[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to SDRAM_DQMH -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to SDRAM_DQML -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to SDRAM_nCAS -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to SDRAM_nCS -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to SDRAM_nRAS -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to SDRAM_nWE -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to clk_cpu -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "pll:clock_inst|locked" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "sdram:sdram_inst|addr[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "sdram:sdram_inst|addr[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "sdram:sdram_inst|addr[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "sdram:sdram_inst|addr[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "sdram:sdram_inst|addr[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "sdram:sdram_inst|addr[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "sdram:sdram_inst|addr[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "sdram:sdram_inst|addr[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "sdram:sdram_inst|addr[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "sdram:sdram_inst|addr[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "sdram:sdram_inst|addr[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "sdram:sdram_inst|addr[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "sdram:sdram_inst|addr[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "sdram:sdram_inst|addr[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "sdram:sdram_inst|addr[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "sdram:sdram_inst|addr[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "sdram:sdram_inst|addr[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "sdram:sdram_inst|addr[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "sdram:sdram_inst|addr[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "sdram:sdram_inst|addr[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "sdram:sdram_inst|addr[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "sdram:sdram_inst|addr[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "sdram:sdram_inst|addr[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "sdram:sdram_inst|addr[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "sdram:sdram_inst|addr[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "sdram:sdram_inst|din[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "sdram:sdram_inst|din[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "sdram:sdram_inst|din[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "sdram:sdram_inst|din[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "sdram:sdram_inst|din[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "sdram:sdram_inst|din[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "sdram:sdram_inst|din[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "sdram:sdram_inst|din[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "sdram:sdram_inst|dout[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "sdram:sdram_inst|dout[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "sdram:sdram_inst|dout[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "sdram:sdram_inst|dout[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "sdram:sdram_inst|dout[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "sdram:sdram_inst|dout[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "sdram:sdram_inst|dout[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "sdram:sdram_inst|dout[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "sdram:sdram_inst|oe" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "sdram:sdram_inst|q[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "sdram:sdram_inst|q[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "sdram:sdram_inst|q[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "sdram:sdram_inst|reset[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "sdram:sdram_inst|reset[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "sdram:sdram_inst|reset[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "sdram:sdram_inst|reset[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "sdram:sdram_inst|reset[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "system:system_inst|T80se:z80_inst|A[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "system:system_inst|T80se:z80_inst|A[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "system:system_inst|T80se:z80_inst|A[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "system:system_inst|T80se:z80_inst|A[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "system:system_inst|T80se:z80_inst|A[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "system:system_inst|T80se:z80_inst|A[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "system:system_inst|T80se:z80_inst|A[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "system:system_inst|T80se:z80_inst|A[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "system:system_inst|T80se:z80_inst|A[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "system:system_inst|T80se:z80_inst|A[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "system:system_inst|T80se:z80_inst|A[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "system:system_inst|T80se:z80_inst|A[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "system:system_inst|T80se:z80_inst|A[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "system:system_inst|T80se:z80_inst|A[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "system:system_inst|T80se:z80_inst|A[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "system:system_inst|T80se:z80_inst|A[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "system:system_inst|T80se:z80_inst|CLKEN" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "system:system_inst|T80se:z80_inst|CLK_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "system:system_inst|T80se:z80_inst|DI[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "system:system_inst|T80se:z80_inst|DI[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "system:system_inst|T80se:z80_inst|DI[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "system:system_inst|T80se:z80_inst|DI[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "system:system_inst|T80se:z80_inst|DI[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "system:system_inst|T80se:z80_inst|DI[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "system:system_inst|T80se:z80_inst|DI[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "system:system_inst|T80se:z80_inst|DI[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "system:system_inst|T80se:z80_inst|DO[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "system:system_inst|T80se:z80_inst|DO[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "system:system_inst|T80se:z80_inst|DO[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "system:system_inst|T80se:z80_inst|DO[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "system:system_inst|T80se:z80_inst|DO[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "system:system_inst|T80se:z80_inst|DO[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "system:system_inst|T80se:z80_inst|DO[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "system:system_inst|T80se:z80_inst|DO[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "system:system_inst|T80se:z80_inst|IORQ_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "system:system_inst|T80se:z80_inst|MREQ_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "system:system_inst|T80se:z80_inst|RD_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "system:system_inst|T80se:z80_inst|RESET_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "system:system_inst|T80se:z80_inst|WR_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "system:system_inst|bootloader" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "system:system_inst|ctl_WR_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "system:system_inst|io_RD_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "system:system_inst|io_WR_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "system:system_inst|psg_WR_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "system:system_inst|ram_WR_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "system:system_inst|reset" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "system:system_inst|sprom:boot_rom_inst|q[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "system:system_inst|sprom:boot_rom_inst|q[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "system:system_inst|sprom:boot_rom_inst|q[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "system:system_inst|sprom:boot_rom_inst|q[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "system:system_inst|sprom:boot_rom_inst|q[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "system:system_inst|sprom:boot_rom_inst|q[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "system:system_inst|sprom:boot_rom_inst|q[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "system:system_inst|sprom:boot_rom_inst|q[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "system:system_inst|vdp_RD_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "system:system_inst|vdp_WR_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to SDRAM_A[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to SDRAM_A[10] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to SDRAM_A[11] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to SDRAM_A[12] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to SDRAM_A[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to SDRAM_A[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to SDRAM_A[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to SDRAM_A[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to SDRAM_A[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to SDRAM_A[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to SDRAM_A[7] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to SDRAM_A[8] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to SDRAM_A[9] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to SDRAM_BA[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to SDRAM_BA[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to SDRAM_DQMH -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to SDRAM_DQML -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to SDRAM_nCAS -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to SDRAM_nCS -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to SDRAM_nRAS -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to SDRAM_nWE -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to clk_cpu -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "pll:clock_inst|locked" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "sdram:sdram_inst|addr[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "sdram:sdram_inst|addr[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "sdram:sdram_inst|addr[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "sdram:sdram_inst|addr[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "sdram:sdram_inst|addr[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "sdram:sdram_inst|addr[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "sdram:sdram_inst|addr[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "sdram:sdram_inst|addr[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "sdram:sdram_inst|addr[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "sdram:sdram_inst|addr[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "sdram:sdram_inst|addr[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "sdram:sdram_inst|addr[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "sdram:sdram_inst|addr[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "sdram:sdram_inst|addr[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "sdram:sdram_inst|addr[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "sdram:sdram_inst|addr[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "sdram:sdram_inst|addr[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "sdram:sdram_inst|addr[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "sdram:sdram_inst|addr[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "sdram:sdram_inst|addr[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "sdram:sdram_inst|addr[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "sdram:sdram_inst|addr[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "sdram:sdram_inst|addr[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "sdram:sdram_inst|addr[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "sdram:sdram_inst|addr[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "sdram:sdram_inst|din[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "sdram:sdram_inst|din[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "sdram:sdram_inst|din[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "sdram:sdram_inst|din[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "sdram:sdram_inst|din[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "sdram:sdram_inst|din[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "sdram:sdram_inst|din[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "sdram:sdram_inst|din[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "sdram:sdram_inst|dout[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "sdram:sdram_inst|dout[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "sdram:sdram_inst|dout[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "sdram:sdram_inst|dout[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "sdram:sdram_inst|dout[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "sdram:sdram_inst|dout[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "sdram:sdram_inst|dout[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "sdram:sdram_inst|dout[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "sdram:sdram_inst|oe" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "sdram:sdram_inst|q[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "sdram:sdram_inst|q[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "sdram:sdram_inst|q[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "sdram:sdram_inst|reset[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "sdram:sdram_inst|reset[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "sdram:sdram_inst|reset[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "sdram:sdram_inst|reset[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "sdram:sdram_inst|reset[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "system:system_inst|T80se:z80_inst|A[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "system:system_inst|T80se:z80_inst|A[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "system:system_inst|T80se:z80_inst|A[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "system:system_inst|T80se:z80_inst|A[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "system:system_inst|T80se:z80_inst|A[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "system:system_inst|T80se:z80_inst|A[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "system:system_inst|T80se:z80_inst|A[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "system:system_inst|T80se:z80_inst|A[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "system:system_inst|T80se:z80_inst|A[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "system:system_inst|T80se:z80_inst|A[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "system:system_inst|T80se:z80_inst|A[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "system:system_inst|T80se:z80_inst|A[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "system:system_inst|T80se:z80_inst|A[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "system:system_inst|T80se:z80_inst|A[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "system:system_inst|T80se:z80_inst|A[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "system:system_inst|T80se:z80_inst|A[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "system:system_inst|T80se:z80_inst|CLKEN" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "system:system_inst|T80se:z80_inst|CLK_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "system:system_inst|T80se:z80_inst|DI[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "system:system_inst|T80se:z80_inst|DI[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "system:system_inst|T80se:z80_inst|DI[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "system:system_inst|T80se:z80_inst|DI[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "system:system_inst|T80se:z80_inst|DI[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "system:system_inst|T80se:z80_inst|DI[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "system:system_inst|T80se:z80_inst|DI[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "system:system_inst|T80se:z80_inst|DI[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "system:system_inst|T80se:z80_inst|DO[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "system:system_inst|T80se:z80_inst|DO[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "system:system_inst|T80se:z80_inst|DO[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "system:system_inst|T80se:z80_inst|DO[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "system:system_inst|T80se:z80_inst|DO[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "system:system_inst|T80se:z80_inst|DO[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "system:system_inst|T80se:z80_inst|DO[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "system:system_inst|T80se:z80_inst|DO[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "system:system_inst|T80se:z80_inst|IORQ_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "system:system_inst|T80se:z80_inst|MREQ_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "system:system_inst|T80se:z80_inst|RD_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "system:system_inst|T80se:z80_inst|RESET_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "system:system_inst|T80se:z80_inst|WR_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "system:system_inst|bootloader" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "system:system_inst|ctl_WR_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "system:system_inst|io_RD_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "system:system_inst|io_WR_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "system:system_inst|psg_WR_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "system:system_inst|ram_WR_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "system:system_inst|reset" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "system:system_inst|sprom:boot_rom_inst|q[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "system:system_inst|sprom:boot_rom_inst|q[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "system:system_inst|sprom:boot_rom_inst|q[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "system:system_inst|sprom:boot_rom_inst|q[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "system:system_inst|sprom:boot_rom_inst|q[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "system:system_inst|sprom:boot_rom_inst|q[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "system:system_inst|sprom:boot_rom_inst|q[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "system:system_inst|sprom:boot_rom_inst|q[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "system:system_inst|vdp_RD_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "system:system_inst|vdp_WR_n" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=129" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=129" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=410" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=512" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=63756" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=55445" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=512" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dac is
Port (
clk : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (5 downto 0);
output: out STD_LOGIC);
end dac;
architecture rtl of dac is
signal delta_adder: unsigned(7 downto 0);
signal sigma_adder: unsigned(7 downto 0);
signal sigma_latch: unsigned(7 downto 0) := "01000000";
signal delta_b : unsigned(7 downto 0);
begin
delta_b <= sigma_latch(7)&sigma_latch(7)&"000000";
delta_adder <= unsigned(input) + delta_b;
sigma_adder <= delta_adder + sigma_latch;
process (clk, delta_adder)
begin
if rising_edge(clk) then
sigma_latch <= sigma_adder;
output <= sigma_adder(7);
end if;
end process;
end rtl;

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//
// data_io.v
//
// io controller writable ram for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module data_io (
// io controller spi interface
input sck,
input ss,
input sdi,
output downloading, // signal indicating an active download
output [24:0] size, // number of bytes in input buffer
// external ram interface
input clk,
output reg wr,
output reg [24:0] a,
output [7:0] d
);
assign d = data;
parameter START_ADDR = 25'h0;
assign size = addr;
// *********************************************************************************
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg [6:0] sbuf;
reg [7:0] cmd /* synthesis noprune */;
reg [7:0] data /* synthesis noprune */;
reg [4:0] cnt /* synthesis noprune */;
reg [24:0] addr /* synthesis noprune */;
reg rclk /* synthesis noprune */;
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
assign downloading = downloading_reg;
reg downloading_reg = 1'b0;
// data_io has its own SPI interface to the io controller
always@(posedge sck, posedge ss) begin
if(ss == 1'b1)
cnt <= 5'd0;
else begin
rclk <= 1'b0;
// don't shift in last bit. It is evaluated directly
// when writing to ram
if(cnt != 15)
sbuf <= { sbuf[5:0], sdi};
// increase target address after write
if(rclk)
addr <= addr + 25'd1;
// count 0-7 8-15 8-15 ...
if(cnt < 15) cnt <= cnt + 4'd1;
else cnt <= 4'd8;
// finished command byte
if(cnt == 7)
cmd <= {sbuf, sdi};
// prepare/end transmission
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(sdi) begin
addr <= START_ADDR;
downloading_reg <= 1'b1;
end else
downloading_reg <= 1'b0;
end
// command 0x54: UIO_FILE_TX
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
data <= {sbuf, sdi};
rclk <= 1'b1;
a <= addr;
end
end
end
reg rclkD, rclkD2;
always@(posedge clk) begin
// bring rclk from spi clock domain into core clock domain
rclkD <= rclk;
rclkD2 <= rclkD;
wr <= 1'b0;
if(rclkD && !rclkD2)
wr <= 1'b1;
end
endmodule

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED";
outdata_reg_b : string := "UNREGISTERED"
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END dpram;
ARCHITECTURE SYN OF dpram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(width_a-1 DOWNTO 0);
q_b <= sub_wire1(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
numwords_b => 2**widthad_a,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => outdata_reg_a,
outdata_reg_b => outdata_reg_a,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => widthad_a,
widthad_b => widthad_a,
width_a => width_a,
width_b => width_a,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity io is
Port(
clk: in STD_LOGIC;
WR_n: in STD_LOGIC;
RD_n: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (7 downto 0);
D_in: in STD_LOGIC_VECTOR (7 downto 0);
D_out: out STD_LOGIC_VECTOR (7 downto 0);
J1_up: in STD_LOGIC;
J1_down: in STD_LOGIC;
J1_left: in STD_LOGIC;
J1_right:in STD_LOGIC;
J1_tl: in STD_LOGIC;
J1_tr: in STD_LOGIC;
J2_up: in STD_LOGIC;
J2_down: in STD_LOGIC;
J2_left: in STD_LOGIC;
J2_right:in STD_LOGIC;
J2_tl: in STD_LOGIC;
J2_tr: in STD_LOGIC;
RESET: in STD_LOGIC);
end io;
architecture rtl of io is
signal ctrl: std_logic_vector(7 downto 0) := (others=>'1');
begin
process (clk)
begin
if rising_edge(clk) then
if WR_n='0' then
ctrl <= D_in;
end if;
end if;
end process;
-- J1_tr <= ctrl(4) when ctrl(0)='0' else 'Z';
-- J2_tr <= ctrl(6) when ctrl(2)='0' else 'Z';
process (clk)
begin
if rising_edge(clk) then
if RD_n='0' then
if A(0)='0' then
D_out(7) <= J2_down;
D_out(6) <= J2_up;
-- 5=j1_tr
if ctrl(0)='0' then
D_out(5) <= ctrl(4);
else
D_out(5) <= J1_tr;
end if;
D_out(4) <= J1_tl;
D_out(3) <= J1_right;
D_out(2) <= J1_left;
D_out(1) <= J1_down;
D_out(0) <= J1_up;
else
-- 7=j2_th
if ctrl(3)='0' then
D_out(7) <= ctrl(7);
else
D_out(7) <= '1';
end if;
-- 6=j1_th
if ctrl(1)='0' then
D_out(6) <= ctrl(5);
else
D_out(6) <= '1';
end if;
D_out(5) <= '1';
D_out(4) <= '1';
-- 4=j2_tr
if ctrl(2)='0' then
D_out(3) <= ctrl(6);
else
D_out(3) <= J2_tr;
end if;
D_out(2) <= J2_tl;
D_out(1) <= J2_right;
D_out(0) <= J2_left;
end if;
end if;
end if;
end process;
end rtl;

1382
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cores/sms/src/osd.v Normal file
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// A simple OSD implementation. Can be hooked up between a cores
// VGA output and the physical VGA pins
module osd (
// OSDs pixel clock, should be synchronous to cores pixel clock to
// avoid jitter.
input pclk,
// SPI interface
input sck,
input ss,
input sdi,
// VGA signals coming from core
input [5:0] red_in,
input [5:0] green_in,
input [5:0] blue_in,
input hs_in,
input vs_in,
// VGA signals going to video connector
output [5:0] red_out,
output [5:0] green_out,
output [5:0] blue_out,
output hs_out,
output vs_out
);
parameter OSD_X_OFFSET = 10'd0;
parameter OSD_Y_OFFSET = 10'd0;
parameter OSD_COLOR = 3'd1;
localparam OSD_WIDTH = 10'd256;
localparam OSD_HEIGHT = 10'd128;
// *********************************************************************************
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg [7:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [10:0] bcnt;
reg osd_enable;
reg [7:0] osd_buffer [2047:0]; // the OSD buffer itself
// the OSD has its own SPI interface to the io controller
always@(posedge sck, posedge ss) begin
if(ss == 1'b1) begin
cnt <= 5'd0;
bcnt <= 11'd0;
end else begin
sbuf <= { sbuf[6:0], sdi};
// 0:7 is command, rest payload
if(cnt < 15)
cnt <= cnt + 4'd1;
else
cnt <= 4'd8;
if(cnt == 7) begin
cmd <= {sbuf[6:0], sdi};
// lower three command bits are line address
bcnt <= { sbuf[1:0], sdi, 8'h00};
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(sbuf[6:3] == 4'b0100)
osd_enable <= sdi;
end
// command 0x20: OSDCMDWRITE
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
osd_buffer[bcnt] <= {sbuf[6:0], sdi};
bcnt <= bcnt + 11'd1;
end
end
end
// *********************************************************************************
// video timing and sync polarity anaylsis
// *********************************************************************************
// horizontal counter
reg [9:0] h_cnt;
reg hsD, hsD2;
reg [9:0] hs_low, hs_high;
wire hs_pol = hs_high < hs_low;
wire [9:0] h_dsp_width = hs_pol?hs_low:hs_high;
wire [9:0] h_dsp_ctr = { 1'b0, h_dsp_width[9:1] };
always @(posedge pclk) begin
// bring hsync into local clock domain
hsD <= hs_in;
hsD2 <= hsD;
// falling edge of hs_in
if(!hsD && hsD2) begin
h_cnt <= 10'd0;
hs_high <= h_cnt;
end
// rising edge of hs_in
else if(hsD && !hsD2) begin
h_cnt <= 10'd0;
hs_low <= h_cnt;
end
else
h_cnt <= h_cnt + 10'd1;
end
// vertical counter
reg [9:0] v_cnt;
reg vsD, vsD2;
reg [9:0] vs_low, vs_high;
wire vs_pol = vs_high < vs_low;
wire [9:0] v_dsp_width = vs_pol?vs_low:vs_high;
wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_width[9:1] };
always @(posedge hsD) begin
// bring vsync into local clock domain
vsD <= vs_in;
vsD2 <= vsD;
// falling edge of vs_in
if(!vsD && vsD2) begin
v_cnt <= 10'd0;
vs_high <= v_cnt;
end
// rising edge of vs_in
else if(vsD && !vsD2) begin
v_cnt <= 10'd0;
vs_low <= v_cnt;
end
else
v_cnt <= v_cnt + 10'd1;
end
// area in which OSD is being displayed
wire [9:0] h_osd_start = h_dsp_ctr + OSD_X_OFFSET - (OSD_WIDTH >> 1);
wire [9:0] h_osd_end = h_dsp_ctr + OSD_X_OFFSET + (OSD_WIDTH >> 1) - 1;
wire [9:0] v_osd_start = v_dsp_ctr + OSD_Y_OFFSET - (OSD_HEIGHT >> 1);
wire [9:0] v_osd_end = v_dsp_ctr + OSD_Y_OFFSET + (OSD_HEIGHT >> 1) - 1;
reg h_osd_active, v_osd_active;
always @(posedge pclk) begin
if(hs_in != hs_pol) begin
if(h_cnt == h_osd_start) h_osd_active <= 1'b1;
if(h_cnt == h_osd_end) h_osd_active <= 1'b0;
end
if(vs_in != vs_pol) begin
if(v_cnt == v_osd_start) v_osd_active <= 1'b1;
if(v_cnt == v_osd_end) v_osd_active <= 1'b0;
end
end
wire osd_de = osd_enable && h_osd_active && v_osd_active;
wire [7:0] osd_hcnt = h_cnt - h_osd_start + 7'd1; // one pixel offset for osd_byte register
wire [6:0] osd_vcnt = v_cnt - v_osd_start;
wire osd_pixel = osd_byte[osd_vcnt[3:1]];
reg [7:0] osd_byte;
always @(posedge pclk)
osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt}];
wire [2:0] osd_color = OSD_COLOR;
assign red_out = !osd_de?red_in: {osd_pixel, osd_pixel, osd_color[2], red_in[5:3] };
assign green_out = !osd_de?green_in:{osd_pixel, osd_pixel, osd_color[1], green_in[5:3]};
assign blue_out = !osd_de?blue_in: {osd_pixel, osd_pixel, osd_color[0], blue_in[5:3] };
assign hs_out = hs_in;
assign vs_out = vs_in;
endmodule

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity psg is
port (clk : in STD_LOGIC;
WR_n : in STD_LOGIC;
D_in : in STD_LOGIC_VECTOR (7 downto 0);
output: out STD_LOGIC);
end entity;
architecture rtl of psg is
signal clk_divide : unsigned(5 downto 0) := "000000";
signal clk32 : std_logic;
signal regn : std_logic_vector(2 downto 0);
signal tone0 : std_logic_vector(9 downto 0):="0000100000";
signal tone1 : std_logic_vector(9 downto 0):="0000100000";
signal tone2 : std_logic_vector(9 downto 0):="0000100000";
signal ctrl3 : std_logic_vector(2 downto 0):="100";
signal volume0 : std_logic_vector(3 downto 0):="1111";
signal volume1 : std_logic_vector(3 downto 0):="1111";
signal volume2 : std_logic_vector(3 downto 0):="1111";
signal volume3 : std_logic_vector(3 downto 0):="1111";
signal output0 : std_logic_vector(3 downto 0);
signal output1 : std_logic_vector(3 downto 0);
signal output2 : std_logic_vector(3 downto 0);
signal output3 : std_logic_vector(3 downto 0);
signal outputs : std_logic_vector(5 downto 0);
component psg_tone is
port (clk : in STD_LOGIC;
tone : in STD_LOGIC_VECTOR (9 downto 0);
volume: in STD_LOGIC_VECTOR (3 downto 0);
output: out STD_LOGIC_VECTOR (3 downto 0));
end component;
component psg_noise is
port (clk : in STD_LOGIC;
style : in STD_LOGIC_VECTOR (2 downto 0);
tone : in STD_LOGIC_VECTOR (9 downto 0);
volume: in STD_LOGIC_VECTOR (3 downto 0);
output: out STD_LOGIC_VECTOR (3 downto 0));
end component;
component dac is
port (clk : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (5 downto 0);
output: out STD_LOGIC);
end component;
begin
t0: psg_tone
port map (
clk => clk32,
tone => tone0,
volume => volume0,
output => output0);
t1: psg_tone
port map (
clk => clk32,
tone => tone1,
volume => volume1,
output => output1);
t2: psg_tone
port map (
clk => clk32,
tone => tone2,
volume => volume2,
output => output2);
t3: psg_noise
port map(
clk => clk32,
style => ctrl3,
tone => tone2,
volume => volume3,
output => output3);
inst_dac: dac
port map (
clk => clk,
input => outputs,
output => output );
process (clk)
begin
if rising_edge(clk) then
clk_divide <= clk_divide+1;
end if;
end process;
clk32 <= std_logic(clk_divide(5));
process (clk, WR_n)
begin
if rising_edge(clk) and WR_n='0' then
if D_in(7)='1' then
case D_in(6 downto 4) is
when "000" => tone0(3 downto 0) <= D_in(3 downto 0);
when "010" => tone1(3 downto 0) <= D_in(3 downto 0);
when "100" => tone2(3 downto 0) <= D_in(3 downto 0);
when "110" => ctrl3 <= D_in(2 downto 0);
when "001" => volume0 <= D_in(3 downto 0);
when "011" => volume1 <= D_in(3 downto 0);
when "101" => volume2 <= D_in(3 downto 0);
when "111" => volume3 <= D_in(3 downto 0);
when others =>
end case;
regn <= D_in(6 downto 4);
else
case regn is
when "000" => tone0(9 downto 4) <= D_in(5 downto 0);
when "010" => tone1(9 downto 4) <= D_in(5 downto 0);
when "100" => tone2(9 downto 4) <= D_in(5 downto 0);
when "110" =>
when "001" => volume0 <= D_in(3 downto 0);
when "011" => volume1 <= D_in(3 downto 0);
when "101" => volume2 <= D_in(3 downto 0);
when "111" => volume3 <= D_in(3 downto 0);
when others =>
end case;
end if;
end if;
end process;
outputs <= std_logic_vector(
unsigned("00"&output0)
+ unsigned("00"&output1)
+ unsigned("00"&output2)
+ unsigned("00"&output3)
);
end rtl;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity psg_noise is
port (
clk : in STD_LOGIC;
style : in STD_LOGIC_VECTOR (2 downto 0);
tone : in STD_LOGIC_VECTOR (9 downto 0);
volume : in STD_LOGIC_VECTOR (3 downto 0);
output : out STD_LOGIC_VECTOR (3 downto 0));
end psg_noise;
architecture rtl of psg_noise is
signal counter : unsigned(9 downto 0);
signal v : std_logic;
signal shift : std_logic_vector(15 downto 0) := "1000000000000000";
begin
process (clk, tone)
begin
if rising_edge(clk) then
if counter="000000001" then
v <= not v;
case style(1 downto 0) is
when "00" => counter <= "0000010000";
when "01" => counter <= "0000100000";
when "10" => counter <= "0001000000";
when "11" => counter <= unsigned(tone);
when others =>
end case;
else
counter <= counter-1;
end if;
end if;
end process;
process (v)
variable feedback: std_logic;
begin
if rising_edge(v) then
if (style(2)='1') then
feedback := shift(0) xor shift(3);
else
feedback := shift(0);
end if;
shift <= feedback & shift(15 downto 1);
end if;
end process;
output <= (shift(0)&shift(0)&shift(0)&shift(0)) or volume;
end rtl;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity psg_tone is
Port (
clk : in STD_LOGIC;
tone : in STD_LOGIC_VECTOR (9 downto 0);
volume: in STD_LOGIC_VECTOR (3 downto 0);
output: out STD_LOGIC_VECTOR (3 downto 0));
end psg_tone;
architecture rtl of psg_tone is
signal counter : unsigned(9 downto 0) := (0=>'1', others=>'0');
signal v : std_logic := '0';
begin
process (clk, tone)
begin
if rising_edge(clk) then
if counter="000000000" then
v <= not v;
counter <= unsigned(tone);
else
counter <= counter-1;
end if;
end if;
end process;
output <= (v&v&v&v) or volume;
end rtl;

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//
// sdram.v
//
// sdram controller implementation for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sdram (
// interface to the MT48LC16M16 chip
inout [15:0] sd_data, // 16 bit bidirectional data bus
output reg [12:0] sd_addr, // 13 bit multiplexed address bus
output reg [1:0] sd_dqm, // two byte masks
output reg [1:0] sd_ba, // two banks
output sd_cs, // a single chip select
output sd_we, // write enable
output sd_ras, // row address select
output sd_cas, // columns address select
// cpu/chipset interface
input init, // init signal after FPGA config to initialize RAM
input clk, // sdram is accessed at up to 128MHz
input clkref, // reference clock to sync to
input [7:0] din, // data input from chipset/cpu
output [7:0] dout, // data output to chipset/cpu
input [24:0] addr, // 25 bit byte address
input oe, // cpu/chipset requests read
input we // cpu/chipset requests write
);
// falling edge on oe/we/rfsh starts state machine
// no burst configured
localparam RASCAS_DELAY = 3'd3; // tRCD=20ns -> 3 cycles@128MHz
localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd3; // 2/3 allowed
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
// ---------------------------------------------------------------------
localparam STATE_IDLE = 3'd0; // first state in cycle
localparam STATE_CMD_START = 3'd0; // state in which a new command can be started
localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY; // 4 command can be continued
localparam STATE_READ = STATE_CMD_CONT + CAS_LATENCY + 4'd1; //
localparam STATE_LAST = 3'd7; // last state in cycle
assign dout = addr[0]?sd_data[7:0]:sd_data[15:8];
reg [2:0] q /* synthesis noprune */;
always @(posedge clk) begin
// 112Mhz counter synchronous to 14 Mhz clock
// force counter to pass state 5->6 exactly after the rising edge of clkref
// since clkref is two clocks early
if(((q == 7) && ( clkref == 0)) ||
((q == 0) && ( clkref == 1)) ||
((q != 7) && (q != 0)))
q <= q + 3'd1;
end
// ---------------------------------------------------------------------
// --------------------------- startup/reset ---------------------------
// ---------------------------------------------------------------------
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
reg [4:0] reset;
always @(posedge clk) begin
if(init) reset <= 5'h1f;
else if((q == STATE_LAST) && (reset != 0))
reset <= reset - 5'd1;
end
// ---------------------------------------------------------------------
// ------------------ generate ram control signals ---------------------
// ---------------------------------------------------------------------
// all possible commands
localparam CMD_INHIBIT = 4'b1111;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_AUTO_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
reg [3:0] sd_cmd; // current command sent to sd ram
// drive control signals according to current command
assign sd_cs = sd_cmd[3];
assign sd_ras = sd_cmd[2];
assign sd_cas = sd_cmd[1];
assign sd_we = sd_cmd[0];
// drive ram data lines when writing, set them as inputs otherwise
// the eight bits are sent on both bytes ports. Which one's actually
// written depends on the state of dqm of which only one is active
// at a time when writing
assign sd_data = we?{din, din}:16'bZZZZZZZZZZZZZZZZ;
// assign dout = addr[0]?sd_data[7:0]:sd_data[15:8];
always @(posedge clk) begin
sd_cmd <= CMD_INHIBIT; // default: idle
if(reset != 0) begin
// initialization takes place at the end of the reset phase
if(q == STATE_CMD_START) begin
if(reset == 13) begin
sd_cmd <= CMD_PRECHARGE;
sd_addr[10] <= 1'b1; // precharge all banks
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
sd_addr <= MODE;
end
end
end else begin
// normal operation
// ------------------- cpu/chipset read/write ----------------------
if(we || oe) begin
// RAS phase
if(q == STATE_CMD_START) begin
sd_cmd <= CMD_ACTIVE;
sd_addr <= addr[21:9];
sd_ba <= addr[23:22];
// always return both bytes in a read. Only the correct byte
// is being stored during read. On write only one of the two
// bytes is enabled
if(!we) sd_dqm <= 2'b00;
else sd_dqm <= { addr[0], ~addr[0] };
end
// CAS phase
if(q == STATE_CMD_CONT) begin
sd_cmd <= we?CMD_WRITE:CMD_READ;
sd_addr <= { 4'b0010, addr[24], addr[8:1] }; // auto precharge
end
end
// read phase
// if(oe) begin
// if(q == STATE_READ)
// dout <= addr[0]?sd_data[7:0]:sd_data[15:8];
// end
// ------------------------ no access --------------------------
else begin
if(q == STATE_CMD_START)
sd_cmd <= CMD_AUTO_REFRESH;
end
end
end
endmodule

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity sms_mist is
port (
-- Clocks
CLOCK_27 : in std_logic_vector(1 downto 0); -- 27 MHz
-- SDRAM
SDRAM_nCS : out std_logic; -- Chip Select
SDRAM_DQ : inout std_logic_vector(15 downto 0); -- SDRAM Data bus 16 Bits
SDRAM_A : out std_logic_vector(12 downto 0); -- SDRAM Address bus 13 Bits
SDRAM_DQMH : out std_logic; -- SDRAM High Data Mask
SDRAM_DQML : out std_logic; -- SDRAM Low-byte Data Mask
SDRAM_nWE : out std_logic; -- SDRAM Write Enable
SDRAM_nCAS : out std_logic; -- SDRAM Column Address Strobe
SDRAM_nRAS : out std_logic; -- SDRAM Row Address Strobe
SDRAM_BA : out std_logic_vector(1 downto 0); -- SDRAM Bank Address
SDRAM_CLK : out std_logic; -- SDRAM Clock
SDRAM_CKE: out std_logic; -- SDRAM Clock Enable
-- SPI
SPI_SCK : in std_logic;
SPI_DI : in std_logic;
SPI_DO : out std_logic;
SPI_SS2 : in std_logic;
SPI_SS3 : in std_logic;
CONF_DATA0 : in std_logic;
-- VGA output
VGA_HS, -- H_SYNC
VGA_VS : out std_logic; -- V_SYNC
VGA_R, -- Red[5:0]
VGA_G, -- Green[5:0]
VGA_B : out std_logic_vector(5 downto 0); -- Blue[5:0]
-- Audio
AUDIO_L,
AUDIO_R : out std_logic
);
end sms_mist;
architecture Behavioral of sms_mist is
component vga_video is
port (
clk16: in std_logic;
pal: in std_logic;
x: out unsigned(8 downto 0);
y: out unsigned(7 downto 0);
color: in std_logic_vector(5 downto 0);
hsync: out std_logic;
vsync: out std_logic;
red: out std_logic_vector(1 downto 0);
green: out std_logic_vector(1 downto 0);
blue: out std_logic_vector(1 downto 0));
end component;
component sdram is
port( sd_data : inout std_logic_vector(15 downto 0);
sd_addr : out std_logic_vector(12 downto 0);
sd_dqm : out std_logic_vector(1 downto 0);
sd_ba : out std_logic_vector(1 downto 0);
sd_cs : out std_logic;
sd_we : out std_logic;
sd_ras : out std_logic;
sd_cas : out std_logic;
init : in std_logic;
clk : in std_logic;
clkref : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
addr : in std_logic_vector(24 downto 0);
oe : in std_logic;
we : in std_logic
);
end component;
constant CONF_STR : string := "SMS;SMS;O1,Video,NTSC,PAL;T2,Pause;T3,Reset";
function to_slv(s: string) return std_logic_vector is
constant ss: string(1 to s'length) := s;
variable rval: std_logic_vector(1 to 8 * s'length);
variable p: integer;
variable c: integer;
begin
for i in ss'range loop
p := 8 * i;
c := character'pos(ss(i));
rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8));
end loop;
return rval;
end function;
component user_io
generic ( STRLEN : integer := 0 );
port ( SPI_CLK, SPI_SS_IO, SPI_MOSI :in std_logic;
SPI_MISO : out std_logic;
conf_str : in std_logic_vector(8*STRLEN-1 downto 0);
JOY0 : out std_logic_vector(5 downto 0);
JOY1 : out std_logic_vector(5 downto 0);
status: out std_logic_vector(7 downto 0);
SWITCHES : out std_logic_vector(1 downto 0);
BUTTONS : out std_logic_vector(1 downto 0);
-- clk : in std_logic;
ps2_clk : out std_logic;
ps2_data : out std_logic
);
end component user_io;
component data_io is
port(sck: in std_logic;
ss: in std_logic;
sdi: in std_logic;
downloading: out std_logic;
size: out std_logic_vector(24 downto 0);
clk: in std_logic;
wr: out std_logic;
a: out std_logic_vector(24 downto 0);
d: out std_logic_vector(7 downto 0)
);
end component data_io;
component osd
port ( pclk, sck, ss, sdi, hs_in, vs_in : in std_logic;
red_in, blue_in, green_in : in std_logic_vector(5 downto 0);
red_out, blue_out, green_out : out std_logic_vector(5 downto 0);
hs_out, vs_out : out std_logic
);
end component osd;
signal clk_64M: std_logic;
signal clk_cpu: std_logic;
signal clk16: std_logic;
signal clk_div : unsigned(1 downto 0);
signal x: unsigned(8 downto 0);
signal y: unsigned(7 downto 0);
signal color: std_logic_vector(5 downto 0);
signal audio: std_logic;
signal pll_locked: std_logic;
signal ram_oe_n: STD_LOGIC;
signal ram_a: STD_LOGIC_VECTOR(21 downto 0);
signal sys_a: STD_LOGIC_VECTOR(21 downto 0);
signal ram_din: STD_LOGIC_VECTOR(7 downto 0);
signal ram_dout: STD_LOGIC_VECTOR(7 downto 0);
signal ram_we: std_logic;
signal ram_oe: std_logic;
signal sdram_dqm: std_logic_vector(1 downto 0);
signal switches : std_logic_vector(1 downto 0);
signal buttons : std_logic_vector(1 downto 0);
signal joy0 : std_logic_vector(5 downto 0);
signal joy1 : std_logic_vector(5 downto 0);
signal status : std_logic_vector(7 downto 0);
signal j1_tr : std_logic;
signal j2_tr : std_logic;
signal r : std_logic_vector(1 downto 0);
signal g : std_logic_vector(1 downto 0);
signal b : std_logic_vector(1 downto 0);
signal vs: std_logic;
signal hs: std_logic;
signal ioctl_wr : std_logic;
signal ioctl_addr : std_logic_vector(24 downto 0);
signal ioctl_data : std_logic_vector(7 downto 0);
signal ioctl_ram_addr : std_logic_vector(24 downto 0);
signal ioctl_ram_data : std_logic_vector(7 downto 0);
signal ioctl_ram_wr : std_logic := '0';
signal downl : std_logic := '0';
signal size : std_logic_vector(24 downto 0) := (others=>'0');
signal reset_n : std_logic := '1';
signal dbr : std_logic := '0';
begin
clock_inst: work.pll
port map (
inclk0 => CLOCK_27(0),
c0 => clk_64M,
c1 => SDRAM_CLK,
locked => pll_locked);
-- generate 16MHz video clock from 64MHz main clock by dividing it by 4
process(clk_64M)
begin
if rising_edge(clk_64M) then
clk_div <= clk_div + 1;
end if;
clk16 <= clk_div(1);
end process;
-- generate 8MHz system clock from 16MHz video clock
process(clk16)
begin
if rising_edge(clk16) then
clk_cpu <= not clk_cpu;
end if;
end process;
video_inst: vga_video
port map (
clk16 => clk16,
pal => status(1),
x => x,
y => y,
color => color,
hsync => hs,
vsync => vs,
red => r,
green => g,
blue => b
);
osd_inst : osd
port map (
pclk => clk16,
sdi => SPI_DI,
sck => SPI_SCK,
ss => SPI_SS3,
red_in => r & r & r,
green_in => g & g & g,
blue_in => b & b & b,
hs_in => hs,
vs_in => vs,
red_out => VGA_R,
green_out => VGA_G,
blue_out => VGA_B,
hs_out => VGA_HS,
vs_out => VGA_VS
);
-- sdram interface
SDRAM_CKE <= '1';
SDRAM_DQMH <= sdram_dqm(1);
SDRAM_DQML <= sdram_dqm(0);
sdram_inst : sdram
port map( sd_data => SDRAM_DQ,
sd_addr => SDRAM_A,
sd_dqm => sdram_dqm,
sd_cs => SDRAM_nCS,
sd_ba => SDRAM_BA,
sd_we => SDRAM_nWE,
sd_ras => SDRAM_nRAS,
sd_cas => SDRAM_nCAS,
clk => clk_64M,
clkref => clk_cpu,
init => not pll_locked,
din => ram_din,
addr => "000" & ram_a,
we => ram_we,
oe => ram_oe,
dout => ram_dout
);
ram_a <= ioctl_ram_addr(21 downto 0) when downl = '1' else sys_a;
ram_din <= ioctl_ram_data;
ram_we <= '1' when ioctl_ram_wr = '1' else '0';
ram_oe <= '0' when downl = '1' else not ram_oe_n;
data_io_inst: data_io
port map(SPI_SCK, SPI_SS2, SPI_DI, downl, size, clk_cpu, ioctl_wr, ioctl_addr, ioctl_data);
process(clk_cpu)
begin
if falling_edge(clk_cpu) then
if downl='1' then
reset_n <= '0';
dbr <= '1';
else
reset_n <= '1';
end if;
if ioctl_wr ='1' then
-- io controller sent a new byte.
ioctl_ram_wr <= '1';
ioctl_ram_addr <= ioctl_addr;
ioctl_ram_data <= ioctl_data;
else
ioctl_ram_wr <= '0';
end if;
end if;
end process;
user_io_d : user_io
generic map (STRLEN => CONF_STR'length)
port map (
SPI_CLK => SPI_SCK,
SPI_SS_IO => CONF_DATA0,
SPI_MISO => SPI_DO,
SPI_MOSI => SPI_DI,
conf_str => to_slv(CONF_STR),
status => status,
JOY0 => joy0,
JOY1 => joy1,
SWITCHES => switches,
BUTTONS => buttons,
-- clk => open,
ps2_clk => open,
ps2_data => open
);
system_inst: work.system
port map (
clk_cpu => clk_cpu,
clk_vdp => clk16,
ram_oe_n => ram_oe_n,
ram_a => sys_a,
ram_do => ram_dout,
j1_up => not joy0(3),
j1_down => not joy0(2),
j1_left => not joy0(1),
j1_right => not joy0(0),
j1_tl => not joy0(4),
j1_tr => not joy0(5),
j2_up => not joy1(3),
j2_down => not joy1(2),
j2_left => not joy1(1),
j2_right => not joy1(0),
j2_tl => not joy1(4),
j2_tr => not joy1(5),
reset => not buttons(1) and not status(3) and not status(0) and pll_locked and reset_n,
pause => not status(2),
x => x,
y => y,
color => color,
audio => audio,
dbr => dbr
);
AUDIO_L <= audio;
AUDIO_R <= audio;
end Behavioral;

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY spram IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED"
);
PORT
(
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END spram;
ARCHITECTURE SYN OF spram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => outdata_reg_a,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => widthad_a,
width_a => width_a,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => address,
data_a => data,
q_a => sub_wire0
);
END SYN;

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sprom IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED"
);
PORT
(
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END sprom;
ARCHITECTURE SYN OF sprom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => outdata_reg_a,
widthad_a => widthad_a,
width_a => width_a,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
END SYN;

373
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.all;
entity system is
port (
clk_cpu: in STD_LOGIC;
clk_vdp: in STD_LOGIC;
ram_oe_n: out STD_LOGIC;
ram_a: out STD_LOGIC_VECTOR(21 downto 0);
ram_do: in STD_LOGIC_VECTOR(7 downto 0);
j1_up: in STD_LOGIC;
j1_down: in STD_LOGIC;
j1_left: in STD_LOGIC;
j1_right: in STD_LOGIC;
j1_tl: in STD_LOGIC;
j1_tr: in STD_LOGIC;
j2_up: in STD_LOGIC;
j2_down: in STD_LOGIC;
j2_left: in STD_LOGIC;
j2_right: in STD_LOGIC;
j2_tl: in STD_LOGIC;
j2_tr: in STD_LOGIC;
reset: in STD_LOGIC;
pause: in STD_LOGIC;
x: in UNSIGNED(8 downto 0);
y: in UNSIGNED(7 downto 0);
color: out STD_LOGIC_VECTOR(5 downto 0);
audio: out STD_LOGIC;
dbr: in STD_LOGIC);
end system;
architecture Behavioral of system is
-- component dummy_z80 is
component T80se is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
port(
RESET_n: in std_logic;
CLK_n: in std_logic;
CLKEN: in std_logic;
WAIT_n: in std_logic;
INT_n: in std_logic;
NMI_n: in std_logic;
BUSRQ_n: in std_logic;
M1_n: out std_logic;
MREQ_n: out std_logic;
IORQ_n: out std_logic;
RD_n: out std_logic;
WR_n: out std_logic;
RFSH_n: out std_logic;
HALT_n: out std_logic;
BUSAK_n: out std_logic;
A: out std_logic_vector(15 downto 0);
DI: in std_logic_vector(7 downto 0);
DO: out std_logic_vector(7 downto 0)
);
end component;
component vdp is
port (
cpu_clk: in STD_LOGIC;
vdp_clk: in STD_LOGIC;
RD_n: in STD_LOGIC;
WR_n: in STD_LOGIC;
IRQ_n: out STD_LOGIC;
A: in STD_LOGIC_VECTOR(7 downto 0);
D_in: in STD_LOGIC_VECTOR(7 downto 0);
D_out: out STD_LOGIC_VECTOR(7 downto 0);
x: in unsigned(8 downto 0);
y: in unsigned(7 downto 0);
color: out std_logic_vector (5 downto 0));
end component;
component psg is
port (
clk: in STD_LOGIC;
WR_n: in STD_LOGIC;
D_in: in STD_LOGIC_VECTOR (7 downto 0);
output: out STD_LOGIC);
end component;
component io is
port (
clk: in STD_LOGIC;
WR_n: in STD_LOGIC;
RD_n: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (7 downto 0);
D_in: in STD_LOGIC_VECTOR (7 downto 0);
D_out: out STD_LOGIC_VECTOR (7 downto 0);
J1_up: in STD_LOGIC;
J1_down: in STD_LOGIC;
J1_left: in STD_LOGIC;
J1_right: in STD_LOGIC;
J1_tl: in STD_LOGIC;
J1_tr: in STD_LOGIC;
J2_up: in STD_LOGIC;
J2_down: in STD_LOGIC;
J2_left: in STD_LOGIC;
J2_right: in STD_LOGIC;
J2_tl: in STD_LOGIC;
J2_tr: in STD_LOGIC;
RESET: in STD_LOGIC);
end component;
signal RESET_n: std_logic;
signal RD_n: std_logic;
signal WR_n: std_logic;
signal IRQ_n: std_logic;
signal IO_n: std_logic;
signal A: std_logic_vector(15 downto 0);
signal D_in: std_logic_vector(7 downto 0);
signal D_out: std_logic_vector(7 downto 0);
signal vdp_RD_n: std_logic;
signal vdp_WR_n: std_logic;
signal vdp_D_out: std_logic_vector(7 downto 0);
signal psg_WR_n: std_logic;
signal ctl_WR_n: std_logic;
signal io_RD_n: std_logic;
signal io_WR_n: std_logic;
signal io_D_out: std_logic_vector(7 downto 0);
signal ram_WR_n: std_logic;
signal ram_D_out: std_logic_vector(7 downto 0);
signal cart_ram_D_out:std_logic_vector(7 downto 0);
signal rom_WR_n: std_logic;
signal boot_rom_D_out: std_logic_vector(7 downto 0);
signal reset_counter: unsigned(3 downto 0) := "1111";
signal bootloader: std_logic := '0';
signal irom_D_out: std_logic_vector(7 downto 0);
signal irom_RD_n: std_logic := '1';
signal bank0: std_logic_vector(7 downto 0) := "00000000";
signal bank1: std_logic_vector(7 downto 0) := "00000001";
signal bank2: std_logic_vector(7 downto 0) := "00000010";
signal ram_e: std_logic := '0';
begin
-- z80_inst: dummy_z80
z80_inst: T80se
port map(
RESET_n => RESET_n and reset,
CLK_n => clk_cpu,
CLKEN => '1',
WAIT_n => '1',
INT_n => IRQ_n,
NMI_n => pause,
BUSRQ_n => '1',
M1_n => open,
MREQ_n => open,
IORQ_n => IO_n,
RD_n => RD_n,
WR_n => WR_n,
RFSH_n => open,
HALT_n => open,
BUSAK_n => open,
A => A,
DI => D_out,
DO => D_in
);
vdp_inst: vdp
port map (
cpu_clk => clk_cpu,
vdp_clk => clk_vdp,
RD_n => vdp_RD_n,
WR_n => vdp_WR_n,
IRQ_n => IRQ_n,
A => A(7 downto 0),
D_in => D_in,
D_out => vdp_D_out,
x => x,
y => y,
color => color);
psg_inst: psg
port map (
clk => clk_cpu,
WR_n => psg_WR_n,
D_in => D_in,
output => audio);
io_inst: io
port map (
clk => clk_cpu,
WR_n => io_WR_n,
RD_n => io_RD_n,
A => A(7 downto 0),
D_in => D_in,
D_out => io_D_out,
J1_up => j1_up,
J1_down => j1_down,
J1_left => j1_left,
J1_right => j1_right,
J1_tl => j1_tl,
J1_tr => j1_tr,
J2_up => j2_up,
J2_down => j2_down,
J2_left => j2_left,
J2_right => j2_right,
J2_tl => j2_tl,
J2_tr => j2_tr,
RESET => reset);
ram_inst : entity work.spram
generic map
(
widthad_a => 13
)
port map
(
clock => clk_cpu,
address => A(12 downto 0),
wren => not ram_WR_n,
data => D_in,
q => ram_D_out
);
ram_inst2 : entity work.spram
generic map
(
widthad_a => 13
)
port map
(
clock => clk_cpu,
address => A(12 downto 0),
wren => not ram_WR_n,
data => D_in,
q => cart_ram_D_out
);
boot_rom_inst : entity work.sprom
generic map
(
init_file => "mboot.mif",
widthad_a => 14
)
port map
(
clock => clk_cpu,
address => A(13 downto 0),
q => boot_rom_D_out
);
-- glue logic
vdp_WR_n <= WR_n when io_n='0' and A(7 downto 6)="10" else '1';
vdp_RD_n <= RD_n when io_n='0' and (A(7 downto 6)="01" or A(7 downto 6)="10") else '1';
psg_WR_n <= WR_n when io_n='0' and A(7 downto 6)="01" else '1';
ctl_WR_n <= WR_n when io_n='0' and A(7 downto 6)="00" and A(0)='0' else '1';
io_WR_n <= WR_n when io_n='0' and A(7 downto 6)="00" and A(0)='1' else '1';
io_RD_n <= RD_n when io_n='0' and A(7 downto 6)="11" else '1';
ram_WR_n <= WR_n when io_n='1' and A(15 downto 14)="11" else '1';
process (clk_cpu)
begin
if rising_edge(clk_cpu) then
if reset='0' then
bootloader <= '0';
end if;
-- memory control
if reset_counter>0 then
reset_counter <= reset_counter - 1;
elsif ctl_WR_n='0' then
if bootloader='0' then
bootloader <= '1';
reset_counter <= (others=>'1');
end if;
end if;
end if;
end process;
reset_n <= '0' when reset_counter>0 else '1';
irom_D_out <= boot_rom_D_out when bootloader='0' and A(15 downto 14)="00" and dbr='0' else ram_do;
process (io_n,A,vdp_D_out,io_D_out,irom_D_out,ram_D_out)
begin
if io_n='0' then
case A(7 downto 6) is
when "11" =>
D_out <= io_D_out;
when others =>
D_out <= vdp_D_out;
end case;
else
if A(15 downto 14)="11" then
D_out <= ram_D_out;
elsif (A(15 downto 14)="10" and ram_e='1') then
D_out <= cart_ram_D_out;
else
D_out <= irom_D_out;
end if;
end if;
end process;
-- external ram control
process (clk_cpu)
begin
if(RESET_n='0' or reset='0') then
bank0 <= "00000000";
bank1 <= "00000001";
bank2 <= "00000010";
else
if rising_edge(clk_cpu) then
if WR_n='0' and A(15 downto 2)="11111111111111" then
case A(1 downto 0) is
when "00" =>
if (D_in(3) = '1') then
ram_e <= '1';
end if;
when "01" => bank0 <= D_in;
when "10" => bank1 <= D_in;
when "11" => bank2 <= D_in;
when others =>
end case;
end if;
end if;
end if;
end process;
ram_oe_n <= RD_n;
ram_a(13 downto 0) <= A(13 downto 0);
process (reset,A,bank0,bank1,bank2)
begin
case A(15 downto 14) is
when "00" =>
-- first kilobyte is always from bank 0
if A(13 downto 10)="0000" then
ram_a(21 downto 14) <= (others=>'0');
else
ram_a(21 downto 14) <= bank0;
end if;
when "01" =>
ram_a(21 downto 14) <= bank1;
when others =>
if(ram_e) = '0' then
ram_a(21 downto 14) <= bank2;
end if;
end case;
end process;
end Behavioral;

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//
// user_io.v
//
// user_io for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// parameter STRLEN and the actual length of conf_str have to match
module user_io #(parameter STRLEN=0) (
input [(8*STRLEN)-1:0] conf_str,
input SPI_CLK,
input SPI_SS_IO,
output reg SPI_MISO,
input SPI_MOSI,
output [5:0] JOY0,
output [5:0] JOY1,
output [1:0] BUTTONS,
output [1:0] SWITCHES,
output reg [7:0] status,
input clk,
output ps2_clk,
output reg ps2_data
);
reg [6:0] sbuf;
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [7:0] byte_cnt; // counts bytes
reg [5:0] joystick0;
reg [5:0] joystick1;
reg [3:0] but_sw;
assign JOY0 = joystick0;
assign JOY1 = joystick1;
assign BUTTONS = but_sw[1:0];
assign SWITCHES = but_sw[3:2];
// this variant of user_io is for 8 bit cores (type == a4) only
wire [7:0] core_type = 8'ha4;
// drive MISO only when transmitting core id
always@(negedge SPI_CLK or posedge SPI_SS_IO) begin
if(SPI_SS_IO == 1) begin
SPI_MISO <= 1'bZ;
end else begin
// first byte returned is always core type, further bytes are
// command dependent
if(byte_cnt == 0) begin
SPI_MISO <= core_type[~bit_cnt];
end else begin
// reading config string
if(cmd == 8'h14) begin
// returning a byte from string
if(byte_cnt < STRLEN + 1)
SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
else
SPI_MISO <= 1'b0;
end
end
end
end
// 8 byte fifo to store ps2 bytes
localparam PS2_FIFO_BITS = 3;
reg [7:0] ps2_fifo [(2**PS2_FIFO_BITS)-1:0];
reg [PS2_FIFO_BITS-1:0] ps2_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_tx_state;
reg [7:0] ps2_tx_byte;
reg ps2_parity;
assign ps2_clk = clk || (ps2_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_r_inc;
always@(posedge clk) begin
ps2_r_inc <= 1'b0;
if(ps2_r_inc)
ps2_rptr <= ps2_rptr + 1;
// transmitter is idle?
if(ps2_tx_state == 0) begin
// data in fifo present?
if(ps2_wptr != ps2_rptr) begin
// load tx register from fifo
ps2_tx_byte <= ps2_fifo[ps2_rptr];
ps2_r_inc <= 1'b1;
// reset parity
ps2_parity <= 1'b1;
// start transmitter
ps2_tx_state <= 4'd1;
// put start bit on data line
ps2_data <= 1'b0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_tx_state >= 1)&&(ps2_tx_state < 9)) begin
ps2_data <= ps2_tx_byte[0]; // data bits
ps2_tx_byte[6:0] <= ps2_tx_byte[7:1]; // shift down
if(ps2_tx_byte[0])
ps2_parity <= !ps2_parity;
end
// transmission of parity
if(ps2_tx_state == 9)
ps2_data <= ps2_parity;
// transmission of stop bit
if(ps2_tx_state == 10)
ps2_data <= 1'b1; // stop bit is 1
// advance state machine
if(ps2_tx_state < 11)
ps2_tx_state <= ps2_tx_state + 4'd1;
else
ps2_tx_state <= 4'd0;
end
end
// SPI receiver
always@(posedge SPI_CLK or posedge SPI_SS_IO) begin
if(SPI_SS_IO == 1) begin
bit_cnt <= 3'd0;
byte_cnt <= 8'd0;
end else begin
sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
bit_cnt <= bit_cnt + 3'd1;
if(bit_cnt == 7) byte_cnt <= byte_cnt + 8'd1;
// finished reading command byte
if(bit_cnt == 7) begin
if(byte_cnt == 0)
cmd <= { sbuf, SPI_MOSI};
if(byte_cnt != 0) begin
if(cmd == 8'h01)
but_sw <= { sbuf[2:0], SPI_MOSI };
if(cmd == 8'h02)
joystick0 <= { sbuf[4:0], SPI_MOSI };
if(cmd == 8'h03)
joystick1 <= { sbuf[4:0], SPI_MOSI };
if(cmd == 8'h05) begin
// store incoming keyboard bytes in
ps2_fifo[ps2_wptr] <= { sbuf, SPI_MOSI };
ps2_wptr <= ps2_wptr + 1;
end
if(cmd == 8'h15) begin
status <= { sbuf[4:0], SPI_MOSI };
end
end
end
end
end
endmodule

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vdp is
port (
cpu_clk: in STD_LOGIC;
vdp_clk: in STD_LOGIC;
RD_n: in STD_LOGIC;
WR_n: in STD_LOGIC;
IRQ_n: out STD_LOGIC;
A: in STD_LOGIC_VECTOR (7 downto 0);
D_in: in STD_LOGIC_VECTOR (7 downto 0);
D_out: out STD_LOGIC_VECTOR (7 downto 0);
x: unsigned(8 downto 0);
y: unsigned(7 downto 0);
color: out std_logic_vector (5 downto 0));
end vdp;
architecture Behavioral of vdp is
component vdp_main is
port (
clk: in std_logic;
vram_A: out std_logic_vector(13 downto 0);
vram_D: in std_logic_vector(7 downto 0);
cram_A: out std_logic_vector(4 downto 0);
cram_D: in std_logic_vector(5 downto 0);
x: unsigned(8 downto 0);
y: unsigned(7 downto 0);
color: out std_logic_vector (5 downto 0);
display_on: in std_logic;
mask_column0: in std_logic;
overscan: in std_logic_vector (3 downto 0);
bg_address: in std_logic_vector (2 downto 0);
bg_scroll_x: in unsigned(7 downto 0);
bg_scroll_y: in unsigned(7 downto 0);
disable_hscroll: in std_logic;
spr_address: in std_logic_vector (5 downto 0);
spr_high_bit: in std_logic;
spr_shift: in std_logic;
spr_tall: in std_logic);
end component;
component vdp_cram is
port (
cpu_clk: in STD_LOGIC;
cpu_WE: in std_logic;
cpu_A: in std_logic_vector(4 downto 0);
cpu_D: in std_logic_vector(5 downto 0);
vdp_clk: in STD_LOGIC;
vdp_A: in std_logic_vector(4 downto 0);
vdp_D: out std_logic_vector(5 downto 0));
end component;
-- helper bits
signal data_write: std_logic;
signal address_ff: std_logic := '0';
signal to_cram: boolean := false;
-- vram and cram lines for the cpu interface
signal xram_cpu_A: std_logic_vector(13 downto 0);
signal vram_cpu_WE: std_logic;
signal cram_cpu_WE: std_logic;
signal vram_cpu_D_out: std_logic_vector(7 downto 0);
signal xram_cpu_A_incr: std_logic := '0';
-- vram and cram lines for the video interface
signal vram_vdp_A: std_logic_vector(13 downto 0);
signal vram_vdp_D: std_logic_vector(7 downto 0);
signal cram_vdp_A: std_logic_vector(4 downto 0);
signal cram_vdp_D: std_logic_vector(5 downto 0);
-- control bits
signal display_on: std_logic := '1';
signal disable_hscroll: std_logic := '0';
signal mask_column0: std_logic := '0';
signal overscan: std_logic_vector (3 downto 0) := "0000";
signal irq_frame_en: std_logic := '0';
signal irq_line_en: std_logic := '0';
signal irq_line_count: unsigned(7 downto 0) := (others=>'1');
signal bg_address: std_logic_vector (2 downto 0) := (others=>'0');
signal bg_scroll_x: unsigned(7 downto 0) := (others=>'0');
signal bg_scroll_y: unsigned(7 downto 0) := (others=>'0');
signal spr_address: std_logic_vector (5 downto 0) := (others=>'0');
signal spr_shift: std_logic := '0';
signal spr_tall: std_logic := '0';
signal spr_high_bit: std_logic := '0';
-- various counters
signal last_y0: std_logic := '0';
signal vbi_done: std_logic := '0';
signal virq_flag: std_logic := '0';
signal reset_virq_flag: boolean := false;
signal irq_counter: unsigned(5 downto 0) := (others=>'0');
signal hbl_counter: unsigned(7 downto 0) := (others=>'0');
signal vbl_irq: std_logic;
signal hbl_irq: std_logic;
begin
vdp_main_inst: vdp_main
port map(
clk => vdp_clk,
vram_A => vram_vdp_A,
vram_D => vram_vdp_D,
cram_A => cram_vdp_A,
cram_D => cram_vdp_D,
x => x,
y => y,
color => color,
display_on => display_on,
mask_column0 => mask_column0,
overscan => overscan,
bg_address => bg_address,
bg_scroll_x => bg_scroll_x,
bg_scroll_y => bg_scroll_y,
disable_hscroll=>disable_hscroll,
spr_address => spr_address,
spr_high_bit => spr_high_bit,
spr_shift => spr_shift,
spr_tall => spr_tall);
vdp_vram_inst : entity work.dpram
generic map
(
init_file => "vram.mif",
widthad_a => 14
)
port map
(
clock_a => cpu_clk,
address_a => xram_cpu_A(13 downto 0),
wren_a => vram_cpu_WE,
data_a => D_in,
q_a => vram_cpu_D_out,
clock_b => not vdp_clk,
address_b => vram_vdp_A,
wren_b => '0',
data_b => (others => '0'),
q_b => vram_vdp_D
);
vdp_cram_inst: vdp_cram
port map (
cpu_clk => cpu_clk,
cpu_WE => cram_cpu_WE,
cpu_A => xram_cpu_A(4 downto 0),
cpu_D => D_in(5 downto 0),
vdp_clk => vdp_clk,
vdp_A => cram_vdp_A,
vdp_D => cram_vdp_D);
data_write <= not WR_n and not A(0);
cram_cpu_WE <= data_write when to_cram else '0';
vram_cpu_WE <= data_write when not to_cram else '0';
process (cpu_clk)
begin
if rising_edge(cpu_clk) then
if WR_n='0' then
if A(0)='0' then
xram_cpu_A_incr <= '1';
else
if address_ff='0' then
xram_cpu_A(7 downto 0) <= D_in;
else
xram_cpu_A(13 downto 8) <= D_in(5 downto 0);
to_cram <= D_in(7 downto 6)="11";
case D_in is
when "10000000" =>
disable_hscroll<= xram_cpu_A(6);
mask_column0 <= xram_cpu_A(5);
irq_line_en <= xram_cpu_A(4);
spr_shift <= xram_cpu_A(3);
when "10000001" =>
display_on <= xram_cpu_A(6);
irq_frame_en <= xram_cpu_A(5);
spr_tall <= xram_cpu_A(1);
when "10000010" =>
bg_address <= xram_cpu_A(3 downto 1);
when "10000101" =>
spr_address <= xram_cpu_A(6 downto 1);
when "10000110" =>
spr_high_bit <= xram_cpu_A(2);
when "10000111" =>
overscan <= xram_cpu_A(3 downto 0);
when "10001000" =>
bg_scroll_x <= unsigned(xram_cpu_A(7 downto 0));
when "10001001" =>
bg_scroll_y <= unsigned(xram_cpu_A(7 downto 0));
when "10001010" =>
irq_line_count <= unsigned(xram_cpu_A(7 downto 0));
when others =>
end case;
end if;
address_ff <= not address_ff;
end if;
elsif RD_n='0' then
case A(7 downto 6)&A(0) is
when "010" =>
D_out <= std_logic_vector(y);
when "011" =>
D_out <= "11111111"; -- std_logic_vector(x(7 downto 0)); -- bad in VGA mode ...
when "100" =>
D_out <= vram_cpu_D_out;
xram_cpu_A_incr <= '1';
when "101" =>
D_out(7) <= virq_flag;
D_out(6 downto 0) <= (others=>'0');
reset_virq_flag <= true;
when others =>
end case;
elsif xram_cpu_A_incr='1' then
xram_cpu_A <= std_logic_vector(unsigned(xram_cpu_A) + 1);
xram_cpu_A_incr <= '0';
else
reset_virq_flag <= false;
end if;
end if;
end process;
process (vdp_clk)
begin
if rising_edge(vdp_clk) then
-- we need to make sure we only send one vbi per image since the
-- y counter repeats within the image and the value 192 occurs twice
if y=0 then
vbi_done <= '0';
end if;
if x=256 and y=192 and not (last_y0=std_logic(y(0))) then
if(vbi_done='0') then
vbl_irq <= irq_frame_en;
vbi_done <= '1';
end if;
else
vbl_irq <= '0';
end if;
end if;
end process;
process (vdp_clk)
begin
if rising_edge(vdp_clk) then
if x=256 and not (last_y0=std_logic(y(0))) then
last_y0 <= std_logic(y(0));
if y<192 then
if hbl_counter=0 then
hbl_irq <= irq_line_en;
hbl_counter <= irq_line_count;
else
hbl_counter <= hbl_counter-1;
end if;
else
hbl_counter <= irq_line_count;
end if;
else
hbl_irq <= '0';
end if;
end if;
end process;
process (vdp_clk)
begin
if rising_edge(vdp_clk) then
if vbl_irq='1' then
virq_flag <= '1';
elsif reset_virq_flag then
virq_flag <= '0';
end if;
end if;
end process;
process (vdp_clk)
begin
if rising_edge(vdp_clk) then
if vbl_irq='1' or hbl_irq='1' then
irq_counter <= (others=>'1');
elsif irq_counter>0 then
irq_counter <= irq_counter-1;
end if;
end if;
end process;
IRQ_n <= '0' when irq_counter>0 else '1';
end Behavioral;

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library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity vdp_background is
port (
clk: in std_logic;
reset: in std_logic;
table_address: in std_logic_vector(13 downto 11);
scroll_x: in unsigned(7 downto 0);
disable_hscroll: in std_logic;
y: in unsigned(7 downto 0);
vram_A: out std_logic_vector(13 downto 0);
vram_D: in std_logic_vector(7 downto 0);
color: out std_logic_vector(4 downto 0);
priority: out std_logic
);
end entity;
architecture rtl of vdp_background is
signal tile_index : std_logic_vector (8 downto 0);
signal x : unsigned (7 downto 0);
signal tile_y : std_logic_vector (2 downto 0);
signal palette : std_logic;
signal priority_latch: std_logic;
signal flip_x : std_logic;
signal data0 : std_logic_vector(7 downto 0);
signal data1 : std_logic_vector(7 downto 0);
signal data2 : std_logic_vector(7 downto 0);
signal data3 : std_logic_vector(7 downto 0);
signal shift0 : std_logic_vector(7 downto 0);
signal shift1 : std_logic_vector(7 downto 0);
signal shift2 : std_logic_vector(7 downto 0);
signal shift3 : std_logic_vector(7 downto 0);
begin
process (clk) begin
if (rising_edge(clk)) then
if (reset='1') then
if disable_hscroll='0' or y>=16 then
x <= 240-scroll_x;
else
x <= "11110000"; -- 240
end if;
else
x <= x + 1;
end if;
end if;
end process;
process (clk)
variable char_address : std_logic_vector(12 downto 0);
variable data_address : std_logic_vector(11 downto 0);
begin
if (rising_edge(clk)) then
char_address(12 downto 10) := table_address;
char_address(9 downto 5) := std_logic_vector(y(7 downto 3));
char_address(4 downto 0) := std_logic_vector(x(7 downto 3) + 1);
data_address := tile_index & tile_y;
case x(2 downto 0) is
when "000" => vram_A <= char_address & "0";
when "001" => vram_A <= char_address & "1";
when "011" => vram_A <= data_address & "00";
when "100" => vram_A <= data_address & "01";
when "101" => vram_A <= data_address & "10";
when "110" => vram_A <= data_address & "11";
when others =>
end case;
end if;
end process;
process (clk) begin
if (rising_edge(clk)) then
case x(2 downto 0) is
when "001" =>
tile_index(7 downto 0) <= vram_D;
when "010" =>
tile_index(8) <= vram_D(0);
flip_x <= vram_D(1);
tile_y(0) <= y(0) xor vram_D(2);
tile_y(1) <= y(1) xor vram_D(2);
tile_y(2) <= y(2) xor vram_D(2);
palette <= vram_D(3);
priority_latch <= vram_D(4);
when "100" =>
data0 <= vram_D;
when "101" =>
data1 <= vram_D;
when "110" =>
data2 <= vram_D;
-- when "111" =>
-- data3 <= vram_D;
when others =>
end case;
end if;
end process;
process (clk) begin
if (rising_edge(clk)) then
case x(2 downto 0) is
when "111" =>
if flip_x='0' then
shift0 <= data0;
shift1 <= data1;
shift2 <= data2;
shift3 <= vram_D;
else
shift0 <= data0(0)&data0(1)&data0(2)&data0(3)&data0(4)&data0(5)&data0(6)&data0(7);
shift1 <= data1(0)&data1(1)&data1(2)&data1(3)&data1(4)&data1(5)&data1(6)&data1(7);
shift2 <= data2(0)&data2(1)&data2(2)&data2(3)&data2(4)&data2(5)&data2(6)&data2(7);
shift3 <= vram_D(0)&vram_D(1)&vram_D(2)&vram_D(3)&vram_D(4)&vram_D(5)&vram_D(6)&vram_D(7);
end if;
color(4) <= palette;
priority <= priority_latch;
when others =>
shift0(7 downto 1) <= shift0(6 downto 0);
shift1(7 downto 1) <= shift1(6 downto 0);
shift2(7 downto 1) <= shift2(6 downto 0);
shift3(7 downto 1) <= shift3(6 downto 0);
end case;
end if;
end process;
color(0) <= shift0(7);
color(1) <= shift1(7);
color(2) <= shift2(7);
color(3) <= shift3(7);
end architecture;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vdp_cram is
port (
cpu_clk: in STD_LOGIC;
cpu_WE: in STD_LOGIC;
cpu_A: in STD_LOGIC_VECTOR (4 downto 0);
cpu_D: in STD_LOGIC_VECTOR (5 downto 0);
vdp_clk: in STD_LOGIC;
vdp_A: in STD_LOGIC_VECTOR (4 downto 0);
vdp_D: out STD_LOGIC_VECTOR (5 downto 0));
end vdp_cram;
architecture Behavioral of vdp_cram is
type t_ram is array (0 to 31) of std_logic_vector(5 downto 0);
signal ram : t_ram := (others => "111111");
begin
process (cpu_clk)
variable i : integer range 0 to 31;
begin
if rising_edge(cpu_clk) then
if cpu_WE='1'then
i := to_integer(unsigned(cpu_A));
ram(i) <= cpu_D;
end if;
end if;
end process;
process (vdp_clk)
variable i : integer range 0 to 31;
begin
if rising_edge(vdp_clk) then
i := to_integer(unsigned(vdp_A));
vdp_D <= ram(i);
end if;
end process;
end Behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vdp_main is
port (
clk: in std_logic;
vram_A: out std_logic_vector(13 downto 0);
vram_D: in std_logic_vector(7 downto 0);
cram_A: out std_logic_vector(4 downto 0);
cram_D: in std_logic_vector(5 downto 0);
x: unsigned(8 downto 0);
y: unsigned(7 downto 0);
color: out std_logic_vector (5 downto 0);
display_on: in std_logic;
mask_column0: in std_logic;
overscan: in std_logic_vector (3 downto 0);
bg_address: in std_logic_vector (2 downto 0);
bg_scroll_x: in unsigned(7 downto 0);
bg_scroll_y: in unsigned(7 downto 0);
disable_hscroll: in std_logic;
spr_address: in std_logic_vector (5 downto 0);
spr_high_bit: in std_logic;
spr_shift: in std_logic;
spr_tall: in std_logic);
end vdp_main;
architecture Behavioral of vdp_main is
component vdp_background is
port (
clk: in std_logic;
reset: in std_logic;
table_address: in std_logic_vector(13 downto 11);
scroll_x: in unsigned(7 downto 0);
disable_hscroll: in std_logic;
y: in unsigned(7 downto 0);
vram_A: out std_logic_vector(13 downto 0);
vram_D: in std_logic_vector(7 downto 0);
color: out std_logic_vector(4 downto 0);
priority: out std_logic);
end component;
component vdp_sprites is
port (
clk: in std_logic;
table_address: in std_logic_vector(13 downto 8);
char_high_bit: in std_logic;
tall: in std_logic;
x: in unsigned(8 downto 0);
y: in unsigned(7 downto 0);
vram_A: out std_logic_vector(13 downto 0);
vram_D: in std_logic_vector(7 downto 0);
color: out std_logic_vector(3 downto 0));
end component;
signal bg_y: unsigned(7 downto 0);
signal bg_vram_A: std_logic_vector(13 downto 0);
signal bg_color: std_logic_vector(4 downto 0);
signal bg_priority: std_logic;
signal spr_vram_A: std_logic_vector(13 downto 0);
signal spr_color: std_logic_vector(3 downto 0);
signal line_reset: std_logic;
begin
process (y,bg_scroll_y)
variable sum: unsigned(8 downto 0);
begin
sum := ('0'&y)+('0'&bg_scroll_y);
if (sum>=224) then
sum := sum-224;
end if;
bg_y <= sum(7 downto 0);
end process;
line_reset <= '1' when x=512-16 else '0';
vdp_bg_inst: vdp_background
port map (
clk => clk,
table_address => bg_address,
reset => line_reset,
disable_hscroll=> disable_hscroll,
scroll_x => bg_scroll_x,
y => bg_y,
vram_A => bg_vram_A,
vram_D => vram_D,
color => bg_color,
priority => bg_priority);
vdp_spr_inst: vdp_sprites
port map (
clk => clk,
table_address => spr_address,
char_high_bit => spr_high_bit,
tall => spr_tall,
x => x,
y => y,
vram_A => spr_vram_A,
vram_D => vram_D,
color => spr_color);
process (x, y, bg_priority, spr_color, bg_color, overscan)
variable spr_active : boolean;
variable bg_active : boolean;
begin
if x<256 and y<192 and (mask_column0='0' or x>=8) then
spr_active := not (spr_color="0000");
bg_active := not (bg_color(3 downto 0)="0000");
if (bg_priority='0' and spr_active) or (bg_priority='1' and not bg_active) then
cram_A <= "1"&spr_color;
else
cram_A <= bg_color;
end if;
else
cram_A <= "1"&overscan;
end if;
end process;
vram_A <= spr_vram_A when x>=256 and x<384 else bg_vram_A;
color <= cram_D;
end Behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vpd_sprite_shifter is
Port( clk : in std_logic;
x : in unsigned (7 downto 0);
spr_x : in unsigned (7 downto 0);
spr_d0: in std_logic_vector (7 downto 0);
spr_d1: in std_logic_vector (7 downto 0);
spr_d2: in std_logic_vector (7 downto 0);
spr_d3: in std_logic_vector (7 downto 0);
color : out std_logic_vector (3 downto 0);
active: out std_logic);
end vpd_sprite_shifter;
architecture Behavioral of vpd_sprite_shifter is
signal count : integer range 0 to 8;
signal shift0 : std_logic_vector (7 downto 0) := (others=>'0');
signal shift1 : std_logic_vector (7 downto 0) := (others=>'0');
signal shift2 : std_logic_vector (7 downto 0) := (others=>'0');
signal shift3 : std_logic_vector (7 downto 0) := (others=>'0');
begin
process (clk)
begin
if rising_edge(clk) then
if spr_x=x then
shift0 <= spr_d0;
shift1 <= spr_d1;
shift2 <= spr_d2;
shift3 <= spr_d3;
else
shift0 <= shift0(6 downto 0)&"0";
shift1 <= shift1(6 downto 0)&"0";
shift2 <= shift2(6 downto 0)&"0";
shift3 <= shift3(6 downto 0)&"0";
end if;
end if;
end process;
color <= shift3(7)&shift2(7)&shift1(7)&shift0(7);
active <= shift3(7) or shift2(7) or shift1(7) or shift0(7);
end Behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vdp_sprites is
port (clk : in std_logic;
table_address : in STD_LOGIC_VECTOR (13 downto 8);
char_high_bit : in std_logic;
tall : in std_logic;
vram_A : out STD_LOGIC_VECTOR (13 downto 0);
vram_D : in STD_LOGIC_VECTOR (7 downto 0);
x : in unsigned (8 downto 0);
y : in unsigned (7 downto 0);
color : out STD_LOGIC_VECTOR (3 downto 0));
end vdp_sprites;
architecture Behavioral of vdp_sprites is
component vpd_sprite_shifter is
port( clk : in std_logic;
x : in unsigned (7 downto 0);
spr_x : in unsigned (7 downto 0);
spr_d0: in std_logic_vector (7 downto 0);
spr_d1: in std_logic_vector (7 downto 0);
spr_d2: in std_logic_vector (7 downto 0);
spr_d3: in std_logic_vector (7 downto 0);
color : out std_logic_vector (3 downto 0);
active: out std_logic);
end component;
constant WAITING: integer := 0;
constant COMPARE: integer := 1;
constant LOAD_N: integer := 2;
constant LOAD_X: integer := 3;
constant LOAD_0: integer := 4;
constant LOAD_1: integer := 5;
constant LOAD_2: integer := 6;
constant LOAD_3: integer := 7;
signal state: integer := WAITING;
signal count: integer range 0 to 7;
signal index: unsigned(5 downto 0);
signal data_address: std_logic_vector(13 downto 2);
type tenable is array (0 to 7) of boolean;
type tx is array (0 to 7) of unsigned(7 downto 0);
type tdata is array (0 to 7) of std_logic_vector(7 downto 0);
signal enable: tenable;
signal spr_x: tx;
signal spr_d0: tdata;
signal spr_d1: tdata;
signal spr_d2: tdata;
signal spr_d3: tdata;
type tcolor is array (0 to 7) of std_logic_vector(3 downto 0);
signal spr_color: tcolor;
signal active: std_logic_vector(7 downto 0);
begin
shifters:
for i in 0 to 7 generate
begin
shifter: vpd_sprite_shifter
port map(clk => clk,
x => x(7 downto 0),
spr_x => spr_x(i),
spr_d0=> spr_d0(i),
spr_d1=> spr_d1(i),
spr_d2=> spr_d2(i),
spr_d3=> spr_d3(i),
color => spr_color(i),
active=> active(i));
end generate;
with state select
vram_a <= table_address&"00"&std_logic_vector(index) when COMPARE,
table_address&"1"&std_logic_vector(index)&"1" when LOAD_N,
table_address&"1"&std_logic_vector(index)&"0" when LOAD_X,
data_address&"00" when LOAD_0,
data_address&"01" when LOAD_1,
data_address&"10" when LOAD_2,
data_address&"11" when LOAD_3,
(others=>'0') when others;
process (clk)
variable y9 : unsigned(8 downto 0);
variable d9 : unsigned(8 downto 0);
variable delta : unsigned(8 downto 0);
begin
if rising_edge(clk) then
if x=255 then
count <= 0;
enable <= (others=>false);
state <= COMPARE;
index <= (others=>'0');
else
y9 := "0"&y;
d9 := "0"&unsigned(vram_D);
if d9>=240 then
d9 := d9-256;
end if;
delta := y9-d9;
case state is
when COMPARE =>
if d9=208 then
state <= WAITING; -- stop
elsif 0<=delta and ((delta<8 and tall='0') or (delta<16 and tall='1')) then
enable(count) <= true;
data_address(5 downto 2) <= std_logic_vector(delta(3 downto 0));
state <= LOAD_N;
else
if index<63 then
index <= index+1;
else
state <= WAITING;
end if;
end if;
when LOAD_N =>
data_address(13) <= char_high_bit;
data_address(12 downto 6) <= vram_d(7 downto 1);
if tall='0' then
data_address(5) <= vram_d(0);
end if;
state <= LOAD_X;
when LOAD_X =>
spr_x(count) <= unsigned(vram_d);
state <= LOAD_0;
when LOAD_0 =>
spr_d0(count) <= vram_d;
state <= LOAD_1;
when LOAD_1 =>
spr_d1(count) <= vram_d;
state <= LOAD_2;
when LOAD_2 =>
spr_d2(count) <= vram_d;
state <= LOAD_3;
when LOAD_3 =>
spr_d3(count) <= vram_d;
if (count<7) then
state <= COMPARE;
index <= index+1;
count <= count+1;
else
state <= WAITING;
end if;
when others =>
end case;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if enable(0) and active(0)='1' then
color <= spr_color(0);
elsif enable(1) and active(1)='1' then
color <= spr_color(1);
elsif enable(2) and active(2)='1' then
color <= spr_color(2);
elsif enable(3) and active(3)='1' then
color <= spr_color(3);
elsif enable(4) and active(4)='1' then
color <= spr_color(4);
elsif enable(5) and active(5)='1' then
color <= spr_color(5);
elsif enable(6) and active(6)='1' then
color <= spr_color(6);
elsif enable(7) and active(7)='1' then
color <= spr_color(7);
else
color <= (others=>'0');
end if;
end if;
end process;
end Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:59:35 01/22/2012
-- Design Name:
-- Module Name: vdp_vga_timing - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_video is
port (
clk16: in std_logic;
pal: in std_logic;
x: out unsigned(8 downto 0);
y: out unsigned(7 downto 0);
color: in std_logic_vector(5 downto 0);
hsync: out std_logic;
vsync: out std_logic;
red: out std_logic_vector(1 downto 0);
green: out std_logic_vector(1 downto 0);
blue: out std_logic_vector(1 downto 0));
end vga_video;
architecture Behavioral of vga_video is
signal hcount: unsigned (8 downto 0) := (others=>'0');
signal vcount: unsigned (9 downto 0) := (others=>'0');
signal visible: boolean;
signal y9: unsigned (8 downto 0);
begin
process (clk16)
begin
if rising_edge(clk16) then
if (pal='0' and hcount=507) or (pal='1' and hcount=511) then
hcount <= (others => '0');
if (pal='0' and vcount=523) or (pal='1' and vcount=625) then
vcount <= (others=>'0');
else
vcount <= vcount + 1;
end if;
else
hcount <= hcount + 1;
end if;
end if;
end process;
-- y counter over 263 (NTSC) or 313 (PAL) lines
-- NTSC 256x192 00-DA, D5-FF
-- PAL 256x192 00-F2, BA-FF
x <= hcount-(91+75);
y9 <= (vcount(9 downto 1)-43) when pal='0' else (vcount(9 downto 1)-70);
y <= y9(7 downto 0);
hsync <= '0' when hcount<61 else '1';
vsync <= '0' when vcount<2 else '1';
visible <=
(vcount>=35 and vcount<35+480 and hcount>=91 and hcount<91+406) when pal='0' else
(vcount>=85 and vcount<85+480 and hcount>=95 and hcount<95+406);
process (clk16)
begin
if rising_edge(clk16) then
if visible then
red <= color(1 downto 0);
green <= color(3 downto 2);
blue <= color(5 downto 4);
else
red <= (others=>'0');
green <= (others=>'0');
blue <= (others=>'0');
end if;
end if;
end process;
end Behavioral;

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--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
OverFlow_v <= Carry_v xor Carry7_v;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

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--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

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--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;

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--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80se is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80se;
architecture rtl of T80se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => Mode,
IOWait => IOWait)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;