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Code Issues Releases Wiki Activity

Dirty bus error fix

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This commit is contained in:
harbaum
2013-04-23 19:23:31 +00:00
parent 2853dbb8e4
commit e8c3cca1cd
3 changed files with 76 additions and 38 deletions
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68
cores/mist/TG68KdotC_Kernel.vhd
View File

@@ -19,6 +19,8 @@
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- add berr handling 10.03.2013
-- bugfix session 07/08.Feb.2013
-- movem ,-(an)
-- movem (an)+, - thanks Gerhard Suttner
@@ -76,7 +78,7 @@ entity TG68KdotC_Kernel is
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
IPL_autovector : in std_logic:='0';
berr : in std_logic:='0'; --TH
berr : in std_logic:='0'; -- only 68000 Stackpointer dummy
CPU : in std_logic_vector(1 downto 0):="00"; -- 00->68000 01->68010 11->68020(only some parts - yet)
addr : buffer std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
@@ -207,7 +209,7 @@ architecture logic of TG68KdotC_Kernel is
signal set_V_Flag : bit;
signal set_vectoraddr : bit;
signal writeSR : bit;
signal trap_berr : bit; -- TH
signal trap_berr : bit;
signal trap_illegal : bit;
signal trap_addr_error : bit;
signal trap_priv : bit;
@@ -221,6 +223,7 @@ architecture logic of TG68KdotC_Kernel is
signal trapd : bit;
signal trap_SR : std_logic_vector(7 downto 0);
signal make_trace : std_logic;
signal make_berr : std_logic;
signal set_stop : bit;
signal stop : bit;
@@ -726,7 +729,8 @@ PROCESS (clk, setdisp, memaddr_a, briefdata, memaddr_delta, setdispbyte, datatyp
IF rising_edge(clk) THEN
IF clkena_lw='1' THEN
trap_vector(31 downto 8) <= (others => '0');
IF trap_berr='1' THEN
-- IF trap_addr_fault='1' THEN
IF trap_berr='1' THEN
trap_vector(7 downto 0) <= X"08";
END IF;
IF trap_addr_error='1' THEN
@@ -844,7 +848,7 @@ PROCESS (clk, setdisp, memaddr_a, briefdata, memaddr_delta, setdispbyte, datatyp
-----------------------------------------------------------------------------
-- PC Calc + fetch opcode
-----------------------------------------------------------------------------
PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro_state, stop, make_trace, IPL_nr, FlagsSR, set_rot_cnt, opcode, writePCbig, set_exec, exec,
PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro_state, stop, make_trace, make_berr, IPL_nr, FlagsSR, set_rot_cnt, opcode, writePCbig, set_exec, exec,
PC_dataa, PC_datab, setnextpass, last_data_read, TG68_PC_brw, TG68_PC_word, Z_error, trap_trap, trap_trapv, interrupt, tmp_TG68_PC, TG68_PC)
BEGIN
@@ -889,7 +893,8 @@ PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro
setinterrupt <= '0';
IF setstate="00" AND next_micro_state=idle AND setnextpass='0' AND (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" AND set_exec(opcCHK)='0'THEN
setendOPC <= '1';
IF FlagsSR(2 downto 0)<IPL_nr OR IPL_nr="111" OR make_trace='1' THEN
-- IF FlagsSR(2 downto 0)<IPL_nr OR IPL_nr="111" OR make_trace='1' OR make_berr='1' THEN
IF FlagsSR(2 downto 0)<IPL_nr OR IPL_nr="111" OR make_trace='1' OR berr='1' THEN
setinterrupt <= '1';
ELSIF stop='0' THEN
setopcode <= '1';
@@ -918,6 +923,7 @@ PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro
byte <= '0';
-- IPL_nr <= "000";
trap_trace <= '0';
trap_berr <= '0';
writePCbig <= '0';
-- recall_last <= '0';
Suppress_Base <= '0';
@@ -947,12 +953,21 @@ PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro
exe_datatype <= set_datatype;
exe_opcode <= opcode;
-- make_berr <= berr OR make_berr;
stop <= set_stop OR (stop AND NOT setinterrupt);
IF setinterrupt='1' THEN
trap_interrupt <= '0';
trap_trace <= '0';
-- TG68_PC_word <= '0';
make_berr <= '0';
trap_berr <= '0';
IF make_trace='1' THEN
trap_trace <= '1';
-- ELSIF make_berr='1' THEN
ELSIF berr='1' THEN
trap_berr <= '1';
ELSE
rIPL_nr <= IPL_nr;
rIPL_nr <= IPL_nr;
IPL_vec <= "00011"&IPL_nr; -- TH
trap_interrupt <= '1';
END IF;
@@ -967,6 +982,7 @@ PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro
trap_interrupt <= '0';
trap_trace <= '0';
TG68_PC_word <= '0';
trap_berr <= '0';
ELSIF opcode(7 downto 0)="00000000" OR opcode(7 downto 0)="11111111" OR data_is_source='1' THEN
TG68_PC_word <= '1';
END IF;
@@ -1225,7 +1241,7 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
build_bcd, set_Z_error, trapd, movem_run, last_data_read, set, set_V_Flag, z_error, trap_trace, trap_interrupt,
SVmode, preSVmode, stop, long_done, ea_only, setstate, execOPC, exec_write_back, exe_datatype,
datatype, interrupt, c_out, trapmake, rot_cnt, brief, addr,
long_start, set_datatype, sndOPC, set_exec, exec, ea_build_now, reg_QA, reg_QB, berr)
long_start, set_datatype, sndOPC, set_exec, exec, ea_build_now, reg_QA, reg_QB, make_berr, trap_berr)
BEGIN
TG68_PC_brw <= '0';
setstate <= "00";
@@ -1253,7 +1269,6 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
ea_only <= '0';
set_direct_data <= '0';
set_exec_tas <= '0';
trap_berr <= '0'; -- TH
trap_illegal <='0';
trap_addr_error <= '0';
trap_priv <='0';
@@ -1272,8 +1287,13 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
next_micro_state <= idle;
build_logical <= '0';
build_bcd <= '0';
skipFetch <= '0';
build_bcd <= '0';
-- skipFetch <= make_berr; --TH
if (berr='1') then
skipFetch <= '1';
else
skipFetch <= '0';
end if;
set_writePCbig <= '0';
-- set_recall_last <= '0';
set_Suppress_Base <= '0';
@@ -1284,11 +1304,6 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
END IF;
set_datatype <= datatype;
IF berr='1' then -- TH
trap_berr <= '1'; -- TH
trapmake <= '1'; -- TH
END IF; -- TH
set <= (OTHERS=>'0');
set_exec <= (OTHERS=>'0');
set(update_ld) <= '0';
@@ -1313,6 +1328,13 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
END IF;
setstate <= "01";
END IF;
IF interrupt='1' AND trap_berr='1' THEN
next_micro_state <= trap0;
IF preSVmode='0' THEN
set(changeMode) <= '1';
END IF;
setstate <= "01";
END IF;
IF micro_state=int1 OR (interrupt='1' AND trap_trace='1') THEN
next_micro_state <= trap0;
-- IF cpu(0)='0' THEN
@@ -2847,7 +2869,7 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
-- set_datatype <= "10";
next_micro_state <= trap1;
ELSE
IF trap_interrupt='1' OR trap_trace='1' THEN
IF trap_interrupt='1' OR trap_trace='1' OR trap_berr='1' THEN
writePC <= '1';
END IF;
datatype <= "10";
@@ -2868,19 +2890,19 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
setstate <= "11";
datatype <= "01";
writeSR <= '1';
-- IF trap_berr='1' THEN -- TH
IF trap_vector = X"08" THEN -- TH
IF trap_berr='1' THEN
next_micro_state <= trap4;
ELSE
next_micro_state <= trap3;
END IF;
ELSE
next_micro_state <= trap3;
END IF;
WHEN trap3 => -- TRAP
set_vectoraddr <= '1';
datatype <= "10";
set(direct_delta) <= '1';
set(directPC) <= '1';
setstate <= "10";
next_micro_state <= nopnop;
setstate <= "10";
next_micro_state <= nopnop;
WHEN trap4 => -- TRAP
set(presub) <= '1';
setstackaddr <='1';

18
cores/mist/mist_top.v
View File

@@ -64,12 +64,15 @@ wire tg68_berr = (dtack_timeout == 5'd31); // || cpu_write_illegal;
// certain bus error
reg [3:0] berr_cnt_out;
reg [3:0] berr_cnt;
reg berrD;
always @(posedge clk_8) begin
berrD <= tg68_berr;
if(reset) begin
berr_cnt <= 4'd0;
end else begin
berr_cnt_out <= 4'd0;
if(tg68_berr) begin
if(tg68_berr && !berrD) begin
berr_cnt_out <= berr_cnt + 4'd1;
berr_cnt <= berr_cnt + 4'd1;
end
@@ -94,10 +97,15 @@ always @(posedge clk_8) begin
end else begin
// timeout only when cpu owns the bus and when
// neither dtack nor fast ram are active
if(!tg68_dtack || br || tg68_cpuena)
dtack_timeout <= 5'd0;
else if(dtack_timeout != 5'd31)
dtack_timeout <= dtack_timeout + 5'd1;
if(dtack_timeout != 5'd31) begin
if(!tg68_dtack || br || tg68_cpuena)
dtack_timeout <= 5'd0;
else
dtack_timeout <= dtack_timeout + 5'd1;
end else
// leave bus error when next instruction is read
if(!tg68_dtack && (tg68_cpustate[1:0] == 2'd3))
dtack_timeout <= 1'b0;
end
end

28
cores/mist/video.v
View File

@@ -42,11 +42,11 @@ module video (
output reg [15:0] reg_dout,
// screen interface
output hs, // H_SYNC
output vs, // V_SYNC
output [5:0] video_r, // Red[5:0]
output [5:0] video_g, // Green[5:0]
output [5:0] video_b, // Blue[5:0]
output reg hs, // H_SYNC
output reg vs, // V_SYNC
output reg [5:0] video_r, // Red[5:0]
output reg [5:0] video_g, // Green[5:0]
output reg [5:0] video_b, // Blue[5:0]
// system config
input pal56, // use VGA compatible 56hz for PAL
@@ -162,11 +162,14 @@ wire [9:0] vcnt = mono?vcnt_mono:vcnt_color;
wire bd = mono?1'b0:bd_color;
// monochome is 640x480 (hs & vs neg)
// color is 800x600 (hs & vs pos)
assign hs = mono?~hs_mono:hs_color;
assign vs = mono?~vs_mono:vs_color;
wire hmax = mono?hmax_mono:hmax_color;
wire vmax = mono?vmax_mono:vmax_color;
always @(posedge clk) begin
hs <= mono?~hs_mono:hs_color;
vs <= mono?~vs_mono:vs_color;
end
reg [15:0] tx, tx0, tx1, tx2, tx3; // output shift registers
localparam BASE_ADDR = 23'h8000; // default video base address 0x010000
@@ -290,10 +293,15 @@ wire [2:0] stvid_g = mono?mono_rgb:color_g;
wire [2:0] stvid_b = mono?mono_rgb:color_b;
// ... add OSD overlay and feed into VGA outputs
assign video_r = !osd_oe?{stvid_r,stvid_r}:{osd_pixel, osd_pixel, osd_pixel, stvid_r};
assign video_g = !osd_oe?{stvid_g,stvid_g}:{osd_pixel, osd_pixel, 1'b1, stvid_g};
assign video_b = !osd_oe?{stvid_b,stvid_b}:{osd_pixel, osd_pixel, osd_pixel, stvid_b};
//assign video_r = !osd_oe?{stvid_r,stvid_r}:{osd_pixel, osd_pixel, osd_pixel, stvid_r};
//assign video_g = !osd_oe?{stvid_g,stvid_g}:{osd_pixel, osd_pixel, 1'b1, stvid_g};
//assign video_b = !osd_oe?{stvid_b,stvid_b}:{osd_pixel, osd_pixel, osd_pixel, stvid_b};
always @(posedge clk) begin
video_r <= !osd_oe?{stvid_r,stvid_r}:{osd_pixel, osd_pixel, osd_pixel, stvid_r};
video_g <= !osd_oe?{stvid_g,stvid_g}:{osd_pixel, osd_pixel, 1'b1, stvid_g};
video_b <= !osd_oe?{stvid_b,stvid_b}:{osd_pixel, osd_pixel, osd_pixel, stvid_b};
end
// display enable signal
// the color modes use a scan doubler and output the data with 2 lines delay