mirror of
https://github.com/mist-devel/mist-board.git
synced 2026-01-27 12:21:44 +00:00
Started blitter implementation
This commit is contained in:
harbaum
@@ -116,7 +116,8 @@ always @(posedge clk) begin
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readPout <= readPout + 4'd1;
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end
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always @(sel, ds, rw, addr, ikbd_rx_data_available, ikbd_rx_data, midi_rx_data_available, midi_tx_empty) begin
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always @(sel, ds, rw, addr, ikbd_rx_data_available, ikbd_rx_data, ikbd_irq,
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midi_rx_data, midi_rx_data_available, midi_tx_empty, midi_irq) begin
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dout = 8'h00;
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if(sel && ~ds && rw) begin
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324
cores/mist/blitter.v
Normal file
324
cores/mist/blitter.v
Normal file
@@ -0,0 +1,324 @@
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// blitter docs:
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module blitter (
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input clk32, // 31.875 MHz
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input [3:0] bus_cycle,
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// cpu register interface
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input clk,
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input reset,
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input sel,
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input [4:0] addr,
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input [15:0] din,
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output reg [15:0] dout,
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input uds,
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input lds,
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input rw,
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output irq
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);
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assign irq = 1'b0;
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// CPU controlled register set
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reg [15:0] halftone_ram[15:0];
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reg [15:1] src_x_inc;
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reg [15:1] src_y_inc;
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reg [23:1] src_addr;
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reg [15:0] endmask1;
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reg [15:0] endmask2;
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reg [15:0] endmask3;
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reg [15:1] dst_x_inc;
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reg [15:1] dst_y_inc;
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reg [23:1] dst_addr;
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reg [15:0] x_count;
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reg [15:0] x_count_latch;
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reg [15:0] y_count;
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reg [1:0] hop;
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reg [3:0] op;
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reg [3:0] line_number;
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reg smudge;
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reg hog;
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reg busy;
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reg [3:0] skew;
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reg nfsr;
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reg fxsr;
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// ------------------ cpu interface --------------------
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// CPU READ
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always @(sel, rw, addr, src_y_inc, src_x_inc, src_addr, endmask1, endmask2, endmask3,
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dst_x_inc, dst_y_inc, dst_addr, x_count, y_count, hop, op, busy, hog,
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smudge, line_number, fxsr, nfsr, skew) begin
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dout = 16'h0000;
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if(sel && rw) begin
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if((addr >= 5'h00) && (addr <= 5'h0f)) dout <= halftone_ram[addr];
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if(addr == 5'h10) dout <= { src_x_inc, 1'b0 };
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if(addr == 5'h11) dout <= { src_y_inc, 1'b0 };
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if(addr == 5'h12) dout <= { 8'h00, src_addr[23:16] };
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if(addr == 5'h13) dout <= { src_addr [15:1], 1'b0 };
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if(addr == 5'h14) dout <= endmask1;
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if(addr == 5'h15) dout <= endmask2;
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if(addr == 5'h16) dout <= endmask3;
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if(addr == 5'h17) dout <= { dst_x_inc, 1'b0 };
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if(addr == 5'h18) dout <= { dst_y_inc, 1'b0 };
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if(addr == 5'h19) dout <= { 8'h00, dst_addr[23:16] };
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if(addr == 5'h1a) dout <= { dst_addr [15:1], 1'b0 };
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if(addr == 5'h1b) dout <= x_count;
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if(addr == 5'h1c) dout <= y_count;
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// since reading them has not side effect we can return the 8 bit registers
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// without caring for uds/lds
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if(addr == 5'h1d) dout <= { 6'b000000, hop, 4'b0000, op };
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if(addr == 5'h1e) dout <= { busy, hog, smudge, 1'b0, line_number, fxsr, nfsr, 2'b00, skew };
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end
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end
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// CPU WRITE
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always @(negedge clk) begin
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if(reset) begin
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end else begin
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if(sel && ~rw) begin
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// ------ 16/32 bit registers, not byte adressable ----------
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if((addr >= 5'h00) && (addr <= 5'h0f)) halftone_ram[addr] <= din;
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if(addr == 5'h10) src_x_inc <= din[15:1];
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if(addr == 5'h11) src_y_inc <= din[15:1];
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if(addr == 5'h12) src_addr [23:16]<= din[7:0];
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if(addr == 5'h13) src_addr [15:1]<= din[15:1];
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if(addr == 5'h14) endmask1 <= din;
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if(addr == 5'h15) endmask2 <= din;
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if(addr == 5'h16) endmask3 <= din;
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if(addr == 5'h17) dst_x_inc <= din[15:1];
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if(addr == 5'h18) dst_y_inc <= din[15:1];
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if(addr == 5'h19) dst_addr [23:16]<= din[7:0];
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if(addr == 5'h1a) dst_addr [15:1]<= din[15:1];
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if(addr == 5'h1b) begin
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x_count <= din;
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x_count_latch <= din; // x_count is latched to be reloaded at each end of line
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end
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if(addr == 5'h1c) y_count <= din;
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// ------ 8 bit registers ----------
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// uds -> even bytes via d15:d8
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// lds -> odd bytes via d7:d0
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if(addr == 5'h1d && ~uds) hop <= din[9:8];
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if(addr == 5'h1d && ~lds) op <= din[3:0];
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if(addr == 5'h1e && ~uds) begin
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line_number <= din[11:8];
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smudge <= din[13];
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hog <= din[14];
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busy <= din[15];
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// writing busy with 1 starts the blitter
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end
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if(addr == 5'h1e && ~lds) begin
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skew <= din[3:0];
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nfsr <= din[6];
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fxsr <= din[7];
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end
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end
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end
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end
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// ----------------- blitter engine -------------------
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always @(posedge clk32) begin
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if(reset) begin
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end else begin
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end
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end
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// wire io = (bus_cycle[3:2] == 0); // blitter does io in cycle 0 which is the same one the cpu uses
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// TODO: Also use bus cycle 2 to make a "turbo blitter" being twice as fast
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// internal registers
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reg [31:0] src; // 32 bit source read buffer
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reg [15:0] dest; // 16 bit destination read buffer
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// ------- wire up the blitter subcomponent combinatorics --------
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wire [15:0] src_skewed;
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wire [15:0] src_halftoned;
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wire [15:0] result;
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// select current halftone line
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wire [15:0] halftone_line = halftone_ram[line_number];
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// shift/select 16 bits of source
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shift shift (
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.skew (skew),
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.in (src),
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.out (src_skewed)
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);
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// apply halftone operation
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halftone_op halftone_op (
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.op (hop),
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.in0 (halftone_line),
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.in1 (src_skewed),
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.out (src_halftoned)
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);
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// apply blitter operation
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blitter_op blitter_op (
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.op (op),
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.in0 (src_halftoned),
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.in1 (dest),
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.out (result)
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);
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wire first_word_in_row = (x_count == x_count_latch);
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wire last_word_in_row = (x_count == 16'h0001);
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wire [15:0] data_to_write;
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// apply masks
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masking masking (
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.endmask1 (endmask1),
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.endmask2 (endmask2),
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.endmask3 (endmask3),
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.first (first_word_in_row),
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.last (last_word_in_row),
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.in0 (result),
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.in1 (dest),
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.out (data_to_write)
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);
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endmodule // blitter
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// the blitter operations
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module blitter_op (
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input [3:0] op,
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input [15:0] in0,
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input [15:0] in1,
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output reg [15:0] out
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);
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always @(op, in0, in1) begin
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case(op)
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0: out = 8'h00;
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1: out = in0 & in1;
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2: out = in0 & ~in1;
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3: out = in0;
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4: out = ~in0 & in1;
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5: out = in1;
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6: out = in0 ^ in1;
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7: out = in0 | in1;
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8: out = ~in0 & ~in1;
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9: out = ~in0 ^ in1;
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10: out = ~in1;
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11: out = in0 | ~in1;
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12: out = ~in0;
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13: out = ~in0 | in1;
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14: out = ~in0 | ~in1;
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15: out = 8'hff;
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endcase; // case (op)
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end
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endmodule // blitter_op
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// the blitter barrel shifter
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module shift (
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input [3:0] skew,
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input [31:0] in,
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output reg [15:0] out
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);
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always @(skew, in) begin
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out = 16'h00;
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// out = in[skew+15:skew];
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case(skew)
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0: out = in[15:0];
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1: out = in[16:1];
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2: out = in[17:2];
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3: out = in[18:3];
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4: out = in[19:4];
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5: out = in[20:5];
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6: out = in[21:6];
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7: out = in[22:7];
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8: out = in[23:8];
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9: out = in[24:9];
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10: out = in[25:10];
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11: out = in[26:11];
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12: out = in[27:12];
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13: out = in[28:13];
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14: out = in[29:14];
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15: out = in[30:15];
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endcase; // case (skew)
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end
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endmodule // shift
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// the halftone operations
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module halftone_op (
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input [1:0] op,
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input [15:0] in0,
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input [15:0] in1,
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output reg [15:0] out
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);
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always @(op, in0, in1) begin
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case(op)
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0: out = 8'hff;
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1: out = in0;
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2: out = in1;
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3: out = in0 & in1;
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endcase; // case (op)
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end
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endmodule // halftone_op
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// masking
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module masking (
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input [15:0] endmask1,
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input [15:0] endmask2,
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input [15:0] endmask3,
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input first,
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input last,
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input [15:0] in0,
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input [15:0] in1,
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output reg [15:0] out
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);
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always @(endmask1, endmask2, endmask3, first, last, in0, in1) begin
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// neither first nor last: endmask2
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out = (in0 & endmask2) | (in1 & ~endmask2);
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// first (last may also be applied): endmask1
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if(first) out = (in0 & endmask1) | (in1 & ~endmask1);
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// last and not first: endmask3
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else if(last) out = (in0 & endmask3) | (in1 & ~endmask3);
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end
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endmodule // masking
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@@ -30,7 +30,7 @@ module dma (
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// ------------- data_io (arm controller) interface ------
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always @(dio_idx, base, scnt, fdc_cmd, fdc_track, fdc_sector,
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fdc_data, drv_sel, drv_side, fdc_busy) begin
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fdc_data, drv_sel, drv_side, fdc_busy, acsi_busy, acsi_target, acsi_cmd) begin
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dio_data = 8'h00;
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case (dio_idx)
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@@ -203,7 +203,9 @@ assign gpip_cpu_out = (gpip_in & ~ddr) | (gpip & ddr);
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// cpu read interface
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always @(iack, sel, ds, rw, addr, gpip_cpu_out, aer, ddr, ier, ipr, isr, imr,
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vr, irq_vec) begin
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vr, irq_vec, serial_data_out_fifo_full, timera_dat_o, timerb_dat_o,
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timerc_dat_o, timerd_dat_o, timera_ctrl_o, timerb_ctrl_o, timerc_ctrl_o,
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timerd_ctrl_o) begin
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dout = 8'd0;
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if(sel && ~ds && rw) begin
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@@ -464,6 +464,7 @@ set_global_assignment -name VERILOG_FILE mfp_timer.v
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set_global_assignment -name VHDL_FILE vol_table_array.vhd
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set_global_assignment -name VHDL_FILE YM2149_volmix.vhd
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set_global_assignment -name VERILOG_FILE acia.v
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set_global_assignment -name VERILOG_FILE blitter.v
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set_global_assignment -name VHDL_FILE TG68K.vhd
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set_global_assignment -name VHDL_FILE TG68K_ALU.vhd
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set_global_assignment -name VHDL_FILE TG68K_Pack.vhd
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@@ -52,7 +52,7 @@ wire [1:0] buttons;
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// generate dtack for all implemented peripherals
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wire io_dtack = vreg_sel || mmu_sel || mfp_sel || mfp_iack ||
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acia_sel || psg_sel || dma_sel || auto_iack;
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acia_sel || psg_sel || dma_sel || auto_iack || blitter_sel;
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// the original tg68k did not contain working support for bus fault exceptions. While earlier
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// TOS versions cope with that, TOS versions with blitter support need this to work as this is
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@@ -160,6 +160,11 @@ wire [7:0] mfp_data_out;
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wire acia_sel = io_sel && ({tg68_adr[15:8], 8'd0} == 16'hfc00);
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wire [7:0] acia_data_out;
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// blitter 16 bit interface at $ff8a00 - $ff8a3f
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// wire blitter_sel = io_sel && ({tg68_adr[15:8], 8'd0} == 16'h8a00);
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wire blitter_sel = 1'b0;
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wire [15:0] blitter_data_out;
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// psg 8 bit interface at $ff8800 - $ff8803
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wire psg_sel = io_sel && ({tg68_adr[15:8], 8'd0} == 16'h8800);
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wire [7:0] psg_data_out;
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@@ -171,7 +176,7 @@ wire [15:0] dma_data_out;
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// de-multiplex the various io data output ports into one
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wire [7:0] io_data_out_8u = acia_data_out | psg_data_out;
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wire [7:0] io_data_out_8l = mmu_data_out | mfp_data_out | auto_vector;
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wire [15:0] io_data_out = vreg_data_out | dma_data_out |
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wire [15:0] io_data_out = vreg_data_out | dma_data_out | blitter_data_out |
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{8'h00, io_data_out_8l} | {io_data_out_8u, 8'h00};
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wire init = ~pll_locked;
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@@ -276,6 +281,20 @@ acia acia (
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.ikbd_data_in (ikbd_data_to_acia)
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);
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blitter blitter (
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// cpu interface
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.clk (clk_8 ),
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.reset (reset ),
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.din (tg68_dat_out ),
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.sel (blitter_sel ),
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.addr (tg68_adr[5:1] ),
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.uds (tg68_uds ),
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.lds (tg68_uds ),
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.rw (tg68_rw ),
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.dout (blitter_data_out ),
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.irq ( )
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);
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//// ym2149 sound chip ////
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reg [1:0] sclk;
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@@ -11,7 +11,7 @@ module mmu (
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reg [7:0] memconfig;
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always @(sel, ds, rw) begin
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always @(sel, ds, rw, memconfig) begin
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dout = 8'd0;
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if(sel && ~ds && rw)
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dout = memconfig;
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@@ -199,7 +199,7 @@ reg [2:0] palette_r[15:0];
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reg [2:0] palette_g[15:0];
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reg [2:0] palette_b[15:0];
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always @(reg_sel, reg_rw, reg_uds, reg_lds, reg_addr, _v_bas_ad, shmode, vaddr) begin
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always @(reg_sel, reg_rw, reg_uds, reg_lds, reg_addr, _v_bas_ad, shmode, vaddr, syncmode) begin
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reg_dout = 16'h0000;
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// read registers
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