[BBC] Scanlines

cores/bbc/fpga/mist/bbc_mist_top.v

@@ -42,14 +42,17 @@ module bbc_mist_top(
   input          CONF_DATA0  // SPI_SS for user_io
 );
 
+assign LED = 1'b0;
+
 // the configuration string is returned to the io controller to allow
 // it to control the menu on the OSD 
 parameter CONF_STR = {
         "BBC;ROM;",
-        "T1,Reset;"
+        "O1,Scanlines,Off,On;",
+        "T2,Reset;"
 };
 
-parameter CONF_STR_LEN = 8+9;
+parameter CONF_STR_LEN = 8+20+9;
 
 // generated clocks
 wire clk_32m /* synthesis keep */ ;
@@ -66,8 +69,7 @@ wire [14:0] vid_adr;
 wire [7:0]  vid_data;
 
 wire [15:0] mem_adr;
-assign LED = (mem_romsel == 0) || (loader_addr == 0) || (loader_data == 0) || loader_we;
-wire [3:0]  mem_romsel /* synthesis keep */;
+wire [3:0]  mem_romsel;
 
 wire [7:0]  mem_di;
 wire [7:0]  rom_do;
@@ -193,7 +195,7 @@ wire sd_sdo = user_via_cb2_in;
 assign user_via_cb1_in = user_via_pb_out[1];
 
 sd_card sd_card (
-        // connection to io controller
+   // connection to io controller
    .io_lba (sd_lba ),
    .io_rd  (sd_rd),
    .io_wr  (sd_wr),
@@ -215,12 +217,10 @@ sd_card sd_card (
 );
 
 // data loading 
-wire 			loader_active 	/* synthesis keep */ ;
-wire 			loader_we 		/* synthesis keep */ ;
-wire [24:0]	loader_addr 	/* synthesis keep */ ;
-wire [7:0]	loader_data 	/* synthesis keep */ ;
-
-// http://beebwiki.mdfs.net/index.php/Paged_ROM
+wire 			loader_active;
+wire 			loader_we;
+wire [24:0]	loader_addr;
+wire [7:0]	loader_data;
 	 
 data_io DATA_IO  (
 	.sck				( SPI_SCK 			),
@@ -244,7 +244,7 @@ wire user_via_cb2_in;
 // the bbc is being reset of the pll isn't stable, if the ram isn't ready,
 // of the arm boots or if the user selects reset from the osd or of the user
 // presses the "core" button or the io controller uploads a rom
-wire reset_in = ~pll_ready || ~sdram_ready || status[0] || status[1] ||
+wire reset_in = ~pll_ready || ~sdram_ready || status[0] || status[2] ||
 		buttons[1] || loader_active;
 
 // synchronize reset with memory state machine
@@ -375,12 +375,16 @@ audio	AUDIO	(
 );
 
 wire sd_hs, sd_vs;
-wire sd_r, sd_g, sd_b;
+wire [1:0] sd_r;
+wire [1:0] sd_g;
+wire [1:0] sd_b;
 
 scandoubler SCANDOUBLE(
 
 	.clk_16		( clk_32m		),
 	.clk_16_en	( core_clken	),
+
+	.scanlines  ( status[1]    ),
 	
 	.vs_in		( core_vs		),
 	.hs_in		( core_hs		),
@@ -400,9 +404,9 @@ scandoubler SCANDOUBLE(
 );
 
 // switch between doubled and non-doubled video 
-wire video_r = scandoubler_disable?core_r:sd_r;
-wire video_g = scandoubler_disable?core_g:sd_g;
-wire video_b = scandoubler_disable?core_b:sd_b;
+wire [1:0] video_r = scandoubler_disable?core_r:sd_r;
+wire [1:0] video_g = scandoubler_disable?core_g:sd_g;
+wire [1:0] video_b = scandoubler_disable?core_b:sd_b;
 wire video_hs = scandoubler_disable?core_hs:sd_hs;
 wire video_vs = scandoubler_disable?core_vs:sd_vs;
 

cores/bbc/fpga/mist/osd.v

@@ -34,9 +34,9 @@ module osd (
 	input         sdi,
 
 	// VGA signals coming from core
-	input   	    red_in,
-	input   	    green_in,
-	input   	    blue_in,
+	input   	    [1:0] red_in,
+	input   	    [1:0] green_in,
+	input   	    [1:0] blue_in,
 	input			hs_in,
 	input			vs_in,
 	
@@ -194,9 +194,9 @@ always @(posedge pclk)
   osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt}];
 
 wire [2:0] osd_color = OSD_COLOR;
-assign red_out   = !osd_de? {6{red_in}}     :  {osd_pixel, osd_pixel, osd_color[2], {3{red_in}}  };
-assign green_out = !osd_de? {6{green_in}}   :  {osd_pixel, osd_pixel, osd_color[1], {3{green_in}} };
-assign blue_out  = !osd_de? {6{blue_in}}    :  {osd_pixel, osd_pixel, osd_color[0], {3{blue_in}} };
+assign red_out   = !osd_de? {3{red_in}}     :  {osd_pixel, osd_pixel, osd_color[2], {red_in, red_in[1]}  };
+assign green_out = !osd_de? {3{green_in}}   :  {osd_pixel, osd_pixel, osd_color[1], {green_in, green_in[1]} };
+assign blue_out  = !osd_de? {3{blue_in}}    :  {osd_pixel, osd_pixel, osd_color[0], {blue_in, blue_in[1]} };
 
 assign hs_out = hs_in;
 assign vs_out = vs_in;

cores/bbc/fpga/rtl/scandoubler.v

@@ -23,20 +23,21 @@ module scandoubler (
   input 	   clk,     // 31.875 MHz
   input        clk_16,  // from shifter
   input		   clk_16_en,
+  input        scanlines,
   
   // shifter video interface
   input 	   hs_in,
   input 	   vs_in,
-  input  	   r_in,
-  input  	   g_in,
-  input  	   b_in,
+  input  	r_in,
+  input  	g_in,
+  input  	b_in,
 
   // output interface
-  output reg 	   hs_out,
+  output reg      hs_out,
   output reg 	   vs_out,
-  output reg  		r_out,
-  output reg  		g_out,
-  output reg  		b_out,
+  output reg [1:0] r_out,
+  output reg [1:0] g_out,
+  output reg [1:0] b_out,
 
   output 	   is15k
 );
@@ -61,9 +62,15 @@ always @(posedge clk) begin
          scanline <= !scanline;
 
     // if no scanlines or not a scanline
-    r_out <= sd_out[2];
-    g_out <= sd_out[1];
-    b_out <= sd_out[0];
+	 if(!scanlines || !scanline) begin
+		r_out <= { sd_out[2], sd_out[2] };
+		g_out <= { sd_out[1], sd_out[1] };
+		b_out <= { sd_out[0], sd_out[0] };
+	end else begin
+		r_out <= { 1'b0, sd_out[2] };
+		g_out <= { 1'b0, sd_out[1] };
+		b_out <= { 1'b0, sd_out[0] };
+	end
 end