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Code Issues Releases Wiki Activity

[PLUS TOO] Stability improvements and keyboard support

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This commit is contained in:
Till Harbaum
2015-10-16 15:04:08 +02:00
parent 0952d647e9
commit fe07cfe86b
11 changed files with 1346 additions and 333 deletions
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36
cores/plus_too/addrController_top.v
View File

@@ -56,13 +56,16 @@ module addrController_top(
always @(posedge clk8) begin
busCycle <= busCycle + 1'b1;
end
// video controls memory bus during the first clock of the four-clock cycle
assign videoBusControl = busCycle == 2'b00;
assign videoBusControl = (busCycle == 2'b00);
// cpu controls memory bus during the third clock of the four-clock cycle
wire cpuBusControl = (busCycle == 2'b10);
// DTACK generation
// TODO: delay DTACK for once full bus cycle when RAM is accessed, to match Mac Plus memory timing
// TODO: according to datasheet, /DTACK should continue to be asserted through the final bus cycle too
assign _cpuDTACK = ~(_cpuAS == 1'b0 && busCycle == 2'b10 && videoBusControl == 1'b0);
assign _cpuDTACK = ~(_cpuAS == 1'b0 && cpuBusControl);
// interconnects
wire selectRAM, selectROM;
@@ -70,12 +73,12 @@ module addrController_top(
// RAM/ROM control signals
wire videoControlActive = _hblank == 1'b1 || loadSound;
assign _romCS = ~((videoBusControl == 1'b1 && videoControlActive == 1'b0) || (videoBusControl == 1'b0 && selectROM == 1'b1));
assign _romOE = ~((videoBusControl == 1'b1 && videoControlActive == 1'b0) || (videoBusControl == 1'b0 && selectROM == 1'b1 && _cpuRW == 1'b1));
assign _romCS = ~((videoBusControl && videoControlActive == 1'b0) || (cpuBusControl && selectROM == 1'b1));
assign _romOE = ~((videoBusControl && videoControlActive == 1'b0) || (cpuBusControl && selectROM == 1'b1 && _cpuRW == 1'b1));
assign _romWE = 1'b1;
assign _ramCS = ~((videoBusControl == 1'b1 && videoControlActive == 1'b1) || (videoBusControl == 1'b0 && selectRAM == 1'b1));
assign _ramOE = ~((videoBusControl == 1'b1 && videoControlActive == 1'b1) || (videoBusControl == 1'b0 && selectRAM == 1'b1 && _cpuRW == 1'b1));
assign _ramWE = ~(videoBusControl == 1'b0 && selectRAM && _cpuRW == 1'b0);
assign _ramCS = ~((videoBusControl && videoControlActive == 1'b1) || (cpuBusControl && selectRAM == 1'b1));
assign _ramOE = ~((videoBusControl && videoControlActive == 1'b1) || (cpuBusControl && selectRAM == 1'b1 && _cpuRW == 1'b1));
assign _ramWE = ~(cpuBusControl && selectRAM && _cpuRW == 1'b0);
assign _memoryUDS = videoBusControl ? 1'b0 : _cpuUDS;
assign _memoryLDS = videoBusControl ? 1'b0 : _cpuLDS;
wire [21:0] addrMux = videoBusControl ? videoAddr : cpuAddr[21:0];
@@ -104,9 +107,11 @@ module addrController_top(
assign extraRomReadAck = videoBusControl == 1'b1 && videoControlActive == 1'b0;
assign memoryAddr = videoBusControl == 1'b1 && videoControlActive == 1'b0 ? extraRomReadAddr : macAddr;
// address decoding
wire selectSCCByAddress;
wire selectIWMByAddress;
wire selectVIAByAddress;
addrDecoder ad(
.address(cpuAddr),
.enable(!videoBusControl),
@@ -115,11 +120,13 @@ module addrController_top(
.selectRAM(selectRAM),
.selectROM(selectROM),
.selectSCC(selectSCCByAddress),
.selectIWM(selectIWM),
.selectVIA(selectVIA),
.selectIWM(selectIWMByAddress),
.selectVIA(selectVIAByAddress),
.selectInterruptVectors(selectInterruptVectors));
/* SCC register access is a mess. Reads and writes can have side-effects that alter the meaning of subsequent reads
/* TH: The following isn't 100% true anymore but kept for now for documentation purposes ...
SCC register access is a mess. Reads and writes can have side-effects that alter the meaning of subsequent reads
and writes to the same address. It's not safe to do multiple reads of the same address, or multiple writes of the
same value to the same address. So we need to be sure we only perform one read or write per 4-clock CPU bus cycle.
@@ -142,8 +149,9 @@ module addrController_top(
Another solution would be to create a custom clock for the SCC, whose positive edge is the negative edge of
clock 3 of the bus cycle.
*/
assign selectSCC = selectSCCByAddress && (busCycle == 2'b10 || // reads and writes enable on clock 2
(_cpuRW == 1'b1 && busCycle == 2'b11 && clk8)); // reads enable on first half of clock 3
assign selectSCC = selectSCCByAddress && cpuBusControl;
assign selectIWM = selectIWMByAddress && cpuBusControl;
assign selectVIA = selectVIAByAddress && cpuBusControl;
// video
videoTimer vt(

30
cores/plus_too/dataController_top.v
View File

@@ -38,8 +38,8 @@ module dataController_top(
input keyData, // need pull-up
// mouse:
inout mouseClk, // need pull-up
inout mouseData, // need pull-up
input mouseClk, // need pull-up
input mouseData, // need pull-up
// serial:
input serialIn, // need pull-up
@@ -141,8 +141,12 @@ module dataController_top(
._irq(_viaIrq),
.dataOut(viaDataOut),
.memoryOverlayOn(memoryOverlayOn),
.SEL(SEL));
.SEL(SEL),
.kbd_in_data(kbd_in_data),
.kbd_in_strobe(kbd_in_strobe),
.kbd_out_data(kbd_out_data),
.kbd_out_strobe(kbd_out_strobe)
);
// IWM
iwm i(
.clk8(clk8),
@@ -166,7 +170,7 @@ module dataController_top(
.sysclk(clk8),
.reset_hw(~_cpuReset),
.cs(selectSCC && (_cpuLDS == 1'b0 || _cpuUDS == 1'b0)),
.we(~_cpuRW),
.we(!_cpuRW),
.rs(cpuAddrRegLo),
.wdata(cpuDataIn[15:8]),
.rdata(sccDataOut),
@@ -202,4 +206,20 @@ module dataController_top(
.y2(mouseY2),
.button(mouseButton));
wire [7:0] kbd_in_data;
wire kbd_in_strobe;
wire [7:0] kbd_out_data;
wire kbd_out_strobe;
// Keyboard
ps2_kbd kbd(
.sysclk(clk8),
.reset(~_cpuReset),
.ps2dat(keyData),
.ps2clk(keyClk),
.data_out(kbd_out_data), // data from mac
.strobe_out(kbd_out_strobe),
.data_in(kbd_in_data), // data to mac
.strobe_in(kbd_in_strobe));
endmodule

29
cores/plus_too/iwm.v
View File

@@ -90,6 +90,7 @@ module iwm(
.extraRomReadAddr(extraRomReadAddr),
.extraRomReadAck(extraRomReadAck),
.extraRomReadData(extraRomReadData));
floppy floppyExt(
.clk8(clk8),
._reset(_reset),
@@ -173,7 +174,7 @@ module iwm(
end
// update IWM bit registers
always @(posedge clk8 or negedge _reset) begin
always @(negedge clk8 or negedge _reset) begin
if (_reset == 1'b0) begin
ca0 <= 0;
ca1 <= 0;
@@ -202,23 +203,21 @@ module iwm(
always @(*) begin
dataOutLo = 8'hEF;
if (_cpuRW == 1'b1 && selectIWM == 1'b1 && _cpuLDS == 1'b0) begin
// reading any IWM address returns state as selected by Q7 and Q6
case ({q7Next,q6Next})
2'b00: // data-in register (from disk drive) - MSB is 1 when data is valid
dataOutLo <= readDataLatch;
2'b01: // IWM status register - read only
dataOutLo <= { (selectExternalDriveNext ? senseExt : senseInt), 1'b0, diskEnableExt & diskEnableInt, iwmMode };
2'b10: // handshake - read only
dataOutLo <= { _iwmBusy, _writeUnderrun, 6'b000000 };
2'b11: // IWM mode register when not enabled (write-only), or (write?) data register when enabled
dataOutLo <= 0;
endcase
end
// reading any IWM address returns state as selected by Q7 and Q6
case ({q7Next,q6Next})
2'b00: // data-in register (from disk drive) - MSB is 1 when data is valid
dataOutLo <= readDataLatch;
2'b01: // IWM status register - read only
dataOutLo <= { (selectExternalDriveNext ? senseExt : senseInt), 1'b0, diskEnableExt & diskEnableInt, iwmMode };
2'b10: // handshake - read only
dataOutLo <= { _iwmBusy, _writeUnderrun, 6'b000000 };
2'b11: // IWM mode register when not enabled (write-only), or (write?) data register when enabled
dataOutLo <= 0;
endcase
end
// write IWM state
always @(posedge clk8 or negedge _reset) begin
always @(negedge clk8 or negedge _reset) begin
if (_reset == 1'b0) begin
iwmMode <= 0;
writeData <= 0;

4
cores/plus_too/pll.qip Normal file
View File

@@ -0,0 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

503
cores/plus_too/clock325MHz_bb.v → cores/plus_too/pll.v
View File

@@ -1,194 +1,309 @@
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clock325MHz.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module clock325MHz (
inclk0,
c0);
input inclk0;
output c0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "20"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.500000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "13"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clock325MHz.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "20"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "13"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clock325MHz.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock325MHz.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock325MHz.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock325MHz.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock325MHz.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock325MHz_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock325MHz_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0,
locked);
input inclk0;
output c0;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 27,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 65,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "65.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "65.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "65"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

4
cores/plus_too/plusToo_top.qsf
View File

@@ -337,6 +337,7 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_R
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to UART_RX
set_global_assignment -name VERILOG_FILE ps2_kbd.v
set_global_assignment -name VHDL_FILE TG68K_Pack.vhd
set_global_assignment -name VHDL_FILE TG68KdotC_Kernel.vhd
set_global_assignment -name VHDL_FILE TG68K_ALU.vhd
@@ -358,10 +359,9 @@ set_global_assignment -name VERILOG_FILE dataController_top.v
set_global_assignment -name VERILOG_FILE videoTimer.v
set_global_assignment -name VERILOG_FILE videoShifter.v
set_global_assignment -name VERILOG_FILE plusToo_top.v
set_global_assignment -name QIP_FILE clock325MHz.qip
set_global_assignment -name VERILOG_FILE debugPanel.v
set_global_assignment -name VERILOG_FILE fontGen.v
set_global_assignment -name VERILOG_FILE romAdapter.v
set_global_assignment -name VERILOG_FILE floppy.v
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_global_assignment -name QIP_FILE pll.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

40
cores/plus_too/plusToo_top.v
View File

@@ -39,6 +39,16 @@ module plusToo_top(
input wire CONF_DATA0 // SPI_SS for user_io
);
// ------------------------------ Plus Too Bus Timing ---------------------------------
// for stability and maintainability reasons the whole timing has been simplyfied:
// 00 01 10 11
// ______ _____________ _____________ _____________ _____________ ___
// ______X_video_cycle_X____unused___X__cpu_cycle__X___unused____X___
// ^ ^ ^
// | | |
// video cpu cpu
// read write read
// include the OSD into the video data path
osd #(10,0,2) osd (
.pclk ( clk32 ),
@@ -114,20 +124,26 @@ wire [7:0] ledg;
// ps2 interface for mouse, to be mapped into user_io
wire mouseClk;
wire mouseData;
wire keyClk;
wire keyData;
// NO REAL LOGIC SHOULD GO IN THIS MODULE!
// It may not exist in the hand-built Plus Too.
// Only interconnections and interfaces specific to the dev board should go here
assign SDRAM_CLK = !clk64;
// synthesize a 32.5 MHz clock
wire clk32;
wire clk128;
wire clk64;
wire pll_locked;
clock325MHz cs0(
reg clk32;
always @(posedge clk64)
clk32 <= !clk32;
pll cs0(
.inclk0 ( CLOCK_27[0] ),
.c0 ( clk32 ),
.c1 ( clk128 ),
.c2 ( SDRAM_CLK ),
.c0 ( clk64 ),
.locked ( pll_locked )
);
@@ -138,16 +154,14 @@ wire mouseData;
ps2_clk_div <= ps2_clk_div + 9'd1;
// set the real-world inputs to sane defaults
localparam keyClk = 1'b0,
keyData = 1'b0,
serialIn = 1'b0,
localparam serialIn = 1'b0,
interruptButton = 1'b0,
configROMSize = 1'b1, // 128K ROM
configRAMSize = 2'b01; // 512K RAM
// interconnects
// CPU
wire clk8, _cpuReset, _cpuAS, _cpuUDS, _cpuLDS, _cpuRW, _cpuDTACK, cpuDriveData;
wire clk8, _cpuReset, _cpuAS, _cpuUDS, _cpuLDS, _cpuRW, _cpuDTACK;
wire [2:0] _cpuIPL;
wire [7:0] cpuAddrHi;
wire [23:0] cpuAddr;
@@ -217,8 +231,8 @@ wire mouseData;
// ps2 interface
.ps2_clk ( ps2_clk ),
.ps2_kbd_clk ( ),
.ps2_kbd_data ( ),
.ps2_kbd_clk ( keyClk ),
.ps2_kbd_data ( keyData ),
.ps2_mouse_clk ( mouseClk ),
.ps2_mouse_data( mouseData )
);
@@ -425,7 +439,7 @@ sdram sdram (
.sd_cas ( SDRAM_nCAS ),
// system interface
.clk_128 ( clk128 ),
.clk_64 ( clk64 ),
.clk_8 ( clk8 ),
.init ( !pll_locked ),

800
cores/plus_too/ps2_kbd.v Normal file
View File

@@ -0,0 +1,800 @@
`timescale 1ns / 100ps
/*
* PS2 Keyboard to Mac interface module
*/
module ps2_kbd( input sysclk,
input reset,
inout ps2dat,
inout ps2clk,
input [7:0] data_out,
input strobe_out,
output [7:0] data_in,
output strobe_in,
output reg [15:0] debug
);
reg [8:0] keymac;
reg key_pending;
reg [21:0] pacetimer;
reg inquiry_active;
reg extended;
reg keybreak;
reg capslock;
reg haskey;
wire got_key;
wire got_break;
wire got_extend;
wire tick_short;
wire tick_long;
wire pop_key;
reg cmd_inquiry;
reg cmd_instant;
reg cmd_model;
reg cmd_test;
reg[1:0] state;
reg[1:0] next;
reg nreq;
reg[7:0] nbyte;
/* PS2 interface signals */
wire istrobe;
wire [7:0] ibyte;
reg oreq;
reg [7:0] obyte;
wire oack;
wire timeout;
wire [1:0] dbg_lowstate;
ps2 ps20(.sysclk(sysclk),
.reset(reset),
.ps2dat(ps2dat),
.ps2clk(ps2clk),
.istrobe(istrobe),
.ibyte(ibyte),
.oreq(oreq),
.obyte(obyte),
.oack(oack),
.timeout(timeout),
.dbg_state(dbg_lowstate));
/* --- PS2 side State machine ---
*
* - at state_init: wait for BAT reply
* * 0xaa -> send 0xed -> state_led1
* * bad reply -> send 0xff -> state_init
* * timeout -> send 0xff -> state_init
*
* - at state_led1: wait for ack, send LED state
* * 0xfa -> send 0xYY -> state_led2 YY=LED
* * bad reply -> send 0xff -> state_init
* * timeout -> send 0xff -> state_init
*
* - at state_led2: wait for ack, go wait data
* * 0xfa -> state_wait
* * bad reply -> send 0xff -> state_init
* * timeout -> send 0xff -> state_init
*
* - at state_wait: wait for data byte
* * capslock -> send 0xed -> state_led1
* * other -> state_wait
*
* Works fine with my logitech USB/PS2 keyboard, but fails
* miserably with an old HP PS2 keyboard (which also behaves
* oddly with minimig as an amiga). Will eventually investigate...
*/
localparam ps2k_state_init = 0;
localparam ps2k_state_led1 = 1;
localparam ps2k_state_led2 = 2;
localparam ps2k_state_wait = 3;
/* Unlike my other modules, here I'll play with a big fat
* combo logic. The outputs are:
* - oreq : triggers sending of a byte. Set based on either
* timeout or istrobe, and as such only set for a
* clock.
* - next : next state
* - obyte : next byte to send
*/
always@(timeout or state or istrobe or ibyte or capslock) begin
nreq = 0;
next = state;
nbyte = 8'hff;
if (istrobe || timeout)
case(state)
ps2k_state_init: begin
if (istrobe && ibyte == 8'haa) begin
nbyte = 8'hed;
nreq = 1;
next = ps2k_state_led1;
end else if (ibyte != 8'hfa)
nreq = 1;
end
ps2k_state_led1: begin
nreq = 1;
if (istrobe && ibyte == 8'hfa) begin
nbyte = { 5'b00000, capslock, 1'b1, 1'b0 };
next = ps2k_state_led2;
end else
next = ps2k_state_init;
end
ps2k_state_led2: begin
if (istrobe && ibyte == 8'hfa)
next = ps2k_state_wait;
else begin
nreq = 1;
next = ps2k_state_init;
end
end
ps2k_state_wait: begin
/* Update LEDs */
// if (istrobe && ibyte == 8'h58) begin
// nbyte = 8'hed;
// nreq = 1;
// next = ps2k_state_led1;
// end
end
endcase
end
/* State related latches. We latch oreq and obyte, we don't
* necessarily have to but that avoids back to back
* receive/send at the low level which can upset things
*/
always@(posedge sysclk or posedge reset)
if (reset)
state <= ps2k_state_wait; // ps2k_state_init
else
state <= next;
always@(posedge sysclk or posedge reset)
if (reset)
oreq <= 0;
else
oreq <= nreq;
always@(posedge sysclk or posedge reset)
if (reset)
obyte <= 0;
else
obyte <= nbyte;
assign got_key = (state == ps2k_state_wait) && istrobe;
assign got_break = { ibyte[7:1], 1'b0 } == 8'hf0;
assign got_extend = { ibyte[7:1], 1'b0 } == 8'he0;
/* Latch key info from PS2, handle capslock state */
always@(posedge sysclk or posedge reset)
if (reset) begin
extended <= 0;
keybreak <= 0;
capslock <= 0;
end else if (got_key) begin
if (got_break)
keybreak <= 1;
else if (got_extend)
extended <= 1;
else begin
keybreak <= 0;
extended <= 0;
/* Capslock handling */
if (ibyte == 8'h58 && !keybreak)
capslock <= ~capslock;
end
end
/* --- Mac side --- */
/* Latch commands from Mac */
always@(posedge sysclk or posedge reset)
if (reset) begin
cmd_inquiry <= 0;
cmd_instant <= 0;
cmd_model <= 0;
cmd_test <= 0;
end else begin
if (strobe_out) begin
cmd_inquiry <= 0;
cmd_instant <= 0;
cmd_model <= 0;
cmd_test <= 0;
case(data_out)
8'h10: cmd_inquiry <= 1;
8'h14: cmd_instant <= 1;
8'h16: cmd_model <= 1;
8'h36: cmd_test <= 1;
endcase
end
end
/* Divide our clock to pace our responses to the Mac. tick_short ticks
* when we can respond to a command, and tick_long ticks when an inquiry
* command shall timeout
*/
always@(posedge sysclk or posedge reset)
if (reset)
pacetimer <= 0;
else begin
/* reset counter on command from Mac */
if (strobe_out)
pacetimer <= 0;
else if (!tick_long)
pacetimer <= pacetimer + 1;
end
assign tick_long = pacetimer == 22'h3fffff;
assign tick_short = pacetimer == 22'h000fff;
/* Delay inquiry responses to after tick_short */
always@(posedge sysclk or posedge reset)
if (reset)
inquiry_active <= 0;
else begin
if (strobe_out | strobe_in)
inquiry_active <= 0;
else if (tick_short)
inquiry_active <= cmd_inquiry;
end
/* Key answer to the mac XXX FIXME: keypad */
assign pop_key = (cmd_instant & tick_short) |
(inquiry_active & tick_long) |
(inquiry_active & key_pending);
/* Reply to Mac */
assign strobe_in = ((cmd_model | cmd_test) & tick_short) | pop_key;
/* Latch key_pending */
always @(posedge sysclk or posedge reset)
if (reset)
key_pending <= 0;
else begin
if (pop_key | cmd_model | cmd_test)
key_pending <= 0;
else if (!key_pending & got_key && !got_break && !got_extend)
key_pending <= 1;
end
/* Data to Mac ... XXX: Handle keypad and special case capslock */
assign data_in = cmd_test ? 8'h7d :
cmd_model ? 8'h03 :
key_pending ? keymac[7:0] : 8'h7b;
/* Keymap. XXX add option to assign ctrl/alt/windows to cmd/option
* differently
*/
always @(posedge sysclk)
if (got_key && !key_pending) begin
case({extended,ibyte}) // Scan Code Set 2
9'h000: keymac[8:0] <= 9'h07b;
9'h001: keymac[8:0] <= 9'h07b; //F9
9'h002: keymac[8:0] <= 9'h07b;
9'h003: keymac[8:0] <= 9'h07b; //F5
9'h004: keymac[8:0] <= 9'h07b; //F3
9'h005: keymac[8:0] <= 9'h07b; //F1
9'h006: keymac[8:0] <= 9'h07b; //F2
9'h007: keymac[8:0] <= 9'h07b; //F12 <OSD>
9'h008: keymac[8:0] <= 9'h07b;
9'h009: keymac[8:0] <= 9'h07b; //F10
9'h00a: keymac[8:0] <= 9'h07b; //F8
9'h00b: keymac[8:0] <= 9'h07b; //F6
9'h00c: keymac[8:0] <= 9'h07b; //F4
9'h00d: keymac[8:0] <= 9'h061; //TAB
9'h00e: keymac[8:0] <= 9'h065; //~ (`)
9'h00f: keymac[8:0] <= 9'h07b;
9'h010: keymac[8:0] <= 9'h07b;
9'h011: keymac[8:0] <= 9'h075; //LEFT ALT (option)
9'h012: keymac[8:0] <= 9'h071; //LEFT SHIFT
9'h013: keymac[8:0] <= 9'h07b;
9'h014: keymac[8:0] <= 9'h06f; //CTRL (command)
9'h015: keymac[8:0] <= 9'h019; //q
9'h016: keymac[8:0] <= 9'h025; //1
9'h017: keymac[8:0] <= 9'h07b;
9'h018: keymac[8:0] <= 9'h07b;
9'h019: keymac[8:0] <= 9'h07b;
9'h01a: keymac[8:0] <= 9'h00d; //z
9'h01b: keymac[8:0] <= 9'h003; //s
9'h01c: keymac[8:0] <= 9'h001; //a
9'h01d: keymac[8:0] <= 9'h01b; //w
9'h01e: keymac[8:0] <= 9'h027; //2
9'h01f: keymac[8:0] <= 9'h07b;
9'h020: keymac[8:0] <= 9'h07b;
9'h021: keymac[8:0] <= 9'h011; //c
9'h022: keymac[8:0] <= 9'h00f; //x
9'h023: keymac[8:0] <= 9'h005; //d
9'h024: keymac[8:0] <= 9'h01d; //e
9'h025: keymac[8:0] <= 9'h02b; //4
9'h026: keymac[8:0] <= 9'h029; //3
9'h027: keymac[8:0] <= 9'h07b;
9'h028: keymac[8:0] <= 9'h07b;
9'h029: keymac[8:0] <= 9'h063; //SPACE
9'h02a: keymac[8:0] <= 9'h013; //v
9'h02b: keymac[8:0] <= 9'h007; //f
9'h02c: keymac[8:0] <= 9'h023; //t
9'h02d: keymac[8:0] <= 9'h01f; //r
9'h02e: keymac[8:0] <= 9'h02f; //5
9'h02f: keymac[8:0] <= 9'h07b;
9'h030: keymac[8:0] <= 9'h07b;
9'h031: keymac[8:0] <= 9'h05b; //n
9'h032: keymac[8:0] <= 9'h017; //b
9'h033: keymac[8:0] <= 9'h009; //h
9'h034: keymac[8:0] <= 9'h00b; //g
9'h035: keymac[8:0] <= 9'h021; //y
9'h036: keymac[8:0] <= 9'h02d; //6
9'h037: keymac[8:0] <= 9'h07b;
9'h038: keymac[8:0] <= 9'h07b;
9'h039: keymac[8:0] <= 9'h07b;
9'h03a: keymac[8:0] <= 9'h05d; //m
9'h03b: keymac[8:0] <= 9'h04d; //j
9'h03c: keymac[8:0] <= 9'h041; //u
9'h03d: keymac[8:0] <= 9'h035; //7
9'h03e: keymac[8:0] <= 9'h039; //8
9'h03f: keymac[8:0] <= 9'h07b;
9'h040: keymac[8:0] <= 9'h07b;
9'h041: keymac[8:0] <= 9'h057; //<,
9'h042: keymac[8:0] <= 9'h051; //k
9'h043: keymac[8:0] <= 9'h045; //i
9'h044: keymac[8:0] <= 9'h03f; //o
9'h045: keymac[8:0] <= 9'h03b; //0
9'h046: keymac[8:0] <= 9'h033; //9
9'h047: keymac[8:0] <= 9'h07b;
9'h048: keymac[8:0] <= 9'h07b;
9'h049: keymac[8:0] <= 9'h05f; //>.
9'h04a: keymac[8:0] <= 9'h059; //FORWARD SLASH
9'h04b: keymac[8:0] <= 9'h04b; //l
9'h04c: keymac[8:0] <= 9'h053; //;
9'h04d: keymac[8:0] <= 9'h047; //p
9'h04e: keymac[8:0] <= 9'h037; //-
9'h04f: keymac[8:0] <= 9'h07b;
9'h050: keymac[8:0] <= 9'h07b;
9'h051: keymac[8:0] <= 9'h07b;
9'h052: keymac[8:0] <= 9'h04f; //'"
9'h053: keymac[8:0] <= 9'h07b;
9'h054: keymac[8:0] <= 9'h043; //[
9'h055: keymac[8:0] <= 9'h031; // =
9'h056: keymac[8:0] <= 9'h07b;
9'h057: keymac[8:0] <= 9'h07b;
9'h058: keymac[8:0] <= 9'h073; //CAPSLOCK
9'h059: keymac[8:0] <= 9'h071; //RIGHT SHIFT
9'h05a: keymac[8:0] <= 9'h049; //ENTER
9'h05b: keymac[8:0] <= 9'h03d; //]
9'h05c: keymac[8:0] <= 9'h07b;
9'h05d: keymac[8:0] <= 9'h055; //BACKSLASH
9'h05e: keymac[8:0] <= 9'h07b;
9'h05f: keymac[8:0] <= 9'h07b;
9'h060: keymac[8:0] <= 9'h07b;
9'h061: keymac[8:0] <= 9'h071; //international left shift cut out (German '<>' key), 0x56 Set#1 code
9'h062: keymac[8:0] <= 9'h07b;
9'h063: keymac[8:0] <= 9'h07b;
9'h064: keymac[8:0] <= 9'h07b;
9'h065: keymac[8:0] <= 9'h07b;
9'h066: keymac[8:0] <= 9'h067; //BACKSPACE
9'h067: keymac[8:0] <= 9'h07b;
9'h068: keymac[8:0] <= 9'h07b;
9'h069: keymac[8:0] <= 9'h127; //KP 1
9'h06a: keymac[8:0] <= 9'h07b;
9'h06b: keymac[8:0] <= 9'h12d; //KP 4
9'h06c: keymac[8:0] <= 9'h133; //KP 7
9'h06d: keymac[8:0] <= 9'h07b;
9'h06e: keymac[8:0] <= 9'h07b;
9'h06f: keymac[8:0] <= 9'h07b;
9'h070: keymac[8:0] <= 9'h125; //KP 0
9'h071: keymac[8:0] <= 9'h103; //KP .
9'h072: keymac[8:0] <= 9'h129; //KP 2
9'h073: keymac[8:0] <= 9'h12f; //KP 5
9'h074: keymac[8:0] <= 9'h131; //KP 6
9'h075: keymac[8:0] <= 9'h137; //KP 8
9'h076: keymac[8:0] <= 9'b000; //ESCAPE
9'h077: keymac[8:0] <= 9'h07b; //NUMLOCK
9'h078: keymac[8:0] <= 9'h07b; //F11 <OSD>
9'h079: keymac[8:0] <= 9'h07b; //KP +
9'h07a: keymac[8:0] <= 9'h12b; //KP 3
9'h07b: keymac[8:0] <= 9'h11d; //KP -
9'h07c: keymac[8:0] <= 9'h07b; //KP *
9'h07d: keymac[8:0] <= 9'h139; //KP 9
9'h07e: keymac[8:0] <= 9'h07b; //SCROLL LOCK / KP )
9'h07f: keymac[8:0] <= 9'h07b;
9'h080: keymac[8:0] <= 9'h07b;
9'h081: keymac[8:0] <= 9'h07b;
9'h082: keymac[8:0] <= 9'h07b;
9'h083: keymac[8:0] <= 9'h07b; //F7
9'h084: keymac[8:0] <= 9'h07b;
9'h085: keymac[8:0] <= 9'h07b;
9'h086: keymac[8:0] <= 9'h07b;
9'h087: keymac[8:0] <= 9'h07b;
9'h088: keymac[8:0] <= 9'h07b;
9'h089: keymac[8:0] <= 9'h07b;
9'h08a: keymac[8:0] <= 9'h07b;
9'h08b: keymac[8:0] <= 9'h07b;
9'h08c: keymac[8:0] <= 9'h07b;
9'h08d: keymac[8:0] <= 9'h07b;
9'h08e: keymac[8:0] <= 9'h07b;
9'h08f: keymac[8:0] <= 9'h07b;
9'h090: keymac[8:0] <= 9'h07b;
9'h091: keymac[8:0] <= 9'h07b;
9'h092: keymac[8:0] <= 9'h07b;
9'h093: keymac[8:0] <= 9'h07b;
9'h094: keymac[8:0] <= 9'h07b;
9'h095: keymac[8:0] <= 9'h07b;
9'h096: keymac[8:0] <= 9'h07b;
9'h097: keymac[8:0] <= 9'h07b;
9'h098: keymac[8:0] <= 9'h07b;
9'h099: keymac[8:0] <= 9'h07b;
9'h09a: keymac[8:0] <= 9'h07b;
9'h09b: keymac[8:0] <= 9'h07b;
9'h09c: keymac[8:0] <= 9'h07b;
9'h09d: keymac[8:0] <= 9'h07b;
9'h09e: keymac[8:0] <= 9'h07b;
9'h09f: keymac[8:0] <= 9'h07b;
9'h0a0: keymac[8:0] <= 9'h07b;
9'h0a1: keymac[8:0] <= 9'h07b;
9'h0a2: keymac[8:0] <= 9'h07b;
9'h0a3: keymac[8:0] <= 9'h07b;
9'h0a4: keymac[8:0] <= 9'h07b;
9'h0a5: keymac[8:0] <= 9'h07b;
9'h0a6: keymac[8:0] <= 9'h07b;
9'h0a7: keymac[8:0] <= 9'h07b;
9'h0a8: keymac[8:0] <= 9'h07b;
9'h0a9: keymac[8:0] <= 9'h07b;
9'h0aa: keymac[8:0] <= 9'h07b;
9'h0ab: keymac[8:0] <= 9'h07b;
9'h0ac: keymac[8:0] <= 9'h07b;
9'h0ad: keymac[8:0] <= 9'h07b;
9'h0ae: keymac[8:0] <= 9'h07b;
9'h0af: keymac[8:0] <= 9'h07b;
9'h0b0: keymac[8:0] <= 9'h07b;
9'h0b1: keymac[8:0] <= 9'h07b;
9'h0b2: keymac[8:0] <= 9'h07b;
9'h0b3: keymac[8:0] <= 9'h07b;
9'h0b4: keymac[8:0] <= 9'h07b;
9'h0b5: keymac[8:0] <= 9'h07b;
9'h0b6: keymac[8:0] <= 9'h07b;
9'h0b7: keymac[8:0] <= 9'h07b;
9'h0b8: keymac[8:0] <= 9'h07b;
9'h0b9: keymac[8:0] <= 9'h07b;
9'h0ba: keymac[8:0] <= 9'h07b;
9'h0bb: keymac[8:0] <= 9'h07b;
9'h0bc: keymac[8:0] <= 9'h07b;
9'h0bd: keymac[8:0] <= 9'h07b;
9'h0be: keymac[8:0] <= 9'h07b;
9'h0bf: keymac[8:0] <= 9'h07b;
9'h0c0: keymac[8:0] <= 9'h07b;
9'h0c1: keymac[8:0] <= 9'h07b;
9'h0c2: keymac[8:0] <= 9'h07b;
9'h0c3: keymac[8:0] <= 9'h07b;
9'h0c4: keymac[8:0] <= 9'h07b;
9'h0c5: keymac[8:0] <= 9'h07b;
9'h0c6: keymac[8:0] <= 9'h07b;
9'h0c7: keymac[8:0] <= 9'h07b;
9'h0c8: keymac[8:0] <= 9'h07b;
9'h0c9: keymac[8:0] <= 9'h07b;
9'h0ca: keymac[8:0] <= 9'h07b;
9'h0cb: keymac[8:0] <= 9'h07b;
9'h0cc: keymac[8:0] <= 9'h07b;
9'h0cd: keymac[8:0] <= 9'h07b;
9'h0ce: keymac[8:0] <= 9'h07b;
9'h0cf: keymac[8:0] <= 9'h07b;
9'h0d0: keymac[8:0] <= 9'h07b;
9'h0d1: keymac[8:0] <= 9'h07b;
9'h0d2: keymac[8:0] <= 9'h07b;
9'h0d3: keymac[8:0] <= 9'h07b;
9'h0d4: keymac[8:0] <= 9'h07b;
9'h0d5: keymac[8:0] <= 9'h07b;
9'h0d6: keymac[8:0] <= 9'h07b;
9'h0d7: keymac[8:0] <= 9'h07b;
9'h0d8: keymac[8:0] <= 9'h07b;
9'h0d9: keymac[8:0] <= 9'h07b;
9'h0da: keymac[8:0] <= 9'h07b;
9'h0db: keymac[8:0] <= 9'h07b;
9'h0dc: keymac[8:0] <= 9'h07b;
9'h0dd: keymac[8:0] <= 9'h07b;
9'h0de: keymac[8:0] <= 9'h07b;
9'h0df: keymac[8:0] <= 9'h07b;
9'h0e0: keymac[8:0] <= 9'h07b; //ps2 extended key
9'h0e1: keymac[8:0] <= 9'h07b;
9'h0e2: keymac[8:0] <= 9'h07b;
9'h0e3: keymac[8:0] <= 9'h07b;
9'h0e4: keymac[8:0] <= 9'h07b;
9'h0e5: keymac[8:0] <= 9'h07b;
9'h0e6: keymac[8:0] <= 9'h07b;
9'h0e7: keymac[8:0] <= 9'h07b;
9'h0e8: keymac[8:0] <= 9'h07b;
9'h0e9: keymac[8:0] <= 9'h07b;
9'h0ea: keymac[8:0] <= 9'h07b;
9'h0eb: keymac[8:0] <= 9'h07b;
9'h0ec: keymac[8:0] <= 9'h07b;
9'h0ed: keymac[8:0] <= 9'h07b;
9'h0ee: keymac[8:0] <= 9'h07b;
9'h0ef: keymac[8:0] <= 9'h07b;
9'h0f0: keymac[8:0] <= 9'h07b; //ps2 release code
9'h0f1: keymac[8:0] <= 9'h07b;
9'h0f2: keymac[8:0] <= 9'h07b;
9'h0f3: keymac[8:0] <= 9'h07b;
9'h0f4: keymac[8:0] <= 9'h07b;
9'h0f5: keymac[8:0] <= 9'h07b;
9'h0f6: keymac[8:0] <= 9'h07b;
9'h0f7: keymac[8:0] <= 9'h07b;
9'h0f8: keymac[8:0] <= 9'h07b;
9'h0f9: keymac[8:0] <= 9'h07b;
9'h0fa: keymac[8:0] <= 9'h07b; //ps2 ack code
9'h0fb: keymac[8:0] <= 9'h07b;
9'h0fc: keymac[8:0] <= 9'h07b;
9'h0fd: keymac[8:0] <= 9'h07b;
9'h0fe: keymac[8:0] <= 9'h07b;
9'h0ff: keymac[8:0] <= 9'h07b;
9'h100: keymac[8:0] <= 9'h07b;
9'h101: keymac[8:0] <= 9'h07b;
9'h102: keymac[8:0] <= 9'h07b;
9'h103: keymac[8:0] <= 9'h07b;
9'h104: keymac[8:0] <= 9'h07b;
9'h105: keymac[8:0] <= 9'h07b;
9'h106: keymac[8:0] <= 9'h07b;
9'h107: keymac[8:0] <= 9'h07b;
9'h108: keymac[8:0] <= 9'h07b;
9'h109: keymac[8:0] <= 9'h07b;
9'h10a: keymac[8:0] <= 9'h07b;
9'h10b: keymac[8:0] <= 9'h07b;
9'h10c: keymac[8:0] <= 9'h07b;
9'h10d: keymac[8:0] <= 9'h07b;
9'h10e: keymac[8:0] <= 9'h07b;
9'h10f: keymac[8:0] <= 9'h07b;
9'h110: keymac[8:0] <= 9'h07b;
9'h111: keymac[8:0] <= 9'h075; //RIGHT ALT
9'h112: keymac[8:0] <= 9'h07b;
9'h113: keymac[8:0] <= 9'h07b;
9'h114: keymac[8:0] <= 9'h07b;
9'h115: keymac[8:0] <= 9'h07b;
9'h116: keymac[8:0] <= 9'h07b;
9'h117: keymac[8:0] <= 9'h07b;
9'h118: keymac[8:0] <= 9'h07b;
9'h119: keymac[8:0] <= 9'h07b;
9'h11a: keymac[8:0] <= 9'h07b;
9'h11b: keymac[8:0] <= 9'h07b;
9'h11c: keymac[8:0] <= 9'h07b;
9'h11d: keymac[8:0] <= 9'h07b;
9'h11e: keymac[8:0] <= 9'h07b;
9'h11f: keymac[8:0] <= 9'h06f; //LEFT COMMAND (LEFT GUI)
9'h120: keymac[8:0] <= 9'h07b;
9'h121: keymac[8:0] <= 9'h07b;
9'h122: keymac[8:0] <= 9'h07b;
9'h123: keymac[8:0] <= 9'h07b;
9'h124: keymac[8:0] <= 9'h07b;
9'h125: keymac[8:0] <= 9'h07b;
9'h126: keymac[8:0] <= 9'h07b;
9'h127: keymac[8:0] <= 9'h06f; //RIGHT AMIGA (RIGHT GUI)
9'h128: keymac[8:0] <= 9'h07b;
9'h129: keymac[8:0] <= 9'h07b;
9'h12a: keymac[8:0] <= 9'h07b;
9'h12b: keymac[8:0] <= 9'h07b;
9'h12c: keymac[8:0] <= 9'h07b;
9'h12d: keymac[8:0] <= 9'h07b;
9'h12e: keymac[8:0] <= 9'h07b;
9'h12f: keymac[8:0] <= 9'h06f; //RIGHT AMIGA (APPS)
9'h130: keymac[8:0] <= 9'h07b;
9'h131: keymac[8:0] <= 9'h07b;
9'h132: keymac[8:0] <= 9'h07b;
9'h133: keymac[8:0] <= 9'h07b;
9'h134: keymac[8:0] <= 9'h07b;
9'h135: keymac[8:0] <= 9'h07b;
9'h136: keymac[8:0] <= 9'h07b;
9'h137: keymac[8:0] <= 9'h07b;
9'h138: keymac[8:0] <= 9'h07b;
9'h139: keymac[8:0] <= 9'h07b;
9'h13a: keymac[8:0] <= 9'h07b;
9'h13b: keymac[8:0] <= 9'h07b;
9'h13c: keymac[8:0] <= 9'h07b;
9'h13d: keymac[8:0] <= 9'h07b;
9'h13e: keymac[8:0] <= 9'h07b;
9'h13f: keymac[8:0] <= 9'h07b;
9'h140: keymac[8:0] <= 9'h07b;
9'h141: keymac[8:0] <= 9'h07b;
9'h142: keymac[8:0] <= 9'h07b;
9'h143: keymac[8:0] <= 9'h07b;
9'h144: keymac[8:0] <= 9'h07b;
9'h145: keymac[8:0] <= 9'h07b;
9'h146: keymac[8:0] <= 9'h07b;
9'h147: keymac[8:0] <= 9'h07b;
9'h148: keymac[8:0] <= 9'h07b;
9'h149: keymac[8:0] <= 9'h07b;
9'h14a: keymac[8:0] <= 9'h07b; //KP /
9'h14b: keymac[8:0] <= 9'h07b;
9'h14c: keymac[8:0] <= 9'h07b;
9'h14d: keymac[8:0] <= 9'h07b;
9'h14e: keymac[8:0] <= 9'h07b;
9'h14f: keymac[8:0] <= 9'h07b;
9'h150: keymac[8:0] <= 9'h07b;
9'h151: keymac[8:0] <= 9'h07b;
9'h152: keymac[8:0] <= 9'h07b;
9'h153: keymac[8:0] <= 9'h07b;
9'h154: keymac[8:0] <= 9'h07b;
9'h155: keymac[8:0] <= 9'h07b;
9'h156: keymac[8:0] <= 9'h07b;
9'h157: keymac[8:0] <= 9'h07b;
9'h158: keymac[8:0] <= 9'h07b;
9'h159: keymac[8:0] <= 9'h07b;
9'h15a: keymac[8:0] <= 9'h119; //KP ENTER
9'h15b: keymac[8:0] <= 9'h07b;
9'h15c: keymac[8:0] <= 9'h07b;
9'h15d: keymac[8:0] <= 9'h07b;
9'h15e: keymac[8:0] <= 9'h07b;
9'h15f: keymac[8:0] <= 9'h07b;
9'h160: keymac[8:0] <= 9'h07b;
9'h161: keymac[8:0] <= 9'h07b;
9'h162: keymac[8:0] <= 9'h07b;
9'h163: keymac[8:0] <= 9'h07b;
9'h164: keymac[8:0] <= 9'h07b;
9'h165: keymac[8:0] <= 9'h07b;
9'h166: keymac[8:0] <= 9'h07b;
9'h167: keymac[8:0] <= 9'h07b;
9'h168: keymac[8:0] <= 9'h07b;
9'h169: keymac[8:0] <= 9'h07b; //END
9'h16a: keymac[8:0] <= 9'h07b;
9'h16b: keymac[8:0] <= 9'h10d; //ARROW LEFT
9'h16c: keymac[8:0] <= 9'h07b; //HOME
9'h16d: keymac[8:0] <= 9'h07b;
9'h16e: keymac[8:0] <= 9'h07b;
9'h16f: keymac[8:0] <= 9'h07b;
9'h170: keymac[8:0] <= 9'h07b; //INSERT = HELP
9'h171: keymac[8:0] <= 9'h10f; //DELETE
9'h172: keymac[8:0] <= 9'h111; //ARROW DOWN
9'h173: keymac[8:0] <= 9'h07b;
9'h174: keymac[8:0] <= 9'h105; //ARROW RIGHT
9'h175: keymac[8:0] <= 9'h10b; //ARROW UP
9'h176: keymac[8:0] <= 9'h07b;
9'h177: keymac[8:0] <= 9'h07b;
9'h178: keymac[8:0] <= 9'h07b;
9'h179: keymac[8:0] <= 9'h07b;
9'h17a: keymac[8:0] <= 9'h07b; //PGDN <OSD>
9'h17b: keymac[8:0] <= 9'h07b;
9'h17c: keymac[8:0] <= 9'h07b; //PRTSCR <OSD>
9'h17d: keymac[8:0] <= 9'h07b; //PGUP <OSD>
9'h17e: keymac[8:0] <= 9'h07b; //ctrl+break
9'h17f: keymac[8:0] <= 9'h07b;
9'h180: keymac[8:0] <= 9'h07b;
9'h181: keymac[8:0] <= 9'h07b;
9'h182: keymac[8:0] <= 9'h07b;
9'h183: keymac[8:0] <= 9'h07b;
9'h184: keymac[8:0] <= 9'h07b;
9'h185: keymac[8:0] <= 9'h07b;
9'h186: keymac[8:0] <= 9'h07b;
9'h187: keymac[8:0] <= 9'h07b;
9'h188: keymac[8:0] <= 9'h07b;
9'h189: keymac[8:0] <= 9'h07b;
9'h18a: keymac[8:0] <= 9'h07b;
9'h18b: keymac[8:0] <= 9'h07b;
9'h18c: keymac[8:0] <= 9'h07b;
9'h18d: keymac[8:0] <= 9'h07b;
9'h18e: keymac[8:0] <= 9'h07b;
9'h18f: keymac[8:0] <= 9'h07b;
9'h190: keymac[8:0] <= 9'h07b;
9'h191: keymac[8:0] <= 9'h07b;
9'h192: keymac[8:0] <= 9'h07b;
9'h193: keymac[8:0] <= 9'h07b;
9'h194: keymac[8:0] <= 9'h07b;
9'h195: keymac[8:0] <= 9'h07b;
9'h196: keymac[8:0] <= 9'h07b;
9'h197: keymac[8:0] <= 9'h07b;
9'h198: keymac[8:0] <= 9'h07b;
9'h199: keymac[8:0] <= 9'h07b;
9'h19a: keymac[8:0] <= 9'h07b;
9'h19b: keymac[8:0] <= 9'h07b;
9'h19c: keymac[8:0] <= 9'h07b;
9'h19d: keymac[8:0] <= 9'h07b;
9'h19e: keymac[8:0] <= 9'h07b;
9'h19f: keymac[8:0] <= 9'h07b;
9'h1a0: keymac[8:0] <= 9'h07b;
9'h1a1: keymac[8:0] <= 9'h07b;
9'h1a2: keymac[8:0] <= 9'h07b;
9'h1a3: keymac[8:0] <= 9'h07b;
9'h1a4: keymac[8:0] <= 9'h07b;
9'h1a5: keymac[8:0] <= 9'h07b;
9'h1a6: keymac[8:0] <= 9'h07b;
9'h1a7: keymac[8:0] <= 9'h07b;
9'h1a8: keymac[8:0] <= 9'h07b;
9'h1a9: keymac[8:0] <= 9'h07b;
9'h1aa: keymac[8:0] <= 9'h07b;
9'h1ab: keymac[8:0] <= 9'h07b;
9'h1ac: keymac[8:0] <= 9'h07b;
9'h1ad: keymac[8:0] <= 9'h07b;
9'h1ae: keymac[8:0] <= 9'h07b;
9'h1af: keymac[8:0] <= 9'h07b;
9'h1b0: keymac[8:0] <= 9'h07b;
9'h1b1: keymac[8:0] <= 9'h07b;
9'h1b2: keymac[8:0] <= 9'h07b;
9'h1b3: keymac[8:0] <= 9'h07b;
9'h1b4: keymac[8:0] <= 9'h07b;
9'h1b5: keymac[8:0] <= 9'h07b;
9'h1b6: keymac[8:0] <= 9'h07b;
9'h1b7: keymac[8:0] <= 9'h07b;
9'h1b8: keymac[8:0] <= 9'h07b;
9'h1b9: keymac[8:0] <= 9'h07b;
9'h1ba: keymac[8:0] <= 9'h07b;
9'h1bb: keymac[8:0] <= 9'h07b;
9'h1bc: keymac[8:0] <= 9'h07b;
9'h1bd: keymac[8:0] <= 9'h07b;
9'h1be: keymac[8:0] <= 9'h07b;
9'h1bf: keymac[8:0] <= 9'h07b;
9'h1c0: keymac[8:0] <= 9'h07b;
9'h1c1: keymac[8:0] <= 9'h07b;
9'h1c2: keymac[8:0] <= 9'h07b;
9'h1c3: keymac[8:0] <= 9'h07b;
9'h1c4: keymac[8:0] <= 9'h07b;
9'h1c5: keymac[8:0] <= 9'h07b;
9'h1c6: keymac[8:0] <= 9'h07b;
9'h1c7: keymac[8:0] <= 9'h07b;
9'h1c8: keymac[8:0] <= 9'h07b;
9'h1c9: keymac[8:0] <= 9'h07b;
9'h1ca: keymac[8:0] <= 9'h07b;
9'h1cb: keymac[8:0] <= 9'h07b;
9'h1cc: keymac[8:0] <= 9'h07b;
9'h1cd: keymac[8:0] <= 9'h07b;
9'h1ce: keymac[8:0] <= 9'h07b;
9'h1cf: keymac[8:0] <= 9'h07b;
9'h1d0: keymac[8:0] <= 9'h07b;
9'h1d1: keymac[8:0] <= 9'h07b;
9'h1d2: keymac[8:0] <= 9'h07b;
9'h1d3: keymac[8:0] <= 9'h07b;
9'h1d4: keymac[8:0] <= 9'h07b;
9'h1d5: keymac[8:0] <= 9'h07b;
9'h1d6: keymac[8:0] <= 9'h07b;
9'h1d7: keymac[8:0] <= 9'h07b;
9'h1d8: keymac[8:0] <= 9'h07b;
9'h1d9: keymac[8:0] <= 9'h07b;
9'h1da: keymac[8:0] <= 9'h07b;
9'h1db: keymac[8:0] <= 9'h07b;
9'h1dc: keymac[8:0] <= 9'h07b;
9'h1dd: keymac[8:0] <= 9'h07b;
9'h1de: keymac[8:0] <= 9'h07b;
9'h1df: keymac[8:0] <= 9'h07b;
9'h1e0: keymac[8:0] <= 9'h07b; //ps2 extended key(duplicate, see $e0)
9'h1e1: keymac[8:0] <= 9'h07b;
9'h1e2: keymac[8:0] <= 9'h07b;
9'h1e3: keymac[8:0] <= 9'h07b;
9'h1e4: keymac[8:0] <= 9'h07b;
9'h1e5: keymac[8:0] <= 9'h07b;
9'h1e6: keymac[8:0] <= 9'h07b;
9'h1e7: keymac[8:0] <= 9'h07b;
9'h1e8: keymac[8:0] <= 9'h07b;
9'h1e9: keymac[8:0] <= 9'h07b;
9'h1ea: keymac[8:0] <= 9'h07b;
9'h1eb: keymac[8:0] <= 9'h07b;
9'h1ec: keymac[8:0] <= 9'h07b;
9'h1ed: keymac[8:0] <= 9'h07b;
9'h1ee: keymac[8:0] <= 9'h07b;
9'h1ef: keymac[8:0] <= 9'h07b;
9'h1f0: keymac[8:0] <= 9'h07b; //ps2 release code(duplicate, see $f0)
9'h1f1: keymac[8:0] <= 9'h07b;
9'h1f2: keymac[8:0] <= 9'h07b;
9'h1f3: keymac[8:0] <= 9'h07b;
9'h1f4: keymac[8:0] <= 9'h07b;
9'h1f5: keymac[8:0] <= 9'h07b;
9'h1f6: keymac[8:0] <= 9'h07b;
9'h1f7: keymac[8:0] <= 9'h07b;
9'h1f8: keymac[8:0] <= 9'h07b;
9'h1f9: keymac[8:0] <= 9'h07b;
9'h1fa: keymac[8:0] <= 9'h07b; //ps2 ack code(duplicate see $fa)
9'h1fb: keymac[8:0] <= 9'h07b;
9'h1fc: keymac[8:0] <= 9'h07b;
9'h1fd: keymac[8:0] <= 9'h07b;
9'h1fe: keymac[8:0] <= 9'h07b;
9'h1ff: keymac[8:0] <= 9'h07b;
endcase // case ({extended,ps2key[7:0]})
keymac[7] <= keybreak;
end
/* Some debug signals for my own sanity */
always@(posedge sysclk or posedge reset) begin
if (reset)
debug <= 0;
else begin
if (istrobe)
debug[15:8] <= ibyte;
debug[7:0] <= { ps2clk, ps2dat, dbg_lowstate, 2'b0,
state };
end
end
endmodule

79
cores/plus_too/scc.v
View File

@@ -47,6 +47,7 @@ module scc(input sysclk,
/* Register access is semi-insane */
reg [3:0] rindex;
reg [3:0] rindex_latch;
wire wreg_a;
wire wreg_b;
wire wdata_a;
@@ -139,23 +140,28 @@ module scc(input sysclk,
assign rdata_a = cs & (~we) & (rs[1] | (rindex == 8)) & rs[0];
assign rdata_b = cs & (~we) & (rs[1] | (rindex == 8)) & ~rs[0];
// make sure rindex changes after the cpu cycle has ended so
// read data is still stable while cpu advances
always@(negedge sysclk)
rindex <= rindex_latch;
/* Register index is set by a write to WR0 and reset
* after any subsequent write. We ignore the side
*/
always@(posedge sysclk or posedge reset) begin
always@(negedge sysclk or posedge reset) begin
if (reset)
rindex <= 0;
rindex_latch <= 0;
else if (cs && !rs[1]) begin
/* Default, reset index */
rindex <= 0;
rindex_latch <= 0;
/* Write to WR0 */
if (we && rindex == 0) begin
/* Get low index bits */
rindex[2:0] <= wdata[2:0];
rindex_latch[2:0] <= wdata[2:0];
/* Add point high */
rindex[3] <= (wdata[5:3] == 3'b001);
rindex_latch[3] <= (wdata[5:3] == 3'b001);
end
end
end
@@ -173,7 +179,7 @@ module scc(input sysclk,
/* WR1
* Reset: bit 5 and 2 unchanged */
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr1_a <= 0;
else begin
@@ -183,7 +189,7 @@ module scc(input sysclk,
wr1_a <= wdata;
end
end
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr1_b <= 0;
else begin
@@ -197,7 +203,7 @@ module scc(input sysclk,
/* WR2
* Reset: unchanged
*/
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr2 <= 0;
else if ((wreg_a || wreg_b) && rindex == 2)
@@ -207,7 +213,7 @@ module scc(input sysclk,
/* WR3
* Reset: bit 0 to 0, otherwise unchanged.
*/
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr3_a <= 0;
else begin
@@ -217,7 +223,7 @@ module scc(input sysclk,
wr3_a <= wdata;
end
end
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr3_b <= 0;
else begin
@@ -231,7 +237,7 @@ module scc(input sysclk,
/* WR4
* Reset: Bit 2 to 1, otherwise unchanged
*/
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr4_a <= 0;
else begin
@@ -241,7 +247,7 @@ module scc(input sysclk,
wr4_a <= wdata;
end
end
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr4_b <= 0;
else begin
@@ -255,7 +261,7 @@ module scc(input sysclk,
/* WR5
* Reset: Bits 7,4,3,2,1 to 0
*/
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr5_a <= 0;
else begin
@@ -265,7 +271,7 @@ module scc(input sysclk,
wr5_a <= wdata;
end
end
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr5_b <= 0;
else begin
@@ -279,13 +285,13 @@ module scc(input sysclk,
/* WR6
* Reset: Unchanged.
*/
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr6_a <= 0;
else if (wreg_a && rindex == 6)
wr6_a <= wdata;
end
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr6_b <= 0;
else if (wreg_b && rindex == 6)
@@ -295,13 +301,13 @@ module scc(input sysclk,
/* WR7
* Reset: Unchanged.
*/
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr7_a <= 0;
else if (wreg_a && rindex == 7)
wr7_a <= wdata;
end
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr7_b <= 0;
else if (wreg_b && rindex == 7)
@@ -311,7 +317,7 @@ module scc(input sysclk,
/* WR9. Special: top bits are reset, handled separately, bottom
* bits are only reset by a hw reset
*/
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr9 <= 0;
else if ((wreg_a || wreg_b) && rindex == 9)
@@ -321,7 +327,7 @@ module scc(input sysclk,
/* WR10
* Reset: all 0, except chanel reset retains 6 and 5
*/
always@(posedge sysclk or posedge reset) begin
always@(negedge sysclk or posedge reset) begin
if (reset)
wr10_a <= 0;
else begin
@@ -331,7 +337,7 @@ module scc(input sysclk,
wr10_a <= wdata;
end
end
always@(posedge sysclk or posedge reset) begin
always@(negedge sysclk or posedge reset) begin
if (reset)
wr10_b <= 0;
else begin
@@ -345,13 +351,13 @@ module scc(input sysclk,
/* WR11
* Reset: On full reset only, not channel reset
*/
always@(posedge sysclk or posedge reset) begin
always@(negedge sysclk or posedge reset) begin
if (reset)
wr11_a <= 8'b00001000;
else if (wreg_a && rindex == 11)
wr11_a <= wdata;
end
always@(posedge sysclk or posedge reset) begin
always@(negedge sysclk or posedge reset) begin
if (reset)
wr11_b <= 8'b00001000;
else if (wreg_b && rindex == 11)
@@ -361,13 +367,13 @@ module scc(input sysclk,
/* WR12
* Reset: Unchanged
*/
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr12_a <= 0;
else if (wreg_a && rindex == 12)
wr12_a <= wdata;
end
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr12_b <= 0;
else if (wreg_b && rindex == 12)
@@ -377,13 +383,13 @@ module scc(input sysclk,
/* WR13
* Reset: Unchanged
*/
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr13_a <= 0;
else if (wreg_a && rindex == 13)
wr13_a <= wdata;
end
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr13_b <= 0;
else if (wreg_b && rindex == 13)
@@ -395,7 +401,7 @@ module scc(input sysclk,
* Chan reset also maitains bottom 2 bits, bit 4 also
* reset to a different value
*/
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr14_a <= 0;
else begin
@@ -407,7 +413,7 @@ module scc(input sysclk,
wr14_a <= wdata;
end
end
always@(posedge sysclk or posedge reset_hw) begin
always@(negedge sysclk or posedge reset_hw) begin
if (reset_hw)
wr14_b <= 0;
else begin
@@ -421,17 +427,14 @@ module scc(input sysclk,
end
/* WR15 */
always@(posedge sysclk or posedge reset) begin
if (reset)
always@(negedge sysclk or posedge reset) begin
if (reset) begin
wr15_a <= 8'b11111000;
else if (wreg_a && rindex == 15)
wr15_a <= wdata;
end
always@(posedge sysclk or posedge reset) begin
if (reset)
wr15_b <= 8'b11111000;
else if (wreg_b && rindex == 15)
wr15_b <= wdata;
end else if (rindex == 15) begin
if(wreg_a) wr15_a <= wdata;
if(wreg_b) wr15_b <= wdata;
end
end
/* Read data mux */

20
cores/plus_too/sdram.v
View File

@@ -33,7 +33,7 @@ module sdram (
// cpu/chipset interface
input init, // init signal after FPGA config to initialize RAM
input clk_128, // sdram is accessed at 128MHz
input clk_64, // sdram is accessed at 64MHz
input clk_8, // 8MHz chipset clock to which sdram state machine is synchonized
input [15:0] din, // data input from chipset/cpu
@@ -44,7 +44,7 @@ module sdram (
input we // cpu/chipset requests write
);
localparam RASCAS_DELAY = 3'd3; // tRCD=20ns -> 3 cycles@128MHz
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 3 cycles@128MHz
localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd3; // 2/3 allowed
@@ -61,20 +61,20 @@ localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, B
// The state machine runs at 128Mhz synchronous to the 8 Mhz chipset clock.
// It wraps from T15 to T0 on the rising edge of clk_8
localparam STATE_FIRST = 4'd0; // first state in cycle
localparam STATE_CMD_START = 4'd1; // state in which a new command can be started
localparam STATE_FIRST = 3'd0; // first state in cycle
localparam STATE_CMD_START = 3'd1; // state in which a new command can be started
localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY; // command can be continued
localparam STATE_READ = STATE_CMD_CONT + CAS_LATENCY + 4'd1;
localparam STATE_LAST = 4'd15; // last state in cycle
localparam STATE_LAST = 3'd7; // last state in cycle
reg [3:0] t;
always @(posedge clk_128) begin
reg [2:0] t;
always @(posedge clk_64) begin
// 128Mhz counter synchronous to 8 Mhz clock
// force counter to pass state 0 exactly after the rising edge of clk_8
if(((t == STATE_LAST) && ( clk_8 == 0)) ||
((t == STATE_FIRST) && ( clk_8 == 1)) ||
((t != STATE_LAST) && (t != STATE_FIRST)))
t <= t + 4'd1;
t <= t + 3'd1;
end
// ---------------------------------------------------------------------
@@ -84,7 +84,7 @@ end
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
reg [4:0] reset;
always @(posedge clk_128) begin
always @(posedge clk_64) begin
if(init) reset <= 5'h1f;
else if((t == STATE_LAST) && (reset != 0))
reset <= reset - 5'd1;
@@ -117,7 +117,7 @@ assign sd_we = sd_cmd[0];
assign sd_data = we?din:16'bZZZZZZZZZZZZZZZZ;
assign dout = sd_data;
always @(posedge clk_128) begin
always @(posedge clk_64) begin
sd_cmd <= CMD_INHIBIT; // default: idle
if(reset != 0) begin

134
cores/plus_too/via.v
View File

@@ -117,7 +117,12 @@ module via(
output _irq,
output [15:0] dataOut,
output memoryOverlayOn,
output SEL // to IWM
output SEL, // to IWM
input [7:0] kbd_in_data,
input kbd_in_strobe,
output [7:0] kbd_out_data,
output reg kbd_out_strobe
);
wire [7:0] dataInHi = dataIn[15:8];
@@ -130,12 +135,44 @@ module via(
reg [6:0] viaIFR;
reg [6:0] viaIER;
reg [7:0] viaACR;
reg [7:0] viaSR;
reg [15:0] viaTimer1Count;
reg [15:0] viaTimer1Latch;
reg [15:0] viaTimer2Count;
reg [7:0] viaTimer2LatchLow;
reg viaTimer2Armed;
// shift register can be written by CPU and by external source
/* Write to SR (including external input) */
assign kbd_out_data = viaSR;
always @(negedge clk8 or negedge _reset) begin
if (_reset == 1'b0)
viaSR <= 8'b0;
else begin
if((selectVIA == 1'b1) && (_cpuUDS == 1'b0) &&
(_cpuRW == 1'b0) && (cpuAddrRegHi == 4'hA))
viaSR <= dataInHi;
if (viaACR[4:2] == 3'b011 && kbd_in_strobe)
viaSR <= kbd_in_data;
end
end
/* Generate sr_out_strobe */
always @(negedge clk8 or negedge _reset) begin
if (_reset == 1'b0)
kbd_out_strobe <= 1'b0;
else begin
if((selectVIA == 1'b1) && (_cpuUDS == 1'b0) &&
(_cpuRW == 1'b0) && (cpuAddrRegHi == 4'hA) &&
(viaACR[4:2] == 3'b111))
kbd_out_strobe <= 1;
else
kbd_out_strobe <= 0;
end
end
// divide by 10 clock divider for the VIA timers: 0.78336 MHz
reg [3:0] clkDiv;
always @(posedge clk8) begin
@@ -148,13 +185,13 @@ module via(
// store previous vblank value, for edge detection
reg _lastVblank;
always @(posedge clk8) begin
always @(negedge clk8) begin
_lastVblank <= _vblank;
end
// count vblanks, and set 1 second interrupt after 60 vblanks
reg [5:0] vblankCount;
always @(posedge clk8) begin
always @(negedge clk8) begin
if (_vblank == 1'b0 && _lastVblank == 1'b1) begin
if (vblankCount != 59) begin
vblankCount <= vblankCount + 1'b1;
@@ -168,7 +205,7 @@ module via(
// register write
wire loadT2 = selectVIA == 1'b1 && _cpuUDS == 1'b0 && _cpuRW == 1'b0 && cpuAddrRegHi == 4'h9;
always @(posedge clk8 or negedge _reset) begin
always @(negedge clk8 or negedge _reset) begin
if (_reset == 1'b0) begin
viaB0DDR <= 1'b1;
viaADataOut <= 8'b01111111;
@@ -183,6 +220,8 @@ module via(
viaTimer2Armed <= 0;
end
else begin
// kbd_out_strobe <= 1'b0;
if (selectVIA == 1'b1 && _cpuUDS == 1'b0) begin
if (_cpuRW == 1'b0) begin
// normal register writes
@@ -208,6 +247,10 @@ module via(
viaTimer2Armed = 1'b1;
viaIFR[`INT_T2] <= 1'b0;
end
4'hA: begin // shift register
if( viaACR[4:2] == 3'b111 )
viaIFR[`INT_KEYREADY] <= 1'b1;
end
4'hB: // Aux control register
viaACR <= dataInHi;
// 4'hC: ignore PCR
@@ -231,6 +274,8 @@ module via(
end
4'h8: // reading T2C-L clears the T2 interrupt flag
viaIFR[`INT_T2] <= 1'b0;
4'hA: // reading SR clears the SR interrupt flag
viaIFR[`INT_KEYREADY] <= 1'b0;
4'hF: begin // reading (and writing?) register A clears VBLANK and ONESEC interrupt flags
viaIFR[`INT_ONESEC] <= 1'b0;
viaIFR[`INT_VBLANK] <= 1'b0;
@@ -252,49 +297,54 @@ module via(
end
viaTimer2Count <= viaTimer2Count - 1'b1;
end
// Shift in under control of external clock
if (viaACR[4:2] == 3'b011 && kbd_in_strobe)
viaIFR[`INT_KEYREADY] <= 1;
end
end
// register read
always @(*) begin
dataOutHi = 8'hBE;
if (_cpuRW == 1'b1 && selectVIA == 1'b1 && _cpuUDS == 1'b0) begin
case (cpuAddrRegHi)
4'h0: // B
// TODO: clear CB1 and CB2 interrupts
dataOutHi = { viaBDataOut[7], ~_hblank, mouseY2, mouseX2, mouseButton, viaBDataOut[2:1], viaB0DDR == 1'b1 ? viaBDataOut[0] : rtcData };
4'h2: // B DDR
dataOutHi = { 7'b1000011, viaB0DDR };
4'h3: // A DDR
dataOutHi = 8'b01111111;
4'h4: // timer 1 count low
dataOutHi = viaTimer1Count[7:0];
4'h5: // timer 1 count high
dataOutHi = viaTimer1Count[15:8];
4'h6: // timer 1 latch low
dataOutHi = viaTimer1Latch[7:0];
4'h7: // timer 1 latch high
dataOutHi = viaTimer1Latch[15:8];
4'h8: // timer 2 count low
dataOutHi = viaTimer2Count[7:0];
4'h9: // timer 2 count high
dataOutHi = viaTimer2Count[15:8];
4'hB: // Aux control register
dataOutHi = viaACR;
4'hC: // PCR
dataOutHi = 0;
4'hD: // IFR
dataOutHi = { viaIFR & viaIER == 0 ? 1'b0 : 1'b1, viaIFR };
4'hE: // IER
dataOutHi = { 1'b1, viaIER };
4'hF: // A
// TODO: clear CA1 and CA2 interrupts
dataOutHi = { sccWReq, viaADataOut[6:0] };
default:
dataOutHi = 8'hBE;
endcase
end
case (cpuAddrRegHi)
4'h0: // B
// TODO: clear CB1 and CB2 interrupts
dataOutHi = { viaBDataOut[7], ~_hblank, mouseY2, mouseX2, mouseButton, viaBDataOut[2:1], viaB0DDR == 1'b1 ? viaBDataOut[0] : rtcData };
4'h2: // B DDR
dataOutHi = { 7'b1000011, viaB0DDR };
4'h3: // A DDR
dataOutHi = 8'b01111111;
4'h4: // timer 1 count low
dataOutHi = viaTimer1Count[7:0];
4'h5: // timer 1 count high
dataOutHi = viaTimer1Count[15:8];
4'h6: // timer 1 latch low
dataOutHi = viaTimer1Latch[7:0];
4'h7: // timer 1 latch high
dataOutHi = viaTimer1Latch[15:8];
4'h8: // timer 2 count low
dataOutHi = viaTimer2Count[7:0];
4'h9: // timer 2 count high
dataOutHi = viaTimer2Count[15:8];
4'hA: // shift register
dataOutHi = viaSR;
4'hB: // Aux control register
dataOutHi = viaACR;
4'hC: // PCR
dataOutHi = 0;
4'hD: // IFR
dataOutHi = { viaIFR & viaIER == 0 ? 1'b0 : 1'b1, viaIFR };
4'hE: // IER
dataOutHi = { 1'b1, viaIER };
4'hF: // A
// TODO: clear CA1 and CA2 interrupts
dataOutHi = { sccWReq, viaADataOut[6:0] };
default:
dataOutHi = 8'hBE;
endcase
end
assign memoryOverlayOn = viaADataOut[4];