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140 lines
3.2 KiB
Verilog
140 lines
3.2 KiB
Verilog
module mfp_timer(
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input CLK,
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input RST,
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input DAT_WE,
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input [7:0] DAT_I,
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output [7:0] DAT_O,
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input CTRL_WE,
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input [4:0] CTRL_I,
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output [4:0] CTRL_O,
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inout XCLK_I,
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input T_I, // ext. trigger in
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output reg T_O,
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output reg T_O_PULSE
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);
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reg [7:0] data, down_counter, cur_counter;
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reg [3:0] control;
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wire[7:0] prescaler; // prescaler value
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reg [7:0] prescaler_counter; // prescaler counter
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reg count;
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wire started;
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wire delay_mode;
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wire event_mode;
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wire pulse_mode;
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// trigger edge detect registers
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reg trigger_r, trigger_r2;
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// async clock edge detect
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reg xclk_r, xclk_r2;
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// counters work on the negative clock edge. we latch them
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// on the positive edge for stable cpu read
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always @(posedge CLK)
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cur_counter <= down_counter;
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// generate clock from async clock input
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always @(posedge XCLK_I) begin
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if(RST === 1'b1)
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prescaler_counter <= 8'd0;
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else begin
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if(prescaler_counter >= prescaler)
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prescaler_counter <= 8'd0;
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else
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prescaler_counter <= prescaler_counter + 8'd1;
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end
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end
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always @(negedge CLK) begin
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if (RST === 1'b1) begin
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T_O_PULSE <= 1'b0;
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T_O <= 1'b0;
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control <= 4'd0;
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data <= 8'd0;
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down_counter <= 8'd0;
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count <= 1'b0;
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end else begin
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// bring trigger/xclk edges into our clock domain.
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trigger_r <= T_I;
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trigger_r2 <= trigger_r;
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xclk_r <= (prescaler_counter === 8'd0);
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xclk_r2 <= xclk_r;
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T_O_PULSE <= 1'b0;
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// if a write request comes from the main unit
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// then write the data to the appropriate register.
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if(DAT_WE) begin
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data <= DAT_I;
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down_counter <= DAT_I;
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end
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if(CTRL_WE) begin
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control <= CTRL_I[3:0];
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if (CTRL_I[4] == 1'b1)
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T_O <= 1'b0;
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end
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if (started) begin
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count <= 1'b0;
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// handle event mode
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if (event_mode === 1'b1)
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if ((~trigger_r2 & trigger_r) === 1'b1)
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count <= 1'b1;
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// handle delay mode
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if (delay_mode === 1'b1)
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if ((~xclk_r2 & xclk_r) === 1'b1)
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count <= 1'b1;
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if (count) begin
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// timeout pulse
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if (down_counter === 8'd1) begin
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// pulse the timer out
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T_O <= ~T_O;
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down_counter <= data;
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T_O_PULSE <= 1'b1;
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end else begin
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down_counter <= down_counter - 8'd1;
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end
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end
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end
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end
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end
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assign prescaler = control[2:0] === 3'd1 ? 8'd04 :
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control[2:0] === 3'd2 ? 8'd10 :
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control[2:0] === 3'd3 ? 8'd16 :
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control[2:0] === 3'd4 ? 8'd50 :
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control[2:0] === 3'd5 ? 8'd64 :
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control[2:0] === 3'd6 ? 8'd100 :
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control[2:0] === 3'd7 ? 8'd200 : 8'd1;
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assign delay_mode = control[3] === 1'b0;
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assign pulse_mode = control[3] === 1'b1 & !event_mode;
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assign event_mode = control[3:0] === 4'b1000;
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assign started = control[3:0] != 4'd0;
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assign DAT_O = cur_counter;
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assign CTRL_O = {T_O, control};
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endmodule // mfp_timer
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