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70 lines
2.4 KiB
Verilog
70 lines
2.4 KiB
Verilog
/* blockram.v
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Copyright (c) 2012-2015, Stephen J. Leary
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the <organization> nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module blockram #
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(
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parameter init_file = "UNUSED",
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parameter mem_size = 8
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)
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(
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input clka,
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input [3:0] wea, // Port A write enable
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input [31:0] dina, // Port A data input
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input [mem_size-1:0] addra, // Port A address input
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output [31:0] douta
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);
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reg [mem_size-1:0] addra_latched;
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reg [31:0] mem_data [0:(1<<mem_size)-1];
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initial
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begin
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if (init_file != "UNUSED") begin
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$readmemh(init_file, mem_data);
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end
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end
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always @(posedge clka)
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begin
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addra_latched <= addra;
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if (wea[0])
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mem_data[addra][7:0] <= dina[7:0];
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if (wea[1])
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mem_data[addra][15:8] <= dina[15:8];
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if (wea[2])
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mem_data[addra][23:16] <= dina[23:16];
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if (wea[3])
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mem_data[addra][31:24] <= dina[31:24];
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end
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assign douta = mem_data[addra_latched];
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endmodule // ALTERA_MF_MEMORY_INITIALIZATION
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