Gyorgy Szombathelyi 42a828913f Archie: register some SDRAM signals for better timing properties

2019-11-02 18:59:56 +01:00

..

amber

Adding the achie source code.

2016-05-23 17:05:43 +01:00

i2cslave

[Archie] Add CMOS RAM upload

2019-03-02 22:47:58 +01:00

sdram

Archie: register some SDRAM signals for better timing properties

2019-11-02 18:59:56 +01:00

archimedes_top.v

[Archie] Risc Developments IDE interface

2019-11-02 18:59:34 +01:00

blockram.v

removed the unused uart.

2016-05-23 20:23:21 +01:00

fdc1772.v

Archie: common FDC with the ST core

2019-10-18 19:54:03 +02:00

floppy.v

Archie: common FDC with the ST core

2019-10-18 19:54:03 +02:00

ide.sv

[Archie] Risc Developments IDE interface

2019-11-02 18:59:34 +01:00

ioc_irq.v

Adding the achie source code.

2016-05-23 17:05:43 +01:00

ioc.v

Archie: reduce clock to 40MHz

2019-10-18 20:39:40 +02:00

latches.v

[Archie] Silence warnings

2019-03-05 15:57:36 +01:00

memc_translator.v

Adding the achie source code.

2016-05-23 17:05:43 +01:00

memc.v

Revert "Archie: 128bit SDRAM interface (by Sorgelig)"

2019-10-19 23:30:50 +02:00

podules.v

[Archie] Risc Developments IDE interface

2019-11-02 18:59:34 +01:00

por.v

removed the unused uart.

2016-05-23 20:23:21 +01:00

riscdevide_rom.hex

[Archie] Risc Developments IDE interface

2019-11-02 18:59:34 +01:00

vidc_audio.v

[Archie] Use only one clock in vidc (port from MiSTer)

2019-02-08 12:32:34 +01:00

vidc_dcfifo.qip

Archie: replace vidc fifo with DCFIFO component to fix clock domain crossing issues

2019-10-19 17:17:17 +02:00

vidc_dcfifo.v

Archie: replace vidc fifo with DCFIFO component to fix clock domain crossing issues

2019-10-19 17:17:17 +02:00

vidc_dmachannel.v

Archie: use 2 deterministic places for requesting new data in VIDC

2019-10-22 19:57:08 +02:00

vidc_mulaw.mif

Adding the achie source code.

2016-05-23 17:05:43 +01:00

vidc_timing.v

Archie: vidc flybk should be active after the end of the display

2019-10-22 19:57:08 +02:00

vidc.v

Archie: don't consume new pixel data during hsync

2019-10-22 19:57:08 +02:00