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29 lines
421 B
Verilog
29 lines
421 B
Verilog
module mmu (
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// cpu register interface
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input clk,
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input reset,
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input [7:0] din,
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input sel,
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input ds,
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input rw,
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output reg [7:0] dout
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);
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reg [7:0] memconfig;
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always @(sel, ds, rw, memconfig) begin
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dout = 8'd0;
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if(sel && ~ds && rw)
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dout = memconfig;
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end
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always @(negedge clk) begin
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if(reset)
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memconfig <= 8'h00;
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else begin
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if(sel && ~ds && ~rw)
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memconfig <= din;
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end
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end
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endmodule |