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57 lines
1.0 KiB
Verilog
57 lines
1.0 KiB
Verilog
module psg (
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// cpu register interface
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input clk,
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input reset,
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input [7:0] din,
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input sel,
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input [7:0] addr,
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input ds,
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input rw,
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output reg [7:0] dout,
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output dtack,
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output drv_side,
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output [1:0] drv_sel
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);
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// port a is partly used to select the floppy
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assign drv_side = port_a[0];
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assign drv_sel = { port_a[2], port_a[1] };
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// ------------------ cpu interface --------------------
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reg [7:0] port_a;
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reg [3:0] reg_sel;
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// dtack
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assign dtack = sel;
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always @(sel, ds, rw, addr) begin
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dout = 8'h00;
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if(sel && ~ds && rw) begin
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// read from selected register
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if(addr == 8'h00 && reg_sel == 4'd14)
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dout = port_a;
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end
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end
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always @(negedge clk) begin
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if(reset) begin
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reg_sel <= 4'd0;
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port_a <= 8'd0;
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end else begin
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// keyboard acia data register writes into buffer
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if(sel && ~ds && ~rw) begin
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// register select
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if(addr == 8'h00)
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reg_sel <= din[3:0];
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// write to selected register
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if(addr == 8'h02 && reg_sel == 4'd14)
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port_a <= din;
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end
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end
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end
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endmodule |