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Gyorgy Szombathelyi d774f5356b [Archie] Adjust SDRAM simulation

2019-03-07 15:33:15 +01:00

..

adding support files and adding testbench boilerplates

2016-05-23 20:32:57 +01:00

updating some make files

2016-05-23 18:33:09 +01:00

adding support files and adding testbench boilerplates

2016-05-23 20:32:57 +01:00

[Archie] Adjust SDRAM simulation

2019-03-07 15:33:15 +01:00

updates for boilerplates

2016-05-23 20:39:26 +01:00

[Archie] Adjust SDRAM simulation

2019-03-07 15:33:15 +01:00

updates for boilerplates

2016-05-23 20:39:26 +01:00

Adding the achie source code.

2016-05-23 17:05:43 +01:00

starting to cleanup the tests

2016-05-23 18:31:00 +01:00

default.mk

adding the sdram model.

2016-05-23 18:51:00 +01:00

README.txt

starting to cleanup the tests

2016-05-23 18:31:00 +01:00

README.txt

This is the testbench code that runs tests and simulations of various bits of the the the rtl.

This still needs A LOT of tidy up.This is a set of tests that will verify various aspects of the archimedes core.