Gyorgy Szombathelyi 9b19a1f1b8 [Archie] Smart precharge for SDRAM

2019-03-08 01:11:47 +01:00

..

amber

Adding the achie source code.

2016-05-23 17:05:43 +01:00

i2cslave

[Archie] Add CMOS RAM upload

2019-03-02 22:47:58 +01:00

sdram

[Archie] Smart precharge for SDRAM

2019-03-08 01:11:47 +01:00

archimedes_top.v

[Archie] Use standard IO for FDC with full read/write support

2019-03-02 16:43:56 +01:00

blockram.v

removed the unused uart.

2016-05-23 20:23:21 +01:00

fdc1772.v

[Archie] Increase the CPU clock to 42MHz

2019-03-05 23:04:43 +01:00

floppy.v

[Archie] Silence warnings

2019-03-05 15:57:36 +01:00

ioc_irq.v

Adding the achie source code.

2016-05-23 17:05:43 +01:00

ioc.v

[Archie] Increase the CPU clock to 42MHz

2019-03-05 23:04:43 +01:00

latches.v

[Archie] Silence warnings

2019-03-05 15:57:36 +01:00

memc_translator.v

Adding the achie source code.

2016-05-23 17:05:43 +01:00

memc.v

[Archie] Silence warnings

2019-03-05 15:57:36 +01:00

podules.v

removed the unused uart.

2016-05-23 20:23:21 +01:00

por.v

removed the unused uart.

2016-05-23 20:23:21 +01:00

vidc_audio.v

[Archie] Use only one clock in vidc (port from MiSTer)

2019-02-08 12:32:34 +01:00

vidc_dmachannel.v

[Archie] Synchronize reset signals in VIDC

2019-02-24 03:13:15 +01:00

vidc_fifo.v

[Archie] Synchronize reset signals in VIDC

2019-02-24 03:13:15 +01:00

vidc_mulaw.mif

Adding the achie source code.

2016-05-23 17:05:43 +01:00

vidc_timing.v

[Archie] VIDC: there's no horizontal cursor end register

2019-03-05 13:40:48 +01:00

vidc.v

[Archie] Use only one clock in vidc (port from MiSTer)

2019-02-08 12:32:34 +01:00