github.com/olofk.serv
1
0
Fork 0
mirror of https://github.com/olofk/serv.git synced 2026-01-13 15:17:25 +00:00
Code Issues Releases Wiki Activity

Gate mem_misalign in mem_if

Browse Source
This commit is contained in:
Olof Kindgren 2019-09-26 23:23:42 +02:00
parent 5b96b3a938
commit 0f767ad2d3
3 changed files with 11 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
rtl/serv_mem_if.v
View File

@ -5,6 +5,7 @@ module serv_mem_if
input wire i_rst,
input wire i_en,
input wire i_init,
input wire i_mem_op,
input wire i_signed,
input wire i_word,
input wire i_half,
@ -12,7 +13,7 @@ module serv_mem_if
input wire i_rs2,
output wire o_rd,
input wire [1:0] i_lsb,
output reg o_misalign,
output wire o_misalign,
//External interface
output wire [31:0] o_wb_dat,
output wire [3:0] o_wb_sel,
@ -20,6 +21,7 @@ module serv_mem_if
input wire i_wb_ack);
reg signbit;
reg misalign;
reg [7:0] dat0;
reg [7:0] dat1;
@ -59,6 +61,8 @@ module serv_mem_if
assign o_wb_dat = {dat3,dat2,dat1,dat0};
assign o_misalign = misalign & i_mem_op;
always @(posedge i_clk) begin
if (dat0_en)
@ -73,7 +77,7 @@ module serv_mem_if
if (i_wb_ack)
{dat3,dat2,dat1,dat0} <= i_wb_rdt;
o_misalign <= (i_lsb[0] & (i_word | i_half)) | (i_lsb[1] & i_word);
misalign <= (i_lsb[0] & (i_word | i_half)) | (i_lsb[1] & i_word);
if (dat_valid)
signbit <= dat_cur;

8
rtl/serv_state.v
View File

@ -72,11 +72,9 @@ module serv_state
//slt*, branch/jump, shift, load/store
wire two_stage_op = i_slt_op | i_mem_op | i_branch_op | i_shift_op;
wire mem_misalign = i_mem_op & i_mem_misalign;
always @(posedge i_clk) begin
o_csr_mcause[3:0] <= 4'd0;
if (mem_misalign)
if (i_mem_misalign)
o_csr_mcause[3:0] <= {2'b01, i_mem_cmd, 1'b0};
if (i_e_op)
o_csr_mcause <= {!i_ebreak,3'b011};
@ -86,9 +84,9 @@ module serv_state
reg pending_irq;
assign o_dbus_cyc = (state == IDLE) & stage_two_pending & i_mem_op & !mem_misalign;
assign o_dbus_cyc = (state == IDLE) & stage_two_pending & i_mem_op & !i_mem_misalign;
wire trap_pending = (o_ctrl_jump & i_ctrl_misalign) | mem_misalign;
wire trap_pending = (o_ctrl_jump & i_ctrl_misalign) | i_mem_misalign;
//Prepare RF for reads when a new instruction is fetched
// or when stage one caused an exception (rreq implies a write request too)

3
rtl/serv_top.v
View File

@ -322,7 +322,7 @@ module serv_top
.i_trap (trap),
.i_mret (mret),
.i_mepc (o_ibus_adr[0]),
.i_mtval ((mem_misalign & mem_op) ? bufreg_q : bad_pc),
.i_mtval (mem_misalign ? bufreg_q : bad_pc),
.o_csr_pc (csr_pc),
//CSR write port
.i_csr_en (csr_en),
@ -351,6 +351,7 @@ module serv_top
.i_rst (i_rst),
.i_en (cnt_en),
.i_init (init),
.i_mem_op (mem_op),
.i_signed (mem_signed),
.i_word (mem_word),
.i_half (mem_half),