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Add Arty S7-50 support

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This commit is contained in:
Calder Coalson
2023-06-14 08:15:57 -07:00
committed by Olof Kindgren
parent d4491f1060
commit 1268538f9d
3 changed files with 32 additions and 0 deletions
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data/arty_s7_50t.xdc Normal file
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set_property -dict { PACKAGE_PIN R2 IOSTANDARD SSTL135 } [get_ports i_clk]; #IO_L12P_T1_MRCC_34 Sch=ddr3_clk[200]
set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports i_rst_n]; #IO_L11N_T1_SRCC_15
set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports q]; #IO_25_14 Sch=uart_rxd_out
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports q]; #IO_L16N_T2_A27_15 Sch=led[2]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports i_clk];